2026-03-06 01:31:22.626 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.59.20:5700'
2026-03-06 01:31:22.626 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.59.20:5802)
2026-03-06 01:31:22.626 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.59.20:5801)
2026-03-06 01:31:22.626 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.59.22:6700'
2026-03-06 01:31:22.626 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.59.22:6802)
2026-03-06 01:31:22.626 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.59.22:6801)
2026-03-06 01:31:22.626 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.59.20:5700/1'
2026-03-06 01:31:22.626 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.59.20:5804)
2026-03-06 01:31:22.626 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.59.20:5803)
2026-03-06 01:31:22.626 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.59.20:5700/2'
2026-03-06 01:31:22.627 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.59.20:5806)
2026-03-06 01:31:22.627 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.59.20:5805)
2026-03-06 01:31:22.627 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.59.20:5700/3'
2026-03-06 01:31:22.627 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.59.20:5808)
2026-03-06 01:31:22.627 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.59.20:5807)
2026-03-06 01:31:22.627 [INFO] fake_trx.py:429 Init complete
2026-03-06 01:31:22.627 [INFO] fake_trx.py:460 Setting real time process scheduler to SCHED_RR, priority 30
2026-03-06 01:31:23.175 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:31:23.175 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:31:23.175 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:31:23.176 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:31:23.176 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:31:23.176 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:31:27.179 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:31:27.181 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:31:27.181 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:31:27.181 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:31:27.182 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 0 -> 1
2026-03-06 01:31:27.188 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:31:27.189 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:31:27.189 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:31:27.189 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:31:27.189 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:31:27.190 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:31:27.190 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:31:27.190 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 0 -> 1
2026-03-06 01:31:27.190 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:31:27.196 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:31:27.196 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:31:27.196 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:31:27.196 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:31:27.196 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:31:27.197 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:31:27.197 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:31:27.197 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 0 -> 1
2026-03-06 01:31:27.197 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:31:27.203 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:31:27.203 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:31:27.203 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:31:27.203 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:31:27.203 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:31:27.204 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:31:27.204 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:31:27.204 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 0 -> 1
2026-03-06 01:31:27.204 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:31:27.208 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:31:27.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:31:27.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:31:27.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:31:27.208 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:31:27.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:31:27.209 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:31:27.209 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:31:27.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:31:27.209 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:31:27.209 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:31:27.209 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:31:27.210 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:31:27.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:27.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:31:27.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:31:27.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:27.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:27.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:31:27.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:27.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:27.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:27.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:27.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:27.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:27.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:27.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:27.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:27.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:27.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:27.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:27.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:27.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:27.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:27.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:27.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:27.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:27.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:27.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:27.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:27.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:27.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:27.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:27.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:27.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:27.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:27.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:27.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:27.214 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:31:27.692 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:31:27.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:27.749 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:31:27.751 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:31:27.752 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:31:27.761 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:27.761 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:27.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:31:27.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:27.764 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:27.764 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:27.764 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:31:27.764 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:31:27.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:27.964 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:27.965 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:27.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:27.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:28.164 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:31:28.215 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:31:28.216 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:31:28.216 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:31:28.216 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:31:28.364 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:28.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:28.368 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:28.368 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:28.378 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:28.378 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:28.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:31:28.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:28.379 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:28.379 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:28.379 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:31:28.379 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:31:28.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:28.462 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:28.463 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:28.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:28.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:28.635 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:31:28.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:28.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:28.858 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:28.858 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:28.867 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:28.867 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:28.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:31:28.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:28.868 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:28.868 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:28.868 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:31:28.868 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:31:28.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:29.106 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:31:29.141 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:29.142 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:29.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:29.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:29.216 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:31:29.216 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:31:29.217 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:31:29.217 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:31:29.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:29.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:29.546 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:29.546 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:29.565 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:29.566 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:29.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:31:29.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:29.568 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:29.568 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:29.568 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:31:29.568 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:31:29.577 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:31:29.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:29.639 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:29.640 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:29.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:29.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:30.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:30.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:30.034 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:30.034 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:30.044 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:30.045 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:30.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:31:30.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:30.046 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:30.046 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:30.047 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:31:30.047 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:31:30.047 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:31:30.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:30.216 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:31:30.217 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:31:30.218 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:31:30.218 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:31:30.318 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:30.318 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:30.318 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:30.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:30.519 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:31:30.992 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:31:31.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:31.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:31.054 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:31.055 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:31.072 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:31.072 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:31.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:31:31.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:31.074 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:31.074 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:31.074 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:31:31.074 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:31:31.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:31.217 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:31:31.219 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:31:31.219 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:31:31.219 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:31:31.260 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:31.260 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:31.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:31.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:31.465 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:31:31.937 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:31:32.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:32.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:32.081 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:32.081 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:32.098 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:32.098 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:32.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:31:32.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:32.100 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:32.100 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:32.100 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:31:32.100 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:31:32.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:32.207 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:32.208 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:32.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:32.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:32.408 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:31:32.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:32.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:32.621 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:32.621 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:32.634 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:32.634 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:32.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:31:32.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:32.635 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:32.635 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:32.635 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:31:32.635 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:31:32.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:32.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:32.706 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:32.706 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:32.706 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:32.706 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:32.881 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:31:33.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:33.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:33.162 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:33.163 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:33.181 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:33.181 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:33.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:31:33.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:33.183 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:33.183 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:33.183 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:31:33.183 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:31:33.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:33.354 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:31:33.390 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:33.391 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:33.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:33.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:33.826 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:31:34.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:34.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:34.186 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:34.186 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:34.205 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:34.205 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:34.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:31:34.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:34.206 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:34.207 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:34.207 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:31:34.207 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:31:34.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:34.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:34.297 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:31:34.332 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:34.332 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:34.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:34.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:34.770 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:31:35.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:35.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:35.088 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:35.088 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:35.103 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:35.103 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:35.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:31:35.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:35.105 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:35.105 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:35.105 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:31:35.105 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:31:35.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:35.243 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:31:35.278 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:35.279 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:35.279 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:35.279 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:35.715 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:31:36.048 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:36.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:36.053 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:36.053 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:36.071 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:36.071 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:36.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:31:36.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:36.073 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:36.073 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:36.074 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:31:36.074 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:31:36.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:36.187 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:31:36.220 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:36.221 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:36.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:36.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:36.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:36.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:36.592 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:36.592 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:36.613 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:36.613 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:36.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:31:36.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:36.615 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:36.615 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:36.615 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:31:36.615 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:31:36.660 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:31:36.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:36.723 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:36.724 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:36.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:36.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:36.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:36.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:36.820 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:36.821 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:36.840 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:36.840 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:36.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:31:36.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:36.842 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:36.842 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:36.842 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:31:36.842 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:31:36.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:36.959 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:36.960 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:36.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:36.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:37.132 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:31:37.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:37.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:37.308 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:37.309 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:37.327 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:37.327 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:37.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:31:37.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:37.329 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:37.329 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:37.329 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:31:37.329 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:31:37.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:37.430 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:37.430 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:37.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:37.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:37.603 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:31:37.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:37.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:37.798 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:37.798 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:37.807 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:37.807 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:37.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:31:37.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:37.808 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:37.808 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:37.809 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:31:37.809 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:31:37.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:37.901 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:37.901 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:37.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:37.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:38.074 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:31:38.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:38.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:38.287 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:38.287 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:38.296 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:38.296 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:38.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:31:38.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:38.298 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:38.298 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:38.298 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:31:38.298 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:31:38.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:38.371 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:38.372 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:38.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:38.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:38.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:38.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:38.467 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:38.467 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:38.486 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:38.486 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:38.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:31:38.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:38.488 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:38.488 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:38.488 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:31:38.488 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:31:38.544 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:31:38.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:38.607 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:38.607 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:38.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:38.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:38.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:38.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:38.956 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:38.957 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:38.975 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:38.975 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:38.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:31:38.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:38.976 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:38.976 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:38.976 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:31:38.976 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:31:39.015 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:31:39.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:39.077 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:39.078 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:39.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:39.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:39.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:39.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:39.446 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:39.446 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:39.462 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:39.462 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:39.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:31:39.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:39.464 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:39.464 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:39.464 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:31:39.464 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:31:39.486 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:31:39.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:39.548 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:31:39.548 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:31:39.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:39.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:39.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:31:39.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:39.935 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:39.935 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:39.946 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:31:39.946 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:31:39.946 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:31:39.946 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:31:39.949 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:31:39.949 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:31:39.949 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:31:39.949 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:31:39.949 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:31:39.949 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:31:39.949 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:31:39.949 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2754 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:31:39.949 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2754 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:31:39.949 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2754 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:31:39.949 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2754 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:31:44.952 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:31:44.952 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:31:44.952 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:31:44.952 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:31:44.952 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:31:44.952 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:31:44.955 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:31:44.955 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:31:44.955 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:31:44.955 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:31:44.955 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:31:44.956 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:31:44.956 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:31:44.956 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:31:44.957 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:31:44.957 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:31:44.957 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:31:44.957 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:31:44.957 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:31:44.957 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:31:44.958 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:31:44.958 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:31:44.958 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:31:44.958 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:31:44.958 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:31:44.958 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:31:44.958 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:31:44.958 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:31:44.958 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:31:44.960 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:31:44.960 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:31:44.960 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:31:44.960 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:31:44.960 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:31:44.960 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:31:44.960 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:31:44.960 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:31:44.960 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:31:44.962 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:31:44.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:31:44.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:31:44.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:31:44.962 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:31:44.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:31:44.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:31:44.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:44.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:31:44.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:31:44.963 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:31:44.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:44.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:44.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:44.963 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:31:44.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:44.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:44.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:44.963 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:31:44.963 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:31:44.963 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:31:44.963 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:31:44.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:44.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:44.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:44.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:31:44.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:44.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:44.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:44.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:44.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:44.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:44.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:44.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:44.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:44.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:44.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:44.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:44.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:44.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:44.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:44.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:44.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:44.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:44.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:44.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:44.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:44.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:44.968 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:31:45.446 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:31:45.491 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:31:45.493 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:31:45.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.496 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:31:45.518 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:45.519 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:45.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:31:45.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:45.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:45.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:45.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:45.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:45.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:45.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:45.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:45.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:45.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.912 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:31:45.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:45.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:45.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.967 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:31:45.967 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:31:45.967 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:31:45.967 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:31:45.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:45.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:45.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:46.377 [DEBUG] clck_gen.py:113 IND CLOCK 306
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2026-03-06 01:31:46.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:46.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:46.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:46.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:46.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:46.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:46.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:46.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:46.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:46.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:46.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.842 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:31:46.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:46.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:46.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:46.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.967 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:31:46.967 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:31:46.967 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:31:46.968 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:31:46.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:46.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:47.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:47.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 01:31:47.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.307 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:31:47.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:47.369 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:31:47.370 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:31:47.370 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:31:47.370 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:31:47.374 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:31:47.374 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:31:47.374 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:31:47.374 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:31:47.374 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:31:47.374 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:31:47.374 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:31:47.374 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=526 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:31:47.374 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=526 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:31:47.374 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=526 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:31:47.374 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=526 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:31:47.374 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=526 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:31:47.374 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=526 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:31:52.376 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:31:52.376 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:31:52.376 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:31:52.376 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:31:52.376 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:31:52.376 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:31:52.384 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:31:52.386 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:31:52.386 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:31:52.386 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:31:52.386 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:31:52.390 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:31:52.390 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:31:52.391 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:31:52.391 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:31:52.391 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:31:52.391 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:31:52.391 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:31:52.391 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:31:52.392 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:31:52.395 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:31:52.395 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:31:52.395 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:31:52.395 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:31:52.396 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:31:52.396 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:31:52.396 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:31:52.396 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:31:52.396 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:31:52.400 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:31:52.400 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:31:52.400 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:31:52.400 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:31:52.400 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:31:52.400 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:31:52.400 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:31:52.400 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:31:52.401 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:31:52.405 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:31:52.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:31:52.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:31:52.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:31:52.405 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:31:52.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:31:52.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:31:52.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:52.406 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:31:52.406 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:31:52.406 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:31:52.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:52.406 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:52.406 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:52.406 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:31:52.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:52.406 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:52.406 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:52.406 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:31:52.406 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:31:52.406 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:31:52.407 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:31:52.407 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:52.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:52.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:52.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:31:52.407 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:52.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:52.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:52.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:52.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:52.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:52.408 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:52.408 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:52.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:52.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:52.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:52.408 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:52.408 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:52.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:52.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:52.408 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:52.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:52.408 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:52.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:52.408 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:52.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:52.408 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:52.411 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:31:52.890 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:31:52.942 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:31:52.945 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:31:52.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:52.947 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:31:52.967 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:52.967 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:52.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:31:52.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:52.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:52.988 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:31:52.989 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:31:52.989 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:31:52.989 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:31:52.992 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:31:52.993 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:31:52.993 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:31:52.993 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:31:52.993 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:31:52.993 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:31:52.993 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:31:52.993 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=126 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:31:52.993 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:31:52.993 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:31:52.994 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:31:52.994 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:31:52.994 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:31:57.995 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:31:57.995 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:31:57.995 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:31:57.995 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:31:57.995 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:31:57.995 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:31:58.003 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:31:58.004 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:31:58.005 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:31:58.005 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:31:58.005 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:31:58.008 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:31:58.009 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:31:58.009 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:31:58.009 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:31:58.009 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:31:58.010 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:31:58.010 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:31:58.010 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:31:58.011 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:31:58.012 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:31:58.012 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:31:58.012 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:31:58.012 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:31:58.013 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:31:58.013 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:31:58.013 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:31:58.013 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:31:58.013 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:31:58.015 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:31:58.015 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:31:58.015 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:31:58.015 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:31:58.015 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:31:58.015 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:31:58.015 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:31:58.015 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:31:58.015 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:31:58.018 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:31:58.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:31:58.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:31:58.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:31:58.018 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:31:58.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:31:58.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:31:58.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:58.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:31:58.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:31:58.019 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:31:58.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:58.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:58.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:58.019 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:31:58.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:58.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:58.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:58.019 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:31:58.019 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:31:58.019 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:31:58.019 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:31:58.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:58.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:58.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:58.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:31:58.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:58.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:58.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:58.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:58.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:58.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:58.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:58.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:58.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:58.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:58.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:58.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:58.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:31:58.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:58.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:58.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:58.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:58.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:58.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:31:58.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:31:58.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:58.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:31:58.024 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:31:58.502 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:31:58.547 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:31:58.549 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:31:58.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:31:58.553 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:31:58.576 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:31:58.576 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:31:58.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:31:58.594 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:31:58.595 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:31:58.595 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:31:58.595 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:31:58.597 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:31:58.597 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:31:58.597 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:31:58.597 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:31:58.597 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:31:58.598 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:31:58.598 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:31:58.598 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:31:58.598 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:31:58.598 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:31:58.598 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:31:58.598 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:32:03.602 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:32:03.602 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:32:03.602 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:32:03.602 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:32:03.602 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:32:03.602 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:32:03.609 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:32:03.610 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:32:03.610 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:32:03.611 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:32:03.611 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:32:03.614 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:32:03.614 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:32:03.615 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:32:03.615 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:32:03.615 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:32:03.616 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:32:03.616 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:32:03.616 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:32:03.617 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:32:03.618 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:32:03.619 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:32:03.619 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:32:03.619 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:32:03.619 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:32:03.619 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:32:03.620 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:32:03.620 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:32:03.620 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:32:03.622 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:32:03.623 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:32:03.623 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:32:03.623 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:32:03.623 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:32:03.624 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:32:03.624 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:32:03.624 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:32:03.624 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:32:03.627 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:32:03.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:32:03.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:32:03.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:32:03.627 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:32:03.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:32:03.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:32:03.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:32:03.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:32:03.627 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:32:03.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:32:03.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:32:03.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:32:03.628 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:32:03.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:32:03.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:32:03.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:32:03.628 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:32:03.628 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:32:03.628 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:32:03.628 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:32:03.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:32:03.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:32:03.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:32:03.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:32:03.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:32:03.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:32:03.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:32:03.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:32:03.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:32:03.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:32:03.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:32:03.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:32:03.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:32:03.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:32:03.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:32:03.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:32:03.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:32:03.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:32:03.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:32:03.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:32:03.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:32:03.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:32:03.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:32:03.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:32:03.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:32:03.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:32:03.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:32:03.633 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:32:04.111 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:32:04.156 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:32:04.158 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:32:04.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:04.159 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:32:04.181 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:04.181 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:04.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:32:04.197 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:04.197 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:04.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:32:04.204 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:04.204 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:04.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:32:04.211 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:04.211 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:04.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:32:04.219 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:04.219 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:04.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:32:04.226 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:04.227 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:04.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:32:04.234 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:04.234 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:04.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:32:04.241 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:04.241 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:04.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:32:04.248 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:04.248 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:04.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:32:04.255 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:04.255 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:04.256 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:32:04.263 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:04.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:04.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:32:04.270 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:04.271 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:04.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:32:04.278 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:04.278 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:04.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:32:04.282 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:32:04.282 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:32:04.282 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:32:04.282 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:32:04.283 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:32:04.283 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:32:04.283 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:32:04.283 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:32:04.283 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:32:04.283 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:32:04.283 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:32:09.290 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:32:09.290 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:32:09.290 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:32:09.291 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:32:09.291 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:32:09.291 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:32:09.299 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:32:09.300 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:32:09.300 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:32:09.300 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:32:09.300 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:32:09.303 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:32:09.304 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:32:09.304 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:32:09.304 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:32:09.304 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:32:09.305 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:32:09.305 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:32:09.305 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:32:09.305 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:32:09.306 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:32:09.306 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:32:09.307 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:32:09.307 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:32:09.307 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:32:09.307 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:32:09.307 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:32:09.307 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:32:09.307 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:32:09.309 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:32:09.309 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:32:09.309 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:32:09.309 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:32:09.309 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:32:09.309 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:32:09.309 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:32:09.309 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:32:09.309 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:32:09.312 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:32:09.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:32:09.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:32:09.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:32:09.312 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:32:09.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:32:09.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:32:09.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:32:09.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:32:09.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:32:09.312 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:32:09.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:32:09.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:32:09.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:32:09.312 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:32:09.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:32:09.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:32:09.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:32:09.312 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:32:09.312 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:32:09.312 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:32:09.312 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:32:09.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:32:09.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:32:09.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:32:09.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:32:09.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:32:09.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:32:09.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:32:09.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:32:09.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:32:09.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:32:09.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:32:09.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:32:09.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:32:09.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:32:09.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:32:09.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:32:09.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:32:09.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:32:09.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:32:09.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:32:09.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:32:09.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:32:09.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:32:09.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:32:09.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:32:09.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:32:09.317 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:32:09.794 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:32:09.832 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:32:09.834 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:32:09.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:09.835 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:32:09.845 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:09.845 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:09.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:32:09.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:09.848 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:32:09.848 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:32:09.848 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:32:09.848 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:32:09.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:09.899 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:32:09.899 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:32:09.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:09.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:09.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:10.265 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:32:10.315 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:32:10.315 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:32:10.315 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:32:10.315 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:32:10.737 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:32:11.210 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:32:11.316 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:32:11.316 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:32:11.316 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:32:11.316 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:32:11.683 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:32:12.156 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:32:12.316 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:32:12.317 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:32:12.317 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:32:12.317 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:32:12.627 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:32:13.099 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:32:13.318 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:32:13.318 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:32:13.318 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:32:13.318 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:32:13.572 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:32:13.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:14.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:14.001 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:14.001 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:14.011 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:14.011 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:14.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:32:14.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:14.012 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:32:14.013 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:32:14.013 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:32:14.013 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:32:14.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:14.044 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:32:14.046 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:32:14.046 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:32:14.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:14.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:14.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:14.320 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:32:14.320 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:32:14.320 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:32:14.320 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:32:14.516 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:32:14.987 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:32:15.460 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:32:15.933 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:32:16.405 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:32:16.879 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:32:17.351 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:32:17.823 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:32:18.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:18.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:18.269 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:18.269 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:18.284 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:18.284 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:18.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:32:18.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:18.286 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:32:18.286 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:32:18.286 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:32:18.286 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:32:18.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:18.291 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:32:18.291 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:32:18.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:18.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:18.294 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:32:18.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:18.765 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:32:19.238 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:32:19.711 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:32:20.183 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:32:20.654 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:32:21.127 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:32:21.600 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:32:22.072 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:32:22.543 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:32:22.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:22.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:22.734 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:22.735 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:22.755 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:22.755 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:22.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:32:22.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:22.756 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:32:22.756 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:32:22.756 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:32:22.756 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:32:22.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:22.780 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:32:22.780 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:32:22.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:22.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:22.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:23.016 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:32:23.489 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:32:23.961 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:32:24.432 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:32:24.905 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:32:25.378 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:32:25.850 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:32:26.321 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 01:32:26.795 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 01:32:26.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:27.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:27.001 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:27.001 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:27.019 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:27.019 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:27.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:32:27.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:27.021 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:32:27.021 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:32:27.021 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:32:27.021 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:32:27.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:27.024 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:32:27.024 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:32:27.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:27.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:27.267 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 01:32:27.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:27.740 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 01:32:28.213 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 01:32:28.686 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 01:32:29.157 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 01:32:29.631 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 01:32:30.103 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 01:32:30.574 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 01:32:31.045 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 01:32:31.519 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 01:32:31.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:31.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:31.615 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:31.615 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:31.634 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:31.634 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:31.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:32:31.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:31.635 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:32:31.635 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:32:31.635 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:32:31.635 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:32:31.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:31.666 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:32:31.667 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:32:31.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:31.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:31.991 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 01:32:32.462 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 01:32:32.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:32.936 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 01:32:33.408 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 01:32:33.881 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 01:32:34.355 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 01:32:34.827 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 01:32:35.299 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 01:32:35.770 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 01:32:36.244 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 01:32:36.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:36.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:36.489 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:36.489 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:36.508 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:36.508 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:36.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:32:36.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:36.510 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:32:36.510 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:32:36.510 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:32:36.510 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:32:36.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:36.521 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:32:36.521 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:32:36.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:36.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:36.716 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 01:32:37.188 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 01:32:37.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:37.661 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 01:32:38.134 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 01:32:38.607 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 01:32:39.078 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 01:32:39.551 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 01:32:40.024 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 01:32:40.496 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 01:32:40.970 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 01:32:41.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:41.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:41.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:41.367 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:41.381 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:41.381 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:41.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:32:41.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:41.382 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:32:41.382 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:32:41.382 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:32:41.382 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:32:41.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:32:41.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:41.389 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:32:41.389 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:32:41.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:41.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:41.442 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 01:32:41.913 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 01:32:42.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:42.384 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 01:32:42.858 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 01:32:43.330 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 01:32:43.802 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 01:32:44.275 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-06 01:32:44.748 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-06 01:32:45.220 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-06 01:32:45.691 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-06 01:32:46.165 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-06 01:32:46.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:46.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:46.244 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:46.245 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:46.245 [WARNING] transceiver.py:257 (MS@172.18.59.22:6700) RX TRXD message (fn=7976 tn=2 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:32:46.254 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:46.254 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:46.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:32:46.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:46.255 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:32:46.255 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:32:46.255 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:32:46.255 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:32:46.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:46.304 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:32:46.305 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:32:46.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:46.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:46.637 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-06 01:32:47.109 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-06 01:32:47.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:47.583 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-06 01:32:48.055 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-06 01:32:48.527 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-06 01:32:49.000 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-06 01:32:49.473 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-06 01:32:49.946 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-06 01:32:50.419 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-06 01:32:50.891 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-06 01:32:51.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:51.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:51.122 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:51.122 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:51.122 [WARNING] transceiver.py:257 (MS@172.18.59.22:6700) RX TRXD message (fn=9028 tn=6 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:32:51.140 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:51.140 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:51.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:32:51.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:51.142 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:32:51.142 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:32:51.142 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:32:51.142 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:32:51.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:32:51.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:51.181 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:32:51.181 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:32:51.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:51.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:51.362 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-06 01:32:51.835 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-06 01:32:51.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:52.308 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-06 01:32:52.779 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-06 01:32:53.253 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-06 01:32:53.725 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-06 01:32:54.198 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-06 01:32:54.671 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-06 01:32:55.144 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-06 01:32:55.615 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-06 01:32:55.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:55.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:55.883 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:55.883 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:55.901 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:32:55.901 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:32:55.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:32:55.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:55.903 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:32:55.903 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:32:55.903 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:32:55.903 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:32:55.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:55.952 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:32:55.952 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:32:55.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:55.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:32:56.086 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-06 01:32:56.557 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-06 01:32:56.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:32:57.030 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-06 01:32:57.503 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-06 01:32:57.977 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-06 01:32:58.449 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-06 01:32:58.920 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-06 01:32:59.394 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-06 01:32:59.866 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-06 01:33:00.339 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-06 01:33:00.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:00.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:00.694 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:00.694 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:00.712 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:00.712 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:00.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:00.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:00.714 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:00.714 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:00.714 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:00.714 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:00.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:00.766 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:00.766 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:00.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:00.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:00.809 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-06 01:33:01.280 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-06 01:33:01.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:01.754 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-06 01:33:02.219 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-06 01:33:02.693 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-06 01:33:03.165 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-06 01:33:03.636 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-06 01:33:04.109 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-06 01:33:04.582 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-06 01:33:05.054 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-06 01:33:05.525 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-06 01:33:05.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:05.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:05.571 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:05.571 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:05.590 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:05.590 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:05.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:05.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:05.592 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:05.592 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:05.593 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:05.593 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:05.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:05.625 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:05.626 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:05.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:05.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:05.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:05.998 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-06 01:33:06.470 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-06 01:33:06.942 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-06 01:33:07.413 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-06 01:33:07.887 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-06 01:33:08.359 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-06 01:33:08.831 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-06 01:33:09.302 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-06 01:33:09.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:09.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:09.692 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:09.693 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:09.712 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:09.712 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:09.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:09.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:09.714 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:09.714 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:09.714 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:09.714 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:09.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:09.720 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:09.720 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:09.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:09.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:09.775 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-06 01:33:09.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:10.248 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-06 01:33:10.720 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-06 01:33:11.193 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-06 01:33:11.666 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-06 01:33:12.138 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-06 01:33:12.609 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-06 01:33:13.083 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-06 01:33:13.555 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-06 01:33:13.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:13.950 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:13.951 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:13.951 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:13.960 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:13.960 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:13.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:13.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:13.961 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:13.961 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:13.961 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:13.961 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:13.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:13.975 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:13.975 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:13.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:13.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:14.026 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-06 01:33:14.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:14.498 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-06 01:33:14.971 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-06 01:33:15.444 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-06 01:33:15.916 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-06 01:33:16.387 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-06 01:33:16.860 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-06 01:33:17.332 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-06 01:33:17.804 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-06 01:33:18.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:18.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:18.224 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:18.224 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:18.240 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:18.240 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:18.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:18.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:18.242 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:18.242 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:18.242 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:18.242 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:18.275 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-06 01:33:18.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:18.283 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:18.283 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:18.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:18.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:18.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:18.746 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-06 01:33:19.220 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-06 01:33:19.692 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-06 01:33:20.164 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-06 01:33:20.635 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-06 01:33:21.108 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-06 01:33:21.581 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-06 01:33:22.052 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-06 01:33:22.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:22.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:22.491 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:22.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:22.509 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:22.509 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:22.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:22.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:22.511 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:22.511 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:22.511 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:22.511 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:22.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:22.522 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:22.522 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:22.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:22.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:22.523 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-06 01:33:22.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:22.994 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-06 01:33:23.465 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-06 01:33:23.939 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-06 01:33:24.411 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-06 01:33:24.883 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-06 01:33:25.354 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-06 01:33:25.828 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-06 01:33:26.299 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-06 01:33:26.771 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-06 01:33:26.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:26.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:26.919 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:26.919 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:26.919 [WARNING] transceiver.py:257 (MS@172.18.59.22:6700) RX TRXD message (fn=16762 tn=1 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:33:26.937 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:26.937 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:26.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:26.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:26.938 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:26.938 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:26.938 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:26.938 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:26.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:26.958 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:26.958 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:26.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:26.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:27.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:27.243 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-06 01:33:27.716 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-06 01:33:28.188 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-06 01:33:28.660 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-06 01:33:29.132 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-06 01:33:29.605 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-06 01:33:30.077 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-06 01:33:30.550 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-06 01:33:31.023 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-06 01:33:31.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:31.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:31.186 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:31.186 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:31.194 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:31.194 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:31.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:31.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:31.195 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:31.195 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:31.195 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:31.195 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:31.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:31.202 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:31.202 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:31.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:31.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:31.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:31.495 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-06 01:33:31.967 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-06 01:33:32.439 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-06 01:33:32.912 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-06 01:33:33.384 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-06 01:33:33.857 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-06 01:33:34.329 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-06 01:33:34.802 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-06 01:33:35.275 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-03-06 01:33:35.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:35.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:35.453 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:35.453 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:35.472 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:35.472 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:35.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:35.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:35.473 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:35.473 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:35.474 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:35.474 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:35.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:35.519 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:35.519 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:35.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:35.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:35.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:35.745 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-03-06 01:33:36.216 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-03-06 01:33:36.690 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-03-06 01:33:37.162 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-03-06 01:33:37.634 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-03-06 01:33:38.105 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-03-06 01:33:38.579 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-03-06 01:33:39.051 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-03-06 01:33:39.523 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-03-06 01:33:39.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:39.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:39.725 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:39.725 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:39.733 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:33:39.733 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:33:39.733 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:33:39.733 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:33:39.734 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:33:39.734 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:33:39.734 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:33:39.734 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:33:39.734 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:33:39.734 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:33:39.734 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:33:39.734 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19530 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:33:39.734 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19530 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:33:39.734 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19530 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:33:39.734 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19530 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:33:39.734 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19530 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:33:39.734 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19530 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:33:44.741 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:33:44.741 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:33:44.741 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:33:44.741 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:33:44.741 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:33:44.742 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:33:44.750 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:33:44.751 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:33:44.751 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:33:44.751 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:33:44.751 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:33:44.754 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:33:44.754 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:33:44.754 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:33:44.754 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:33:44.755 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:33:44.755 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:33:44.755 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:33:44.755 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:33:44.755 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:33:44.756 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:33:44.757 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:33:44.757 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:33:44.757 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:33:44.757 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:33:44.757 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:33:44.757 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:33:44.757 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:33:44.757 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:33:44.759 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:33:44.759 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:33:44.759 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:33:44.759 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:33:44.759 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:33:44.759 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:33:44.759 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:33:44.759 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:33:44.759 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:33:44.762 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:33:44.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:33:44.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:33:44.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:33:44.762 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:33:44.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:33:44.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:33:44.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:33:44.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:33:44.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:33:44.762 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:33:44.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:33:44.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:33:44.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:33:44.762 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:33:44.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:33:44.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:33:44.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:33:44.762 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:33:44.762 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:33:44.762 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:33:44.763 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:33:44.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:33:44.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:33:44.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:33:44.763 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:33:44.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:33:44.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:33:44.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:33:44.763 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:33:44.763 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:33:44.763 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:33:44.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:33:44.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:33:44.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:33:49.772 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:33:49.772 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:33:49.772 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:33:49.772 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:33:49.772 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:33:49.772 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:33:49.779 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:33:49.780 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:33:49.780 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:33:49.780 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:33:49.780 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:33:49.782 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:33:49.782 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:33:49.782 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:33:49.782 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:33:49.782 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:33:49.782 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:33:49.783 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:33:49.783 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:33:49.783 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:33:49.784 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:33:49.785 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:33:49.785 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:33:49.785 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:33:49.785 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:33:49.785 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:33:49.785 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:33:49.785 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:33:49.785 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:33:49.786 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:33:49.787 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:33:49.787 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:33:49.787 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:33:49.787 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:33:49.787 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:33:49.787 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:33:49.787 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:33:49.787 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:33:49.789 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:33:49.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:33:49.789 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:33:49.789 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:33:49.789 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:33:49.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:33:49.789 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:33:49.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:33:49.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:33:49.789 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:33:49.789 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:33:49.789 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:33:49.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:33:49.789 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:33:49.789 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:33:49.789 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:33:49.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:33:49.789 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:33:49.789 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:33:49.789 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:33:49.790 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:33:49.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:33:49.794 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:33:50.272 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:33:50.307 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:33:50.309 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:33:50.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:50.311 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:33:50.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:50.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:50.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:50.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:50.338 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:50.338 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:50.339 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:50.339 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:50.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:50.375 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:50.375 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:50.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:50.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:50.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:50.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:50.478 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:50.478 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:50.496 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:50.496 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:50.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:50.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:50.499 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:50.499 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:50.499 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:50.499 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:50.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:50.547 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:50.548 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:50.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:50.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:50.740 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:33:50.791 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:33:50.791 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:33:50.792 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:33:50.792 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:33:50.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:50.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:50.962 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:50.962 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:50.977 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:50.977 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:50.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:50.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:50.979 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:50.979 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:50.979 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:50.979 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:51.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:51.031 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:51.031 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:51.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:51.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:51.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:51.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:51.179 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:51.179 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:51.187 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:51.187 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:51.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:51.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:51.189 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:51.189 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:51.189 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:51.189 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:51.214 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:33:51.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:51.245 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:51.245 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:51.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:51.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:51.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:51.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:51.668 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:51.668 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:51.677 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:51.677 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:51.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:51.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:51.679 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:51.679 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:51.679 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:51.679 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:51.686 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:33:51.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:51.735 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:51.735 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:51.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:51.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:51.793 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:33:51.793 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:33:51.793 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:33:51.793 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:33:52.158 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:33:52.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:52.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:52.195 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:52.196 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:52.209 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:52.209 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:52.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:52.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:52.212 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:52.212 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:52.212 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:52.212 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:52.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:52.267 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:52.267 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:52.267 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:52.267 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:52.629 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:33:52.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:52.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:52.735 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:52.735 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:52.746 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:52.746 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:52.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:52.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:52.749 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:52.749 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:52.749 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:52.749 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:52.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:52.794 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:33:52.794 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:33:52.794 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:33:52.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:33:52.799 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:52.799 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:52.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:52.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:53.102 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:33:53.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:53.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:53.276 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:53.276 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:53.295 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:53.295 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:53.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:53.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:53.298 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:53.298 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:53.298 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:53.298 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:53.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:33:53.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:53.348 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:53.348 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:53.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:53.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:53.574 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:33:53.795 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:33:53.796 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:33:53.796 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:33:53.796 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:33:53.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:53.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:53.821 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:53.822 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:53.839 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:53.839 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:53.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:53.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:53.841 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:53.841 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:53.841 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:53.841 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:53.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:53.891 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:53.891 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:53.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:53.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:54.046 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:33:54.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:54.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:54.362 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:54.362 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:54.380 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:54.380 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:54.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:54.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:54.383 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:54.383 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:54.383 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:54.383 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:54.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:33:54.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:54.431 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:54.432 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:54.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:54.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:54.518 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:33:54.797 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:33:54.797 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:33:54.797 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:33:54.798 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:33:54.991 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:33:55.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:55.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:55.266 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:55.266 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:55.283 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:55.283 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:55.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:55.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:55.286 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:55.286 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:55.286 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:55.286 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:55.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:55.335 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:55.335 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:55.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:55.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:55.464 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:33:55.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:55.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:55.746 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:55.746 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:55.767 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:55.767 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:55.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:55.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:55.771 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:55.771 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:55.771 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:55.771 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:55.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:55.800 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:55.801 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:55.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:55.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:55.935 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:33:56.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:56.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:56.286 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:56.287 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:56.304 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:56.304 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:56.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:56.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:56.306 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:56.306 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:56.306 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:56.306 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:56.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:56.361 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:56.361 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:56.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:56.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:56.408 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:33:56.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:56.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:56.564 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:56.564 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:56.572 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:56.572 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:56.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:56.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:56.574 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:56.574 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:56.574 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:56.574 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:56.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:56.623 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:56.623 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:56.624 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:56.624 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:56.880 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:33:57.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:57.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:57.059 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:57.059 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:57.074 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:57.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:57.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:57.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:57.077 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:57.078 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:57.078 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:57.078 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:57.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:57.127 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:57.127 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:57.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:57.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:57.352 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:33:57.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:57.547 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:57.548 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:57.548 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:57.556 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:57.556 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:57.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:57.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:57.558 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:57.558 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:57.558 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:57.558 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:57.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:57.608 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:57.608 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:57.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:57.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:57.823 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:33:58.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:58.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:58.037 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:58.037 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:58.046 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:58.046 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:58.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:58.048 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:58.048 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:58.048 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:58.048 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:58.048 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:58.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:58.098 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:58.098 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:58.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:58.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:58.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:58.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:58.212 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:58.212 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:58.220 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:58.220 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:58.220 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:58.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:58.222 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:58.222 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:58.222 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:58.222 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:58.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:58.271 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:58.272 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:58.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:58.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:58.294 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:33:58.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:58.707 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:58.707 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:58.707 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:58.716 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:58.716 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:58.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:58.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:58.718 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:58.718 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:58.718 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:58.718 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:58.765 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:33:58.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:58.768 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:58.769 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:58.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:58.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:59.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:59.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:59.196 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:59.196 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:59.215 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:59.215 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:59.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:33:59.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:59.217 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:59.217 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:59.217 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:33:59.217 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:33:59.238 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:33:59.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:59.271 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:33:59.271 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:33:59.272 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:59.272 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:59.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:33:59.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:33:59.685 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:33:59.685 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:33:59.694 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:33:59.694 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:33:59.694 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:33:59.695 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:33:59.696 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:33:59.696 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:33:59.696 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:33:59.696 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:33:59.696 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:33:59.696 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:33:59.696 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:33:59.696 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2142 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:33:59.696 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2142 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:33:59.696 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2142 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:33:59.696 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2142 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:33:59.696 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2142 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:33:59.696 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2142 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:34:04.701 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:34:04.701 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:34:04.701 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:34:04.701 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:34:04.701 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:34:04.701 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:34:04.709 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:34:04.710 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:34:04.710 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:34:04.710 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:34:04.711 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:34:04.713 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:34:04.713 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:34:04.714 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:34:04.714 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:34:04.714 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:34:04.714 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:34:04.715 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:34:04.715 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:34:04.715 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:34:04.716 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:34:04.716 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:34:04.716 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:34:04.716 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:34:04.716 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:34:04.716 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:34:04.716 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:34:04.716 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:34:04.717 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:34:04.718 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:34:04.718 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:34:04.718 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:34:04.718 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:34:04.718 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:34:04.718 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:34:04.718 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:34:04.718 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:34:04.718 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:34:04.721 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:34:04.721 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:34:04.721 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:34:04.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:34:04.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:34:04.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:34:04.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:34:04.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:34:04.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:34:04.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:34:04.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:34:04.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:34:04.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:34:04.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:34:04.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:34:04.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:34:04.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:34:04.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:34:04.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:34:04.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:34:04.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:34:04.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:34:04.726 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:34:05.199 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:34:05.241 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:34:05.243 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:34:05.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:05.244 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:34:05.266 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:05.266 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:05.267 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:05.272 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:05.272 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:05.273 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:05.273 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:05.273 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:05.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:05.295 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:05.295 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:05.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:05.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:05.671 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:34:05.724 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:34:05.724 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:34:05.724 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:34:05.726 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:34:05.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:05.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:06.142 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:34:06.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:06.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:06.345 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:06.345 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:06.362 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:06.362 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:06.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:06.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:06.366 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:06.366 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:06.366 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:06.366 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:06.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:06.417 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:06.417 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:06.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:06.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:06.615 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:34:06.724 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:34:06.725 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:34:06.725 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:34:06.727 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:34:07.088 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:34:07.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:07.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:07.561 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:34:07.725 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:34:07.726 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:34:07.726 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:34:07.728 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:34:07.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:07.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:07.783 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:07.783 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:07.800 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:07.800 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:07.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:07.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:07.802 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:07.802 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:07.802 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:07.802 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:07.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:07.849 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:07.849 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:07.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:07.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:08.031 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:34:08.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:08.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:08.505 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:34:08.726 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:34:08.727 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:34:08.727 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:34:08.729 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:34:08.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:08.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:08.943 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:08.943 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:08.963 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:08.963 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:08.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:08.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:08.966 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:08.966 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:08.966 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:08.966 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:08.977 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:34:09.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:09.019 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:09.020 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:09.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:09.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:09.449 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:34:09.727 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:34:09.728 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:34:09.728 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:34:09.730 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:34:09.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:09.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:09.920 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:34:10.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:10.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:10.379 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:10.379 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:10.392 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:10.392 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:10.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:10.393 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:34:10.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:10.394 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:10.394 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:10.394 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:10.394 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:10.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:10.441 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:10.441 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:10.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:10.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:10.865 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:34:11.338 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:34:11.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:11.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:11.812 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:34:11.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:11.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:11.938 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:11.938 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:11.956 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:11.956 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:11.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:11.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:11.959 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:11.959 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:11.959 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:11.959 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:12.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:12.011 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:12.011 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:12.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:12.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:12.283 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:34:12.756 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:34:12.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:12.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:13.227 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:34:13.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:13.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:13.444 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:13.444 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:13.462 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:13.462 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:13.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:13.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:13.464 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:13.464 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:13.464 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:13.464 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:13.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:13.516 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:13.516 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:13.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:13.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:13.700 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:34:14.173 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:34:14.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:14.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:14.645 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:34:14.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:14.950 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:14.950 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:14.951 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:14.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:14.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:14.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:14.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:14.966 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:14.966 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:14.966 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:14.966 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:15.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:34:15.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:15.016 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:15.017 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:15.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:15.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:15.115 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:34:15.587 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:34:15.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:15.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:16.060 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:34:16.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:16.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:16.450 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:16.450 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:16.466 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:16.466 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:16.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:16.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:16.469 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:16.469 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:16.469 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:16.469 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:16.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:16.518 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:16.519 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:16.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:16.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:16.532 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:34:17.004 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:34:17.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:17.475 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:34:17.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:17.946 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:34:17.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:17.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:17.956 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:17.956 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:17.973 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:17.973 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:17.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:17.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:17.976 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:17.976 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:17.976 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:17.976 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:18.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:34:18.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:18.030 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:18.030 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:18.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:18.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:18.417 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:34:18.888 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:34:19.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:19.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:19.361 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:34:19.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:19.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:19.817 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:19.817 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:19.833 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:34:19.834 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:19.834 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:19.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:19.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:19.836 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:19.836 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:19.836 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:19.836 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:19.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:19.883 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:19.883 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:19.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:19.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:20.305 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:34:20.777 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:34:20.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:20.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:21.251 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:34:21.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:21.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:21.267 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:21.267 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:21.286 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:21.286 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:21.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:21.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:21.288 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:21.288 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:21.288 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:21.288 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:21.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:21.345 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:21.345 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:21.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:21.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:21.723 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 01:34:22.194 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 01:34:22.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:22.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:22.665 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 01:34:22.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:22.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:22.767 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:22.767 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:22.787 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:22.787 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:22.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:22.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:22.789 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:22.790 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:22.790 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:22.790 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:22.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:22.843 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:22.843 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:22.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:22.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:23.135 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 01:34:23.609 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 01:34:23.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:23.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:24.081 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 01:34:24.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:24.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:24.241 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:24.242 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:24.260 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:24.260 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:24.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:24.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:24.262 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:24.262 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:24.262 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:24.262 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:24.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:24.324 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:24.325 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:24.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:24.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:24.553 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 01:34:25.024 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 01:34:25.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:25.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:25.498 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 01:34:25.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:25.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:25.672 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:25.672 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:25.690 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:25.690 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:25.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:25.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:25.692 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:25.692 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:25.692 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:25.692 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:25.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:25.742 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:25.742 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:25.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:25.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:25.970 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 01:34:26.442 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 01:34:26.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:26.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:26.913 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 01:34:27.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:27.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:27.107 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:27.107 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:27.117 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:27.117 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:27.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:27.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:27.119 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:27.119 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:27.119 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:27.119 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:27.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:27.172 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:27.172 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:27.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:27.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:27.386 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 01:34:27.858 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 01:34:28.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:28.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:28.330 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 01:34:28.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:28.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:28.544 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:28.544 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:28.563 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:28.563 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:28.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:28.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:28.566 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:28.566 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:28.566 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:28.566 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:28.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:28.621 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:28.621 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:28.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:28.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:28.801 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 01:34:29.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:29.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:29.272 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 01:34:29.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:29.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:29.666 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:29.666 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:29.675 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:29.675 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:29.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:29.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:29.677 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:29.677 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:29.677 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:29.677 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:29.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:29.729 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:29.729 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:29.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:29.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:29.746 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 01:34:30.218 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 01:34:30.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:30.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:30.690 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 01:34:31.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:31.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:31.102 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:31.102 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:31.119 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:31.119 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:31.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:31.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:31.122 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:31.122 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:31.122 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:31.122 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:31.161 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 01:34:31.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:31.171 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:31.171 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:31.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:31.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:31.632 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 01:34:32.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:32.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:32.103 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 01:34:32.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:32.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:32.534 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:32.534 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:32.551 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:32.551 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:32.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:32.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:32.553 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:32.553 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:32.553 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:32.553 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:32.573 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 01:34:32.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:32.604 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:32.604 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:32.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:32.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:33.044 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 01:34:33.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:33.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:33.515 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 01:34:33.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:33.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:33.963 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:33.963 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:33.974 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:34:33.974 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:34:33.974 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:34:33.974 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:34:33.977 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:34:33.977 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:34:33.977 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:34:33.977 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:34:33.977 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:34:33.977 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:34:33.977 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:34:33.977 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6324 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:34:33.977 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6324 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:34:33.977 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6324 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:34:33.977 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6324 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:34:33.977 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6324 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:34:33.977 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6324 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:34:38.981 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:34:38.981 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:34:38.981 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:34:38.981 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:34:38.981 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:34:38.981 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:34:38.989 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:34:38.990 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:34:38.990 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:34:38.990 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:34:38.990 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:34:38.993 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:34:38.993 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:34:38.993 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:34:38.993 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:34:38.993 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:34:38.993 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:34:38.994 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:34:38.994 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:34:38.994 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:34:38.996 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:34:38.996 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:34:38.996 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:34:38.996 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:34:38.996 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:34:38.996 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:34:38.996 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:34:38.996 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:34:38.996 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:34:38.998 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:34:38.998 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:34:38.998 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:34:38.998 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:34:38.998 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:34:38.998 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:34:38.998 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:34:38.998 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:34:38.998 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:34:39.001 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:34:39.001 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:34:39.001 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:34:39.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:34:39.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:34:39.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:34:39.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:34:39.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:34:39.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:34:39.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:34:39.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:34:39.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:34:39.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:34:39.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:34:39.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:34:39.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:34:39.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:34:39.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:34:39.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:34:39.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:34:39.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:34:39.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:34:39.006 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:34:39.482 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:34:39.526 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:34:39.528 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:34:39.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:39.531 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:34:39.555 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:39.555 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:39.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:39.562 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:39.562 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:39.562 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:39.562 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:39.562 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:39.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:39.580 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:39.580 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:39.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:39.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:39.954 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:34:40.004 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:34:40.004 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:34:40.004 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:34:40.004 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:34:40.426 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:34:40.899 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:34:41.005 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:34:41.005 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:34:41.006 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:34:41.006 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:34:41.372 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:34:41.844 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:34:42.006 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:34:42.006 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:34:42.006 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:34:42.007 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:34:42.315 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:34:42.788 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:34:43.007 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:34:43.007 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:34:43.007 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:34:43.007 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:34:43.261 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:34:43.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:43.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:43.466 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:43.466 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:43.480 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:43.480 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:43.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:43.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:43.483 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:43.483 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:43.483 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:43.483 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:43.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:43.535 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:43.535 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:43.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:43.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:43.732 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:34:44.008 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:34:44.008 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:34:44.008 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:34:44.008 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:34:44.204 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:34:44.677 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:34:45.149 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:34:45.621 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:34:46.092 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:34:46.566 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:34:47.038 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:34:47.510 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:34:47.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:47.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:47.732 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:47.732 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:47.749 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:47.749 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:47.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:47.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:47.752 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:47.752 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:47.752 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:47.752 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:47.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:47.803 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:47.803 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:47.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:47.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:47.981 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:34:48.454 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:34:48.927 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:34:49.399 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:34:49.870 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:34:50.341 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:34:50.814 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:34:51.287 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:34:51.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:51.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:51.728 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:51.728 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:51.744 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:51.744 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:51.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:51.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:51.747 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:51.747 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:51.747 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:51.747 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:51.758 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:34:51.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:51.797 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:51.797 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:51.797 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:51.797 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:52.230 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:34:52.703 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:34:53.176 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:34:53.648 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:34:54.119 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:34:54.592 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:34:55.065 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:34:55.536 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:34:55.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:55.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:55.994 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:55.994 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:56.004 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:34:56.004 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:34:56.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:34:56.006 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:56.006 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:56.006 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:56.006 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:34:56.006 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:34:56.007 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 01:34:56.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:34:56.059 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:34:56.060 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:34:56.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:56.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:34:56.479 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 01:34:56.949 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 01:34:57.423 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 01:34:57.896 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 01:34:58.370 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 01:34:58.842 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 01:34:59.316 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 01:34:59.788 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 01:35:00.260 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 01:35:00.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:00.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:00.667 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:00.667 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:00.683 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:00.683 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:00.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:35:00.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:00.686 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:00.686 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:00.686 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:35:00.686 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:35:00.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:00.731 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 01:35:00.737 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:00.738 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:00.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:00.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:01.202 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 01:35:01.673 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 01:35:02.144 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 01:35:02.618 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 01:35:03.090 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 01:35:03.563 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 01:35:04.036 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 01:35:04.509 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 01:35:04.981 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 01:35:05.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:05.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:05.060 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:05.060 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:05.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:05.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:05.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:35:05.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:05.077 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:05.077 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:05.077 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:35:05.077 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:35:05.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:05.127 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:05.127 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:05.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:05.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:05.452 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 01:35:05.926 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 01:35:06.398 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 01:35:06.869 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 01:35:07.340 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 01:35:07.811 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 01:35:08.285 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 01:35:08.757 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 01:35:09.228 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 01:35:09.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:09.450 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:09.451 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:09.451 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:09.467 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:09.467 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:09.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:35:09.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:09.470 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:09.470 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:09.470 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:35:09.470 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:35:09.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:35:09.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:09.519 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:09.519 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:09.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:09.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:09.700 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 01:35:10.174 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 01:35:10.646 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 01:35:11.117 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 01:35:11.587 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 01:35:12.058 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 01:35:12.532 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 01:35:13.004 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 01:35:13.476 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 01:35:13.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:13.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:13.841 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:13.842 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:13.858 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:13.858 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:13.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:35:13.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:13.860 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:13.860 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:13.860 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:35:13.860 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:35:13.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:13.911 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:13.911 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:13.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:13.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:13.949 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-06 01:35:14.422 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-06 01:35:14.894 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-06 01:35:15.365 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-06 01:35:15.835 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-06 01:35:16.306 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-06 01:35:16.777 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-06 01:35:17.250 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-06 01:35:17.723 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-06 01:35:18.196 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-06 01:35:18.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:18.233 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:18.233 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:18.234 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:18.249 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:18.249 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:18.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:35:18.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:18.252 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:18.252 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:18.252 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:35:18.252 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:35:18.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:35:18.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:18.303 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:18.304 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:18.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:18.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:18.667 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-06 01:35:19.140 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-06 01:35:19.612 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-06 01:35:20.085 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-06 01:35:20.559 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-06 01:35:21.031 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-06 01:35:21.505 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-06 01:35:21.978 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-06 01:35:22.449 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-06 01:35:22.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:22.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:22.509 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:22.509 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:22.525 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:22.525 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:22.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:35:22.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:22.528 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:22.528 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:22.528 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:35:22.528 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:35:22.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:22.580 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:22.581 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:22.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:22.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:22.922 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-06 01:35:23.394 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-06 01:35:23.866 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-06 01:35:24.337 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-06 01:35:24.808 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-06 01:35:25.281 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-06 01:35:25.754 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-06 01:35:26.226 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-06 01:35:26.697 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-06 01:35:26.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:26.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:26.841 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:26.841 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:26.858 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:26.858 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:26.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:35:26.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:26.861 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:26.861 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:26.861 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:35:26.861 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:35:26.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:26.916 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:26.917 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:26.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:26.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:27.171 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-06 01:35:27.643 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-06 01:35:28.115 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-06 01:35:28.586 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-06 01:35:29.057 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-06 01:35:29.530 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-06 01:35:30.003 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-06 01:35:30.475 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-06 01:35:30.949 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-06 01:35:31.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:31.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:31.237 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:31.238 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:31.254 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:31.255 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:31.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:35:31.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:31.257 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:31.257 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:31.257 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:35:31.257 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:35:31.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:31.308 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:31.309 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:31.309 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:31.309 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:31.421 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-06 01:35:31.892 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-06 01:35:32.366 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-06 01:35:32.838 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-06 01:35:33.310 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-06 01:35:33.781 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-06 01:35:34.254 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-06 01:35:34.727 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-06 01:35:35.199 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-06 01:35:35.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:35.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:35.358 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:35.359 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:35.377 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:35.377 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:35.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:35:35.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:35.380 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:35.380 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:35.380 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:35:35.380 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:35:35.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:35.443 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:35.443 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:35.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:35.444 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:35.670 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-06 01:35:36.141 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-06 01:35:36.614 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-06 01:35:37.086 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-06 01:35:37.558 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-06 01:35:38.029 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-06 01:35:38.503 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-06 01:35:38.975 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-06 01:35:39.447 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-06 01:35:39.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:39.624 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:39.625 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:39.625 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:39.637 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:39.637 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:39.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:35:39.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:39.640 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:39.640 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:39.640 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:35:39.640 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:35:39.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:39.720 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:39.721 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:39.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:39.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:39.918 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-06 01:35:40.389 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-06 01:35:40.862 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-06 01:35:41.335 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-06 01:35:41.807 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-06 01:35:42.278 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-06 01:35:42.751 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-06 01:35:43.224 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-06 01:35:43.696 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-06 01:35:43.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:43.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:43.891 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:43.891 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:43.909 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:43.909 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:43.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:35:43.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:43.912 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:43.912 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:43.912 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:35:43.912 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:35:43.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:43.965 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:43.965 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:43.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:43.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:44.167 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-06 01:35:44.638 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-06 01:35:45.108 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-06 01:35:45.582 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-06 01:35:46.054 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-06 01:35:46.526 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-06 01:35:46.997 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-06 01:35:47.471 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-06 01:35:47.943 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-06 01:35:48.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:48.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:48.157 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:48.158 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:48.173 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:48.173 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:48.173 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:35:48.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:48.175 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:48.175 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:48.175 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:35:48.175 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:35:48.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:48.232 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:48.232 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:48.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:48.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:48.415 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-06 01:35:48.886 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-06 01:35:49.360 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-06 01:35:49.832 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-06 01:35:50.304 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-06 01:35:50.775 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-06 01:35:51.248 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-06 01:35:51.720 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-06 01:35:52.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:52.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:52.115 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:52.115 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:52.133 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:52.133 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:52.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:35:52.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:52.136 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:52.136 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:52.136 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:35:52.136 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:35:52.192 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-06 01:35:52.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:52.195 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:52.196 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:52.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:52.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:52.663 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-06 01:35:53.137 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-06 01:35:53.609 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-06 01:35:54.081 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-06 01:35:54.552 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-06 01:35:55.025 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-06 01:35:55.498 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-06 01:35:55.970 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-06 01:35:56.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:56.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:56.382 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:56.382 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:56.398 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:35:56.398 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:35:56.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:35:56.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:56.400 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:56.400 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:56.400 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:35:56.400 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:35:56.441 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-06 01:35:56.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:35:56.451 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:35:56.452 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:35:56.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:56.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:35:56.911 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-06 01:35:57.385 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-06 01:35:57.857 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-06 01:35:58.329 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-06 01:35:58.800 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-06 01:35:59.271 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-06 01:35:59.744 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-06 01:36:00.217 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-06 01:36:00.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:36:00.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:00.648 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:36:00.649 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:36:00.665 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:36:00.665 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:36:00.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:36:00.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:00.668 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:36:00.668 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:36:00.668 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:36:00.668 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:36:00.688 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-06 01:36:00.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:36:00.719 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:36:00.720 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:36:00.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:00.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:01.160 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-06 01:36:01.633 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-06 01:36:02.105 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-06 01:36:02.577 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-06 01:36:03.049 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-06 01:36:03.522 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-06 01:36:03.994 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-06 01:36:04.466 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-06 01:36:04.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:36:04.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:04.915 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:36:04.915 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:36:04.923 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:36:04.923 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:36:04.923 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:36:04.923 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:36:04.927 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:36:04.928 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:36:04.928 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:36:04.928 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:36:04.929 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:36:04.929 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:36:04.929 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:36:04.929 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=18564 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:36:04.929 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=18564 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:36:04.929 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=18564 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:36:04.929 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=18564 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:36:04.929 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=18564 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:36:04.929 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=18564 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:36:04.929 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=18564 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:36:09.931 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:36:09.931 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:36:09.931 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:36:09.931 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:36:09.931 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:36:09.931 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:36:09.938 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:36:09.939 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:36:09.939 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:36:09.940 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:36:09.940 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:36:09.942 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:36:09.942 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:36:09.942 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:36:09.942 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:36:09.943 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:36:09.943 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:36:09.943 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:36:09.943 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:36:09.943 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:36:09.944 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:36:09.944 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:36:09.945 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:36:09.945 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:36:09.945 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:36:09.945 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:36:09.945 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:36:09.945 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:36:09.945 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:36:09.946 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:36:09.947 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:36:09.947 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:36:09.947 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:36:09.947 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:36:09.947 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:36:09.947 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:36:09.947 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:36:09.947 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:36:09.949 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:36:09.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:36:09.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:36:09.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:36:09.949 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:36:09.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:36:09.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:36:09.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:36:09.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:36:09.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:36:09.949 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:36:09.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:36:09.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:36:09.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:36:09.950 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:36:09.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:36:09.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:36:09.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:36:09.950 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:36:09.950 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:36:09.950 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:36:09.950 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:36:09.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:36:09.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:36:09.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:36:09.950 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:36:09.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:36:09.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:36:09.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:36:09.951 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:36:09.951 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:36:09.951 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:36:09.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:36:09.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:36:09.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:36:14.957 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:36:14.958 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:36:14.958 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:36:14.958 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:36:14.958 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:36:14.958 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:36:14.982 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:36:14.984 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:36:14.985 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:36:14.985 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:36:14.985 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:36:14.993 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:36:14.993 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:36:14.994 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:36:14.994 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:36:14.995 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:36:14.995 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:36:14.996 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:36:14.996 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:36:14.996 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:36:14.999 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:36:15.000 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:36:15.000 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:36:15.000 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:36:15.001 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:36:15.001 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:36:15.002 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:36:15.002 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:36:15.002 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:36:15.004 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:36:15.005 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:36:15.005 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:36:15.005 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:36:15.005 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:36:15.005 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:36:15.005 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:36:15.005 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:36:15.006 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:36:15.009 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:36:15.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:36:15.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:36:15.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:36:15.009 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:36:15.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:36:15.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:36:15.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:36:15.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:36:15.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:36:15.010 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:36:15.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:36:15.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:36:15.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:36:15.010 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:36:15.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:36:15.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:36:15.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:36:15.010 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:36:15.010 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:36:15.010 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:36:15.010 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:36:15.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:36:15.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:36:15.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:36:15.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:36:15.011 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:36:15.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:36:15.011 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:36:15.011 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:36:15.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:36:15.011 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:36:15.011 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:36:15.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:36:15.011 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:36:15.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:36:15.011 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:36:15.011 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:36:15.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:36:15.011 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:36:15.011 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:36:15.011 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:36:15.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:36:15.011 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:36:15.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:36:15.011 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:36:15.011 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:36:15.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:36:15.015 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:36:15.494 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:36:15.534 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:36:15.535 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:36:15.536 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:36:15.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:36:15.554 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:36:15.554 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:36:15.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:36:15.562 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:15.562 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:36:15.562 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:36:15.562 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:36:15.562 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:36:15.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:36:15.597 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:36:15.598 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:36:15.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:15.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:15.966 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:36:16.012 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:36:16.013 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:36:16.013 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:36:16.013 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:36:16.437 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:36:16.911 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:36:17.013 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:36:17.014 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:36:17.014 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:36:17.014 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:36:17.383 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:36:17.855 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:36:18.014 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:36:18.015 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:36:18.015 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:36:18.015 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:36:18.329 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:36:18.801 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:36:19.016 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:36:19.016 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:36:19.017 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:36:19.017 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:36:19.273 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:36:19.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:36:19.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:19.641 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:36:19.641 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:36:19.658 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:36:19.658 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:36:19.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:36:19.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:19.661 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:36:19.661 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:36:19.661 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:36:19.661 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:36:19.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:36:19.715 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:36:19.715 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:36:19.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:19.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:19.743 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:36:20.018 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:36:20.018 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:36:20.018 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:36:20.018 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:36:20.215 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:36:20.688 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:36:21.161 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:36:21.633 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:36:22.104 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:36:22.577 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:36:23.049 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:36:23.521 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:36:23.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:36:23.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:23.908 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:36:23.908 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:36:23.924 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:36:23.924 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:36:23.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:36:23.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:23.926 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:36:23.926 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:36:23.926 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:36:23.926 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:36:23.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:36:23.976 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:36:23.977 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:36:23.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:23.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:23.992 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:36:24.466 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:36:24.938 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:36:25.410 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:36:25.884 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:36:26.356 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:36:26.828 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:36:27.299 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:36:27.773 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:36:28.245 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:36:28.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:36:28.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:28.379 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:36:28.379 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:36:28.396 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:36:28.396 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:36:28.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:36:28.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:28.398 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:36:28.398 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:36:28.399 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:36:28.399 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:36:28.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:36:28.448 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:36:28.448 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:36:28.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:28.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:28.717 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:36:29.188 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:36:29.662 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:36:30.134 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:36:30.605 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:36:31.076 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:36:31.550 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:36:32.022 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 01:36:32.495 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 01:36:32.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:36:32.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:32.646 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:36:32.646 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:36:32.663 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:36:32.663 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:36:32.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:36:32.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:32.666 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:36:32.666 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:36:32.666 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:36:32.666 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:36:32.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:36:32.718 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:36:32.718 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:36:32.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:32.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:32.968 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 01:36:33.441 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 01:36:33.913 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 01:36:34.384 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 01:36:34.858 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 01:36:35.330 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 01:36:35.803 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 01:36:36.276 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 01:36:36.749 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 01:36:37.220 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 01:36:37.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:36:37.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:37.275 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:36:37.275 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:36:37.291 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:36:37.291 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:36:37.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:36:37.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:37.294 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:36:37.294 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:36:37.294 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:36:37.294 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:36:37.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:36:37.344 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:36:37.344 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:36:37.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:37.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:37.691 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 01:36:38.164 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 01:36:38.637 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 01:36:39.109 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 01:36:39.580 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 01:36:40.054 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 01:36:40.527 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 01:36:41.000 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 01:36:41.473 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 01:36:41.945 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 01:36:42.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:36:42.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:42.152 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:36:42.152 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:36:42.168 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:36:42.168 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:36:42.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:36:42.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:42.171 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:36:42.171 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:36:42.171 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:36:42.171 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:36:42.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:36:42.223 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:36:42.224 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:36:42.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:42.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:42.419 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 01:36:42.891 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 01:36:43.364 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 01:36:43.835 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 01:36:44.308 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 01:36:44.781 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 01:36:45.253 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 01:36:45.727 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 01:36:46.199 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 01:36:46.672 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 01:36:47.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:36:47.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:47.029 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:36:47.029 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:36:47.043 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:36:47.043 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:36:47.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:36:47.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:47.046 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:36:47.047 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:36:47.047 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:36:47.047 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:36:47.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:36:47.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:36:47.100 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:36:47.101 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:36:47.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:47.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:47.145 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 01:36:47.617 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 01:36:48.089 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 01:36:48.560 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 01:36:49.031 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 01:36:49.502 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 01:36:49.976 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-06 01:36:50.448 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-06 01:36:50.921 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-06 01:36:51.394 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-06 01:36:51.867 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-06 01:36:51.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:36:51.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:51.909 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:36:51.909 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:36:51.924 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:36:51.924 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:36:51.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:36:51.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:51.927 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:36:51.927 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:36:51.927 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:36:51.927 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:36:51.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:36:51.979 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:36:51.980 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:36:51.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:51.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:52.338 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-06 01:36:52.811 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-06 01:36:53.283 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-06 01:36:53.756 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-06 01:36:54.230 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-06 01:36:54.702 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-06 01:36:55.174 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-06 01:36:55.648 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-06 01:36:56.120 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-06 01:36:56.592 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-06 01:36:56.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:36:56.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:56.785 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:36:56.785 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:36:56.802 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:36:56.802 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:36:56.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:36:56.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:56.804 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:36:56.804 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:36:56.804 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:36:56.804 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:36:56.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:36:56.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:36:56.856 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:36:56.856 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:36:56.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:56.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:36:57.063 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-06 01:36:57.536 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-06 01:36:58.009 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-06 01:36:58.481 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-06 01:36:58.955 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-06 01:36:59.428 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-06 01:36:59.900 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-06 01:37:00.374 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-06 01:37:00.846 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-06 01:37:01.318 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-06 01:37:01.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:01.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:01.542 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:01.542 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:01.553 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:01.553 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:01.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:37:01.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:01.555 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:01.555 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:01.555 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:37:01.555 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:37:01.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:01.607 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:01.607 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:01.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:01.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:01.789 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-06 01:37:02.260 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-06 01:37:02.734 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-06 01:37:03.206 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-06 01:37:03.677 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-06 01:37:04.151 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-06 01:37:04.623 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-06 01:37:05.095 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-06 01:37:05.566 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-06 01:37:06.040 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-06 01:37:06.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:06.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:06.360 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:06.360 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:06.377 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:06.377 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:06.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:37:06.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:06.379 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:06.379 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:06.379 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:37:06.379 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:37:06.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:06.427 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:06.427 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:06.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:06.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:06.512 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-06 01:37:06.985 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-06 01:37:07.458 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-06 01:37:07.931 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-06 01:37:08.403 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-06 01:37:08.876 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-06 01:37:09.349 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-06 01:37:09.821 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-06 01:37:10.292 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-06 01:37:10.766 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-06 01:37:11.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:11.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:11.237 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:11.237 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:11.238 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-06 01:37:11.244 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:11.244 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:11.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:37:11.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:11.246 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:11.246 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:11.246 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:37:11.246 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:37:11.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:11.295 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:11.295 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:11.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:11.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:11.710 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-06 01:37:12.181 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-06 01:37:12.652 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-06 01:37:13.125 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-06 01:37:13.598 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-06 01:37:14.070 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-06 01:37:14.541 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-06 01:37:15.014 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-06 01:37:15.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:15.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:15.339 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:15.339 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:15.358 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:15.358 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:15.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:37:15.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:15.360 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:15.360 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:15.360 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:37:15.360 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:37:15.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:15.412 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:15.413 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:15.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:15.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:15.486 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-06 01:37:15.959 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-06 01:37:16.429 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-06 01:37:16.901 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-06 01:37:17.375 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-06 01:37:17.846 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-06 01:37:18.318 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-06 01:37:18.788 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-06 01:37:19.262 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-06 01:37:19.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:19.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:19.605 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:19.605 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:19.624 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:19.624 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:19.624 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:37:19.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:19.627 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:19.627 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:19.627 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:37:19.627 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:37:19.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:19.680 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:19.680 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:19.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:19.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:19.734 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-06 01:37:20.206 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-06 01:37:20.677 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-06 01:37:21.151 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-06 01:37:21.623 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-06 01:37:22.094 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-06 01:37:22.566 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-06 01:37:23.039 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-06 01:37:23.511 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-06 01:37:23.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:23.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:23.872 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:23.872 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:23.891 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:23.891 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:23.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:37:23.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:23.893 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:23.893 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:23.894 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:37:23.894 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:37:23.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:23.943 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:23.943 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:23.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:23.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:23.983 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-06 01:37:24.455 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-06 01:37:24.928 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-06 01:37:25.400 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-06 01:37:25.872 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-06 01:37:26.343 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-06 01:37:26.817 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-06 01:37:27.289 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-06 01:37:27.761 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-06 01:37:28.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:28.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:28.139 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:28.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:28.156 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:28.156 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:28.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:37:28.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:28.159 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:28.159 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:28.159 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:37:28.159 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:37:28.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:28.210 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:28.210 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:28.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:28.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:28.232 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-06 01:37:28.703 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-06 01:37:29.176 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-06 01:37:29.649 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-06 01:37:30.121 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-06 01:37:30.592 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-06 01:37:31.063 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-06 01:37:31.536 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-06 01:37:32.008 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-06 01:37:32.480 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-06 01:37:32.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:32.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:32.568 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:32.568 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:32.584 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:32.585 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:32.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:37:32.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:32.587 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:32.587 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:32.587 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:37:32.587 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:37:32.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:32.639 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:32.639 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:32.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:32.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:32.953 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-06 01:37:33.426 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-06 01:37:33.898 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-06 01:37:34.369 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-06 01:37:34.843 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-06 01:37:35.315 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-06 01:37:35.787 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-06 01:37:36.258 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-06 01:37:36.732 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-06 01:37:36.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:36.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:36.841 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:36.842 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:36.850 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:36.850 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:36.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:37:36.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:36.852 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:36.852 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:36.852 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:37:36.852 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:37:36.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:36.905 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:36.905 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:36.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:36.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:37.204 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-06 01:37:37.676 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-06 01:37:38.147 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-06 01:37:38.618 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-06 01:37:39.088 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-06 01:37:39.562 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-06 01:37:40.034 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-06 01:37:40.505 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-06 01:37:40.977 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-03-06 01:37:41.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:41.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:41.107 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:41.107 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:41.125 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:41.125 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:41.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:37:41.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:41.127 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:41.127 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:41.127 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:37:41.127 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:37:41.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:41.176 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:41.176 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:41.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:41.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:41.450 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-03-06 01:37:41.922 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-03-06 01:37:42.394 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-03-06 01:37:42.865 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-03-06 01:37:43.337 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-03-06 01:37:43.810 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-03-06 01:37:44.283 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-03-06 01:37:44.754 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-03-06 01:37:45.227 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-03-06 01:37:45.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:45.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:45.373 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:45.373 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:45.383 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:37:45.383 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:37:45.383 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:37:45.383 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:37:45.384 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:37:45.384 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:37:45.384 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:37:45.384 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:37:45.384 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:37:45.384 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:37:45.384 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:37:50.391 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:37:50.391 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:37:50.391 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:37:50.391 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:37:50.391 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:37:50.391 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:37:50.397 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:37:50.398 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:37:50.398 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:37:50.398 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:37:50.398 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:37:50.402 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:37:50.402 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:37:50.402 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:37:50.402 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:37:50.403 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:37:50.403 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:37:50.403 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:37:50.403 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:37:50.404 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:37:50.405 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:37:50.405 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:37:50.405 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:37:50.405 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:37:50.405 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:37:50.405 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:37:50.405 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:37:50.405 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:37:50.405 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:37:50.407 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:37:50.407 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:37:50.408 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:37:50.408 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:37:50.408 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:37:50.408 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:37:50.408 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:37:50.408 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:37:50.408 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:37:50.410 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:37:50.410 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:37:50.410 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:37:50.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:37:50.410 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:37:50.410 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:37:50.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:37:50.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:37:50.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:37:50.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:37:50.411 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:37:50.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:37:50.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:37:50.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:37:50.411 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:37:50.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:37:50.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:37:50.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:37:50.411 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:37:50.411 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:37:50.411 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:37:50.411 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:37:50.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:37:50.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:37:50.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:37:50.412 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:37:50.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:37:50.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:37:50.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:37:50.412 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:37:50.412 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:37:50.412 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:37:50.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:37:50.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:37:50.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:37:55.419 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:37:55.419 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:37:55.420 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:37:55.420 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:37:55.420 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:37:55.420 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:37:55.427 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:37:55.428 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:37:55.428 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:37:55.429 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:37:55.429 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:37:55.432 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:37:55.432 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:37:55.433 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:37:55.433 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:37:55.433 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:37:55.433 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:37:55.434 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:37:55.434 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:37:55.434 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:37:55.435 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:37:55.436 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:37:55.436 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:37:55.436 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:37:55.436 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:37:55.436 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:37:55.436 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:37:55.436 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:37:55.436 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:37:55.438 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:37:55.439 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:37:55.439 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:37:55.439 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:37:55.439 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:37:55.439 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:37:55.439 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:37:55.439 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:37:55.439 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:37:55.442 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:37:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:37:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:37:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:37:55.442 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:37:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:37:55.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:37:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:37:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:37:55.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:37:55.443 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:37:55.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:37:55.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:37:55.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:37:55.443 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:37:55.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:37:55.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:37:55.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:37:55.443 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:37:55.443 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:37:55.443 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:37:55.443 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:37:55.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:37:55.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:37:55.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:37:55.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:37:55.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:37:55.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:37:55.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:37:55.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:37:55.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:37:55.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:37:55.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:37:55.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:37:55.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:37:55.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:37:55.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:37:55.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:37:55.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:37:55.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:37:55.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:37:55.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:37:55.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:37:55.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:37:55.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:37:55.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:37:55.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:37:55.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:37:55.448 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:37:55.926 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:37:55.971 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:37:55.972 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:37:55.974 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:37:55.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:55.989 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:55.989 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:55.990 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:37:55.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:55.996 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:55.996 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:55.996 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:37:55.996 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:37:56.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:56.032 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:56.032 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:56.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:56.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:56.398 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:37:56.446 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:37:56.446 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:37:56.447 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:37:56.447 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:37:56.869 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:37:57.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:57.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:57.072 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:57.073 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:57.089 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:57.089 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:57.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:37:57.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:57.092 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:57.092 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:57.092 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:37:57.092 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:37:57.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:57.144 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:57.144 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:57.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:57.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:57.342 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:37:57.448 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:37:57.448 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:37:57.448 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:37:57.448 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:37:57.815 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:37:58.287 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:37:58.449 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:37:58.449 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:37:58.449 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:37:58.449 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:37:58.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:58.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:58.510 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:58.510 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:58.519 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:58.519 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:58.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:37:58.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:58.521 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:58.521 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:58.521 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:37:58.521 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:37:58.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:58.576 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:58.577 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:58.577 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:58.577 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:58.758 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:37:59.229 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:37:59.450 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:37:59.450 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:37:59.450 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:37:59.450 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:37:59.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:59.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:59.669 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:59.669 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:59.685 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:37:59.685 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:37:59.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:37:59.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:59.688 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:59.688 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:59.688 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:37:59.688 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:37:59.701 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:37:59.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:37:59.739 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:37:59.739 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:37:59.739 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:37:59.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:00.174 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:38:00.451 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:38:00.468 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:38:00.468 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:38:00.468 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:38:00.646 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:38:01.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:01.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:01.104 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:01.104 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:01.120 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:38:01.124 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:01.124 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:01.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:38:01.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:01.127 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:01.127 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:01.127 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:38:01.127 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:38:01.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:01.176 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:01.176 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:01.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:01.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:01.592 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:38:02.065 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:38:02.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:02.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:02.187 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:02.187 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:02.203 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:02.203 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:02.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:38:02.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:02.206 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:02.206 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:02.206 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:38:02.206 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:38:02.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:02.257 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:02.257 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:02.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:02.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:02.536 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:38:03.009 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:38:03.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:03.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:03.210 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:03.210 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:03.227 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:03.227 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:03.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:38:03.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:03.229 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:03.229 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:03.229 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:38:03.229 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:38:03.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:03.280 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:03.280 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:03.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:03.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:03.481 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:38:03.953 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:38:04.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:04.230 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:04.230 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:04.231 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:04.247 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:04.247 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:04.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:38:04.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:04.250 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:04.251 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:04.251 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:38:04.251 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:38:04.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:38:04.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:04.301 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:04.301 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:04.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:04.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:04.426 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:38:04.899 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:38:05.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:05.256 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:05.256 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:05.257 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:05.275 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:05.275 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:05.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:38:05.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:05.278 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:05.278 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:05.278 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:38:05.278 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:38:05.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:05.322 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:05.322 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:05.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:05.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:05.369 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:38:05.841 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:38:06.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:06.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:06.277 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:06.277 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:06.297 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:06.297 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:06.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:38:06.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:06.300 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:06.300 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:06.300 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:38:06.300 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:38:06.313 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:38:06.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:38:06.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:06.357 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:06.358 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:06.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:06.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:06.785 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:38:07.258 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:38:07.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:07.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:07.662 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:07.662 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:07.680 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:07.680 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:07.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:38:07.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:07.683 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:07.683 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:07.683 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:38:07.683 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:38:07.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:07.731 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:38:07.735 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:07.736 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:07.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:07.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:08.202 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:38:08.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:08.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:08.622 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:08.623 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:08.633 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:08.634 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:08.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:38:08.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:08.637 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:08.637 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:08.637 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:38:08.637 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:38:08.675 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:38:08.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:08.688 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:08.688 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:08.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:08.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:09.147 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:38:09.620 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:38:09.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:09.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:09.649 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:09.649 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:09.667 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:09.667 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:09.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:38:09.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:09.669 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:09.669 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:09.669 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:38:09.669 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:38:09.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:09.719 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:09.719 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:09.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:09.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:10.093 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:38:10.566 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:38:10.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:10.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:10.725 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:10.725 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:10.734 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:10.734 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:10.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:38:10.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:10.736 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:10.736 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:10.736 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:38:10.736 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:38:10.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:10.787 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:10.788 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:10.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:10.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:11.038 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:38:11.509 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:38:11.982 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:38:12.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:12.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:12.157 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:12.157 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:12.175 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:12.175 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:12.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:38:12.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:12.178 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:12.178 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:12.178 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:38:12.178 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:38:12.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:12.227 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:12.227 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:12.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:12.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:12.454 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 01:38:12.926 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 01:38:13.397 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 01:38:13.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:13.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:13.592 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:13.592 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:13.610 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:13.611 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:13.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:38:13.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:13.613 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:13.613 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:13.613 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:38:13.613 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:38:13.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:13.665 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:13.665 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:13.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:13.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:13.870 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 01:38:14.343 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 01:38:14.815 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 01:38:15.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:15.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:15.029 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:15.029 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:15.038 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:15.038 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:15.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:38:15.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:15.040 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:15.040 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:15.040 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:38:15.040 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:38:15.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:15.093 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:15.094 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:15.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:15.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:15.286 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 01:38:15.757 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 01:38:16.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:16.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:16.149 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:16.150 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:16.169 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:16.169 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:16.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:38:16.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:16.172 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:16.172 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:16.172 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:38:16.172 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:38:16.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:16.230 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 01:38:16.237 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:16.237 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:16.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:16.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:16.702 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 01:38:17.174 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 01:38:17.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:17.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:17.586 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:17.586 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:17.603 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:17.603 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:17.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:38:17.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:17.606 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:17.606 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:17.606 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:38:17.606 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:38:17.645 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 01:38:17.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:17.656 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:17.656 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:17.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:17.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:18.119 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 01:38:18.591 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 01:38:19.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:19.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:19.023 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:19.024 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:19.042 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:19.042 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:19.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:38:19.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:19.045 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:19.045 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:19.045 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:38:19.045 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:38:19.063 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 01:38:19.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:19.099 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:19.100 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:19.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:19.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:19.534 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 01:38:20.007 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 01:38:20.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:20.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:20.473 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:20.474 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:20.480 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 01:38:20.484 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:38:20.485 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:38:20.485 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:38:20.485 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:38:20.487 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:38:20.487 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:38:20.487 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:38:20.487 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:38:20.487 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:38:20.487 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:38:20.487 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:38:25.492 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:38:25.492 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:38:25.492 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:38:25.492 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:38:25.492 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:38:25.492 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:38:25.499 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:38:25.500 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:38:25.500 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:38:25.501 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:38:25.501 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:38:25.505 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:38:25.505 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:38:25.505 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:38:25.505 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:38:25.506 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:38:25.506 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:38:25.506 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:38:25.506 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:38:25.506 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:38:25.510 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:38:25.510 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:38:25.511 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:38:25.511 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:38:25.511 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:38:25.511 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:38:25.511 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:38:25.511 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:38:25.511 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:38:25.515 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:38:25.515 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:38:25.515 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:38:25.515 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:38:25.515 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:38:25.515 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:38:25.515 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:38:25.515 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:38:25.516 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:38:25.520 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:38:25.520 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:38:25.520 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:38:25.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:38:25.521 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:38:25.521 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:38:25.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:38:25.521 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:38:25.521 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:38:25.521 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:38:25.521 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:38:25.521 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:38:25.521 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:38:25.521 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:38:25.521 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:38:25.521 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:38:25.521 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:38:25.521 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:38:25.521 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:38:25.521 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:38:25.521 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:38:25.521 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:38:25.522 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:38:25.522 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:38:25.522 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:38:25.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:38:25.522 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:38:25.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:38:25.522 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:38:25.522 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:38:25.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:38:25.522 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:38:25.522 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:38:25.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:38:25.522 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:38:25.522 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:38:25.522 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:38:25.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:38:25.522 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:38:25.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:38:25.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:38:25.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:38:25.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:38:25.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:38:25.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:38:25.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:38:25.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:38:25.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:38:25.526 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:38:26.005 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:38:26.054 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:38:26.056 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:38:26.058 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:38:26.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:26.076 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:26.077 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:26.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:38:26.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:26.082 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:26.082 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:26.082 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:38:26.082 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:38:26.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:38:26.104 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:26.105 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:26.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:26.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:26.478 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:38:26.524 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:38:26.525 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:38:26.525 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:38:26.526 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:38:26.949 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:38:27.422 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:38:27.525 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:38:27.525 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:38:27.526 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:38:27.527 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:38:27.895 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:38:28.367 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:38:28.527 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:38:28.527 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:38:28.527 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:38:28.528 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:38:28.841 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:38:29.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:29.314 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:38:29.527 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:38:29.528 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:38:29.528 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:38:29.530 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:38:29.785 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:38:29.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:29.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:29.859 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:29.859 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:29.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:38:29.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:29.860 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:29.860 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:29.860 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:38:29.860 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:38:29.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:38:29.878 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:29.878 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:29.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:29.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:30.258 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:38:30.529 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:38:30.529 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:38:30.530 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:38:30.531 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:38:30.731 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:38:31.203 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:38:31.677 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:38:32.149 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:38:32.622 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:38:32.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:33.095 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:38:33.568 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:38:33.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:33.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:33.718 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:33.718 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:33.735 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:33.735 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:33.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:38:33.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:33.737 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:33.737 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:33.737 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:38:33.737 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:38:33.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:38:33.785 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:33.786 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:33.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:33.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:34.040 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:38:34.514 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:38:34.986 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:38:35.458 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:38:35.929 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:38:36.400 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:38:36.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:36.871 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:38:37.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:37.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:37.324 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:37.324 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:37.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:38:37.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:37.325 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:37.325 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:37.326 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:38:37.326 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:38:37.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:38:37.342 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:38:37.343 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:37.343 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:37.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:37.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:37.813 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:38:38.283 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:38:38.754 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:38:39.228 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:38:39.700 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:38:40.172 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:38:40.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:40.643 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:38:41.117 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:38:41.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:41.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:41.175 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:41.175 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:41.191 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:41.191 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:41.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:38:41.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:41.193 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:41.193 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:41.193 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:38:41.194 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:38:41.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:38:41.240 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:41.240 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:41.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:41.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:41.589 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:38:42.060 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:38:42.533 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 01:38:43.006 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 01:38:43.478 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 01:38:43.949 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 01:38:44.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:44.420 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 01:38:44.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:44.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:44.859 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:44.859 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:44.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:38:44.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:44.860 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:44.860 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:44.860 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:38:44.860 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:38:44.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:38:44.891 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:44.891 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:44.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:44.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:44.893 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 01:38:45.366 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 01:38:45.838 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 01:38:46.309 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 01:38:46.782 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 01:38:47.255 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 01:38:47.727 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 01:38:47.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:48.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:48.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:48.165 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:48.166 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:48.184 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:48.184 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:48.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:38:48.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:48.186 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:48.186 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:48.186 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:38:48.186 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:38:48.197 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 01:38:48.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:38:48.233 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:48.233 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:48.233 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:48.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:48.669 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 01:38:49.142 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 01:38:49.614 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 01:38:50.086 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 01:38:50.557 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 01:38:51.030 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 01:38:51.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:51.502 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 01:38:51.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:51.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:51.897 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:51.897 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:51.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:38:51.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:51.898 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:51.898 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:51.899 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:38:51.899 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:38:51.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:38:51.924 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:38:51.925 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:38:51.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:51.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:51.974 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 01:38:52.445 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 01:38:52.919 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 01:38:53.391 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 01:38:53.863 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 01:38:54.334 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 01:38:54.807 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 01:38:54.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:55.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:38:55.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:38:55.198 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:38:55.198 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:38:55.206 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:38:55.207 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:38:55.207 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:38:55.207 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:38:55.211 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:38:55.211 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:38:55.211 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:38:55.211 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:38:55.211 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:38:55.211 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:38:55.211 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:38:55.212 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6414 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:38:55.212 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6414 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:38:55.212 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6414 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:38:55.212 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6414 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:38:55.212 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6414 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:38:55.212 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6414 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:39:00.215 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:39:00.215 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:39:00.215 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:39:00.215 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:39:00.215 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:39:00.215 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:39:00.221 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:39:00.223 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:39:00.223 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:39:00.223 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:39:00.223 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:39:00.227 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:39:00.227 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:39:00.227 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:39:00.228 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:39:00.228 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:39:00.228 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:39:00.228 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:39:00.229 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:39:00.229 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:39:00.231 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:39:00.231 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:39:00.231 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:39:00.231 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:39:00.231 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:39:00.231 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:39:00.232 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:39:00.232 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:39:00.232 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:39:00.234 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:39:00.234 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:39:00.234 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:39:00.234 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:39:00.234 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:39:00.235 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:39:00.235 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:39:00.235 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:39:00.235 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:39:00.237 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:39:00.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:39:00.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:39:00.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:39:00.237 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:39:00.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:39:00.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:39:00.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:39:00.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:39:00.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:39:00.238 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:39:00.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:39:00.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:39:00.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:39:00.238 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:39:00.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:39:00.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:39:00.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:39:00.238 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:39:00.238 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:39:00.238 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:39:00.238 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:39:00.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:39:00.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:39:00.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:39:00.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:39:00.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:39:00.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:39:00.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:39:00.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:39:00.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:39:00.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:39:00.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:39:00.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:39:00.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:39:00.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:39:00.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:39:00.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:39:00.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:39:00.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:39:00.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:39:00.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:39:00.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:39:00.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:39:00.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:39:00.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:39:00.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:39:00.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:39:00.243 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:39:00.720 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:39:00.770 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:39:00.773 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:39:00.775 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:39:00.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:00.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:39:00.801 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:39:00.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:39:00.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:00.807 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:00.807 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:00.807 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:39:00.807 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:39:00.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:39:00.816 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:00.817 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:00.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:00.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:01.193 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:39:01.241 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:39:01.241 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:39:01.241 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:39:01.241 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:39:01.664 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:39:02.138 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:39:02.242 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:39:02.243 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:39:02.243 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:39:02.243 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:39:02.610 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:39:03.082 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:39:03.244 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:39:03.244 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:39:03.244 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:39:03.244 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:39:03.556 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:39:03.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:04.029 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:39:04.245 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:39:04.245 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:39:04.245 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:39:04.245 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:39:04.500 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:39:04.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:04.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:04.573 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:39:04.574 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:39:04.574 [WARNING] transceiver.py:257 (MS@172.18.59.22:6700) RX TRXD message (fn=936 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:39:04.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:39:04.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:04.574 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:04.574 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:04.575 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:39:04.575 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:39:04.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:39:04.592 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:04.593 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:04.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:04.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:04.973 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:39:05.246 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:39:05.247 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:39:05.247 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:39:05.247 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:39:05.446 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:39:05.918 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:39:06.389 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:39:06.862 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:39:07.335 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:39:07.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:07.807 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:39:08.278 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:39:08.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:08.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:08.426 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:39:08.426 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:39:08.426 [WARNING] transceiver.py:257 (MS@172.18.59.22:6700) RX TRXD message (fn=1768 tn=7 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:39:08.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:39:08.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:08.427 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:08.427 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:08.427 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:39:08.427 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:39:08.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:39:08.463 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:08.463 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:08.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:08.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:08.749 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:39:09.223 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:39:09.695 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:39:10.167 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:39:10.638 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:39:11.111 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:39:11.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:11.584 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:39:12.056 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:39:12.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:12.279 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:12.279 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:39:12.279 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:39:12.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:39:12.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:12.280 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:12.280 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:12.280 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:39:12.280 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:39:12.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:39:12.294 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:12.294 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:12.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:12.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:12.527 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:39:12.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:13.001 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:39:13.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:13.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:13.238 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:39:13.238 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:39:13.238 [WARNING] transceiver.py:257 (MS@172.18.59.22:6700) RX TRXD message (fn=2808 tn=4 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:39:13.256 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:39:13.256 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:39:13.256 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:39:13.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:13.258 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:13.259 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:13.259 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:39:13.259 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:39:13.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:39:13.305 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:13.305 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:13.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:13.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:13.473 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:39:13.945 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:39:14.419 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:39:14.891 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:39:15.364 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:39:15.837 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:39:16.310 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:39:16.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:16.782 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:39:16.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:16.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:16.856 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:39:16.857 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:39:16.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:39:16.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:16.857 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:16.858 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:16.858 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:39:16.858 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:39:16.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:39:16.875 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:16.875 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:16.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:16.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:17.253 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 01:39:17.724 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 01:39:18.197 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 01:39:18.670 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 01:39:19.142 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 01:39:19.613 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 01:39:19.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:20.087 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 01:39:20.559 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 01:39:20.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:20.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:20.708 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:39:20.708 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:39:20.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:39:20.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:20.710 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:20.711 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:20.711 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:39:20.711 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:39:20.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:39:20.745 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:20.745 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:20.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:20.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:21.031 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 01:39:21.515 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 01:39:21.987 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 01:39:22.458 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 01:39:22.932 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 01:39:23.404 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 01:39:23.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:23.876 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 01:39:24.347 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 01:39:24.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:24.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:24.569 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:39:24.569 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:39:24.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:39:24.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:24.571 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:24.571 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:24.571 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:39:24.571 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:39:24.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:39:24.583 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:24.583 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:24.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:24.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:24.821 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 01:39:25.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:25.293 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 01:39:25.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:25.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:25.534 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:39:25.534 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:39:25.552 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:39:25.552 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:39:25.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:39:25.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:25.554 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:25.554 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:25.554 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:39:25.554 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:39:25.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:39:25.601 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:25.602 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:25.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:25.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:25.765 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 01:39:26.236 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 01:39:26.710 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 01:39:27.182 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 01:39:27.653 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 01:39:28.124 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 01:39:28.597 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 01:39:28.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:29.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:29.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:29.034 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:39:29.034 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:39:29.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:39:29.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:29.034 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:29.034 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:29.034 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:39:29.034 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:39:29.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:39:29.065 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:29.065 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:29.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:29.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:29.070 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 01:39:29.542 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 01:39:30.015 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 01:39:30.488 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 01:39:30.960 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 01:39:31.431 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 01:39:31.904 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 01:39:32.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:32.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:32.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:32.340 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:39:32.340 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:39:32.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:39:32.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:32.341 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:32.341 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:32.341 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:39:32.341 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:39:32.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:39:32.373 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:32.373 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:32.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:32.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:32.376 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 01:39:32.848 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 01:39:33.320 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 01:39:33.793 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 01:39:34.265 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 01:39:34.738 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 01:39:35.208 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-06 01:39:35.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:35.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:35.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:35.648 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:39:35.648 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:39:35.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:39:35.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:35.648 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:35.649 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:35.649 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:39:35.649 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:39:35.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:39:35.681 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:35.681 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:35.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:35.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:35.682 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-06 01:39:36.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:36.154 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-06 01:39:36.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:36.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:36.594 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:39:36.594 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:39:36.612 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:39:36.612 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:39:36.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:39:36.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:36.614 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:36.614 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:36.614 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:39:36.614 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:39:36.626 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-06 01:39:36.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:39:36.661 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:36.661 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:36.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:36.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:37.097 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-06 01:39:37.571 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-06 01:39:38.043 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-06 01:39:38.515 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-06 01:39:38.986 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-06 01:39:39.460 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-06 01:39:39.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:39.932 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-06 01:39:40.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:40.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:40.327 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:39:40.327 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:39:40.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:39:40.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:40.329 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:40.330 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:40.330 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:39:40.330 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:39:40.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:39:40.354 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:40.355 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:40.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:40.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:40.404 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-06 01:39:40.875 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-06 01:39:41.349 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-06 01:39:41.821 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-06 01:39:42.293 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-06 01:39:42.764 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-06 01:39:43.238 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-06 01:39:43.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:43.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:43.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:43.629 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:39:43.629 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:39:43.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:39:43.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:43.630 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:43.630 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:43.630 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:39:43.630 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:39:43.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:39:43.655 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:43.655 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:43.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:43.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:43.710 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-06 01:39:44.182 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-06 01:39:44.653 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-06 01:39:45.126 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-06 01:39:45.599 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-06 01:39:46.070 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-06 01:39:46.542 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-06 01:39:46.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:46.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:46.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:46.935 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:39:46.935 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:39:46.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:39:46.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:46.936 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:46.936 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:46.936 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:39:46.936 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:39:46.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:39:46.962 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:46.962 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:46.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:46.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:47.015 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-06 01:39:47.488 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-06 01:39:47.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:47.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:47.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:47.882 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:39:47.882 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:39:47.890 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:39:47.890 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:39:47.890 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:39:47.890 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:39:47.891 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:39:47.891 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:39:47.891 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:39:47.891 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:39:47.891 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:39:47.891 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:39:47.891 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:39:52.897 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:39:52.897 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:39:52.897 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:39:52.897 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:39:52.897 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:39:52.897 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:39:52.905 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:39:52.906 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:39:52.906 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:39:52.907 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:39:52.907 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:39:52.910 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:39:52.911 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:39:52.911 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:39:52.911 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:39:52.912 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:39:52.912 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:39:52.913 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:39:52.913 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:39:52.913 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:39:52.915 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:39:52.915 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:39:52.915 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:39:52.915 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:39:52.915 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:39:52.915 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:39:52.915 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:39:52.915 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:39:52.916 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:39:52.918 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:39:52.918 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:39:52.918 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:39:52.918 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:39:52.918 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:39:52.918 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:39:52.919 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:39:52.919 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:39:52.919 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:39:52.922 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:39:52.922 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:39:52.922 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:39:52.922 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:39:52.922 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:39:52.922 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:39:52.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:39:52.922 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:39:52.922 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:39:52.922 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:39:52.922 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:39:52.922 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:39:52.922 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:39:52.922 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:39:52.922 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:39:52.922 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:39:52.922 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:39:52.922 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:39:52.922 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:39:52.922 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:39:52.922 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:39:52.923 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:39:52.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:39:52.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:39:52.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:39:52.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:39:52.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:39:52.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:39:52.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:39:52.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:39:52.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:39:52.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:39:52.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:39:52.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:39:52.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:39:52.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:39:52.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:39:52.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:39:52.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:39:52.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:39:52.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:39:52.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:39:52.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:39:52.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:39:52.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:39:52.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:39:52.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:39:52.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:39:52.927 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:39:53.406 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:39:53.449 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:39:53.450 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:39:53.451 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:39:53.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:39:53.455 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:39:53.455 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:39:53.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:39:53.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:39:53.457 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:39:53.457 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:39:53.458 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:39:53.458 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:39:53.878 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:39:53.926 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:39:53.926 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:39:53.927 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:39:53.927 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:39:54.349 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:39:54.819 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:39:54.927 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:39:54.928 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:39:54.928 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:39:54.928 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:39:55.291 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:39:55.763 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:39:55.928 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:39:55.928 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:39:55.929 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:39:55.929 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:39:56.232 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:39:56.702 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:39:56.929 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:39:56.929 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:39:56.929 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:39:56.929 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:39:57.174 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:39:57.644 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:39:57.930 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:39:57.930 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:39:57.930 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:39:57.931 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:39:58.115 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:39:58.586 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:39:59.056 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:39:59.527 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:39:59.998 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:40:00.468 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:40:00.940 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:40:01.410 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:40:01.881 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:40:02.252 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:02.252 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:02.257 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:02.257 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:02.257 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:02.257 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:02.261 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:40:02.261 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:40:02.261 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:40:02.261 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:40:02.261 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:40:02.261 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:40:02.261 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:40:02.261 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2022 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:02.261 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2022 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:02.261 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2022 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:02.261 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2022 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:02.261 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2022 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:02.261 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2022 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:07.264 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:40:07.265 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:40:07.265 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:40:07.265 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:40:07.265 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:40:07.265 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:40:07.272 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:40:07.273 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:40:07.273 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:40:07.273 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:40:07.273 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:40:07.275 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:40:07.276 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:40:07.276 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:40:07.276 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:40:07.276 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:40:07.277 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:40:07.277 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:40:07.277 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:40:07.277 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:07.278 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:40:07.278 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:40:07.278 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:40:07.278 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:40:07.279 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:40:07.279 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:40:07.279 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:40:07.279 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:40:07.279 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:07.281 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:40:07.281 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:40:07.281 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:40:07.281 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:40:07.281 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:40:07.281 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:40:07.281 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:40:07.281 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:40:07.281 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:07.283 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:40:07.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:40:07.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:40:07.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:40:07.283 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:40:07.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:40:07.284 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:40:07.284 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:40:07.284 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:07.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:07.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:07.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:07.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:07.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:07.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:07.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:07.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:07.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:07.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:07.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:07.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:07.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:07.289 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:40:07.767 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:40:07.807 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:40:07.807 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:40:07.807 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:40:07.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:07.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:07.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:07.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:40:07.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:07.809 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:07.810 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:07.810 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:40:07.810 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:40:08.238 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:40:08.286 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:08.286 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:08.286 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:08.286 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:08.710 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:40:09.182 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:40:09.286 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:09.287 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:09.287 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:09.287 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:09.650 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:40:10.122 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:40:10.287 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:10.287 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:10.288 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:10.288 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:10.593 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:40:11.063 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:40:11.288 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:11.288 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:11.288 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:11.289 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:11.534 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:40:12.005 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:40:12.290 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:12.290 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:12.290 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:12.290 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:12.476 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:40:12.947 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:40:13.418 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:40:13.889 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:40:14.359 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:40:14.829 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:40:15.300 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:40:15.772 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:40:16.242 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:40:16.594 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:16.595 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:16.600 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:16.600 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:16.600 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:16.600 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:16.602 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:40:16.602 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:40:16.602 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:40:16.602 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:40:16.602 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:40:16.602 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:40:16.602 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:40:16.602 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2018 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:16.602 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2018 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:16.602 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2018 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:16.602 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2018 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:16.602 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2018 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:16.602 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2018 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:16.603 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2018 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:21.607 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:40:21.607 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:40:21.608 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:40:21.608 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:40:21.608 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:40:21.608 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:40:21.614 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:40:21.616 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:40:21.616 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:40:21.616 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:40:21.616 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:40:21.619 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:40:21.620 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:40:21.620 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:40:21.620 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:40:21.621 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:40:21.621 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:40:21.622 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:40:21.622 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:40:21.622 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:21.623 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:40:21.624 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:40:21.624 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:40:21.624 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:40:21.624 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:40:21.624 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:40:21.624 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:40:21.624 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:40:21.625 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:21.626 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:40:21.626 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:40:21.627 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:40:21.627 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:40:21.627 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:40:21.627 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:40:21.627 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:40:21.627 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:40:21.627 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:21.630 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:40:21.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:40:21.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:40:21.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:40:21.630 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:40:21.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:40:21.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:40:21.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:21.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:40:21.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:40:21.630 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:40:21.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:21.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:21.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:21.631 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:21.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:21.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:21.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:21.631 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:40:21.631 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:40:21.631 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:40:21.631 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:40:21.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:21.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:21.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:21.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:40:21.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:21.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:21.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:21.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:21.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:21.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:21.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:21.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:21.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:21.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:21.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:21.636 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:40:22.113 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:40:22.156 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:40:22.157 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:40:22.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:22.158 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:40:22.160 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:22.160 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:22.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:40:22.585 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:40:22.635 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:22.635 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:22.635 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:22.635 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:23.061 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:40:23.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:23.162 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:23.163 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:23.163 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:40:23.164 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:40:23.533 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:40:23.636 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:23.637 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:23.637 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:23.637 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:24.003 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:40:24.474 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:40:24.637 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:24.638 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:24.638 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:24.638 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:24.945 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:40:25.415 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:40:25.638 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:25.639 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:25.639 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:25.639 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:25.886 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:40:26.357 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:40:26.639 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:26.639 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:26.640 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:26.640 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:26.828 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:40:27.299 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:40:27.770 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:40:28.241 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:40:28.711 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:40:29.182 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:40:29.653 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:40:30.124 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:40:30.596 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:40:31.065 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:40:31.536 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:40:32.006 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:40:32.478 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:40:32.951 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:40:33.424 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:40:33.895 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:40:34.367 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:40:34.839 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:40:34.952 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:34.952 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:34.958 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:34.958 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:34.958 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:34.958 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:34.960 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:40:34.960 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:40:34.960 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:40:34.960 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:40:34.960 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:40:34.960 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:40:34.960 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:40:39.964 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:40:39.964 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:40:39.964 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:40:39.964 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:40:39.964 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:40:39.964 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:40:39.972 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:40:39.974 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:40:39.974 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:40:39.974 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:40:39.974 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:40:39.978 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:40:39.978 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:40:39.978 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:40:39.979 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:40:39.979 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:40:39.979 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:40:39.980 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:40:39.980 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:40:39.980 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:39.981 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:40:39.982 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:40:39.982 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:40:39.982 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:40:39.982 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:40:39.983 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:40:39.983 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:40:39.983 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:40:39.983 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:39.985 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:40:39.985 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:40:39.985 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:40:39.985 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:40:39.985 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:40:39.985 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:40:39.985 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:40:39.985 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:40:39.985 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:39.988 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:40:39.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:40:39.988 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:40:39.988 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:40:39.988 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:40:39.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:40:39.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:40:39.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:39.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:40:39.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:40:39.989 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:40:39.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:39.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:39.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:39.989 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:39.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:39.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:39.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:39.989 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:40:39.989 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:40:39.989 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:40:39.989 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:40:39.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:39.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:39.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:39.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:40:39.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:39.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:39.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:39.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:39.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:39.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:39.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:39.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:39.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:39.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:39.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:39.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:39.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:39.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:39.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:39.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:39.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:39.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:39.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:39.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:39.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:39.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:39.994 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:40:40.472 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:40:40.517 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:40:40.518 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:40:40.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:40.520 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:40:40.521 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:40.521 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:40.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:40:40.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:40.521 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:40.521 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:40.521 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:40:40.521 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:40:40.944 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:40:40.991 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:40.991 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:40.992 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:40.992 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:41.416 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:40:41.562 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:40:41.889 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:40:41.992 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:41.992 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:41.992 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:41.993 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:42.087 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:40:42.361 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:40:42.609 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:40:42.833 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:40:42.992 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:42.993 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:42.993 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:42.993 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:43.304 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:40:43.778 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:40:43.993 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:43.995 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:43.995 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:43.995 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:44.249 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:40:44.624 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:40:44.722 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:40:44.994 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:44.996 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:44.996 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:44.996 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:45.158 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:40:45.193 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:40:45.666 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:40:45.674 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:40:46.138 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:40:46.197 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:40:46.611 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:40:47.084 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:40:47.556 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:40:48.028 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:40:48.203 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:40:48.499 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:40:48.970 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:40:49.444 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:40:49.916 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:40:50.249 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:50.249 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:50.254 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:50.255 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:50.255 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:50.255 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:50.259 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:40:50.259 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:40:50.259 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:40:50.259 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:40:50.260 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:40:50.260 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:40:50.260 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:40:50.260 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2218 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:50.260 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2218 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:50.260 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2218 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:50.261 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2218 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:50.261 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2218 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:50.261 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2218 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:55.261 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:40:55.261 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:40:55.261 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:40:55.261 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:40:55.261 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:40:55.261 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:40:55.269 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:40:55.269 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:40:55.269 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:40:55.269 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:40:55.269 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:40:55.273 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:40:55.273 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:40:55.273 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:40:55.273 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:40:55.273 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:40:55.273 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:40:55.274 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:40:55.274 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:40:55.274 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:55.277 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:40:55.277 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:40:55.277 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:40:55.277 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:40:55.278 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:40:55.278 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:40:55.278 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:40:55.278 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:40:55.278 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:55.281 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:40:55.281 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:40:55.281 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:40:55.281 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:40:55.281 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:40:55.281 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:40:55.281 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:40:55.281 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:40:55.282 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:55.285 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:40:55.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:40:55.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:40:55.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:40:55.285 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:40:55.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:40:55.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:40:55.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:55.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:40:55.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:40:55.285 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:40:55.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:55.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:55.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:55.286 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:55.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:55.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:55.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:55.286 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:40:55.286 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:40:55.286 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:40:55.286 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:40:55.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:55.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:55.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:55.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:40:55.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:55.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:55.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:55.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:55.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:55.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:55.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:55.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:55.287 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:55.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:55.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:55.287 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:40:55.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:55.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:55.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:55.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:55.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:55.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:40:55.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:55.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:40:55.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:55.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:55.290 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:40:55.768 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:40:55.807 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:40:55.808 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:40:55.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:55.810 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:40:55.829 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:55.829 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:55.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:40:55.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:55.833 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:55.833 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:55.833 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:40:55.833 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:40:55.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:40:55.870 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:55.870 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:55.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:55.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:55.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:55.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:55.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:55.938 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:55.938 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:55.956 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:55.956 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:55.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:40:55.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:55.957 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:55.958 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:55.958 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:40:55.958 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:40:56.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:40:56.011 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:56.011 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:56.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:56.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:56.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.190 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:56.190 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:56.206 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:56.206 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:56.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:40:56.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.208 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:56.208 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:56.209 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:40:56.209 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:40:56.238 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:40:56.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:40:56.247 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:56.248 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:56.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.289 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:56.289 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:56.289 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:56.290 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:56.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:56.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:56.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.451 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:56.451 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:56.468 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:56.468 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:56.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:40:56.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.469 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:56.469 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:56.469 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:40:56.469 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:40:56.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:40:56.525 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:56.525 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:56.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:56.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:56.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.705 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:56.705 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:56.710 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:40:56.718 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:56.718 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:56.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:40:56.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.720 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:56.720 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:56.720 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:40:56.720 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:40:56.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:40:56.764 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:56.764 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:56.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:56.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:56.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.775 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:56.775 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:56.789 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:56.789 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:56.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:40:56.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.791 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:56.791 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:56.791 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:40:56.791 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:40:56.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:40:56.801 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:56.802 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:56.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:56.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:56.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.805 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:56.805 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:56.812 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:56.812 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:56.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:40:56.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.813 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:56.814 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:56.814 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:40:56.814 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:40:56.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:40:56.855 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:56.855 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:56.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:56.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:56.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.866 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:56.866 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:56.879 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:56.879 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:56.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:40:56.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.880 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:56.880 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:56.880 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:40:56.880 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:40:56.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:56.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:40:56.895 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:56.895 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:56.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:56.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:56.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.899 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:56.900 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:56.911 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:56.911 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:56.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:40:56.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.912 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:56.912 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:56.912 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:40:56.912 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:40:56.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:40:56.953 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:56.953 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:56.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:56.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:56.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.969 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:56.969 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:56.987 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:56.987 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:56.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:40:56.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:56.988 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:56.988 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:56.989 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:40:56.989 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:40:57.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:40:57.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:40:57.046 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:57.046 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:57.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.048 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:57.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:57.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.056 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:57.057 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:57.069 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:57.069 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:57.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:40:57.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.071 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:57.071 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:57.071 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:40:57.071 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:40:57.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:40:57.083 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:57.083 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:57.083 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.083 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:57.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:57.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.095 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:57.095 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:57.107 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:57.107 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:57.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:40:57.108 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.108 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:57.108 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:57.108 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:40:57.108 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:40:57.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:40:57.134 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:57.135 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:57.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:57.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:57.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.149 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:57.149 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:57.163 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:57.163 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:57.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:40:57.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.164 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:57.164 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:57.164 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:40:57.164 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:40:57.176 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:40:57.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:40:57.184 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:57.184 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:57.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:57.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:57.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.242 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:57.242 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:57.259 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:57.259 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:57.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:40:57.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.261 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:57.261 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:57.261 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:40:57.261 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:40:57.290 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:57.291 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:57.291 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:57.291 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:57.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:40:57.317 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:57.318 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:57.318 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.318 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:57.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:57.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.495 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:57.495 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:57.513 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:57.513 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:57.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:40:57.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.515 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:57.515 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:57.515 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:40:57.515 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:40:57.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:40:57.554 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:57.554 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:57.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.647 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:40:57.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:57.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:57.754 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.754 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:57.754 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:57.772 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:57.772 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:57.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:40:57.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.774 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:57.774 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:57.774 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:40:57.774 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:40:57.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:40:57.786 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:57.786 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:57.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:57.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:58.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:58.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:58.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:58.008 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:58.008 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:58.025 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:58.025 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:58.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:40:58.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:58.027 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:58.027 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:58.027 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:40:58.027 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:40:58.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:40:58.077 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:58.077 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:58.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:58.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:58.119 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:40:58.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:58.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:58.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:58.261 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:58.261 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:58.277 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:58.277 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:58.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:40:58.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:58.278 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:58.278 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:58.278 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:40:58.278 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:40:58.292 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:58.292 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:58.292 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:58.292 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:58.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:40:58.306 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:58.306 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:58.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:58.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:58.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:58.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:58.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:58.516 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:58.516 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:58.533 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:58.534 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:58.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:40:58.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:58.535 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:58.535 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:58.535 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:40:58.535 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:40:58.590 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:40:58.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:40:58.592 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:58.592 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:58.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:58.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:58.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:58.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:58.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:58.770 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:58.770 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:58.788 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:58.788 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:58.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:40:58.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:58.790 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:58.790 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:58.790 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:40:58.790 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:40:58.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:40:58.833 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:40:58.834 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:40:58.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:58.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:59.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:59.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:40:59.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:40:59.023 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:40:59.023 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:40:59.033 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:40:59.034 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:40:59.034 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:40:59.034 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:40:59.037 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:40:59.037 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:40:59.037 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:40:59.037 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:40:59.037 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:40:59.037 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:40:59.037 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:40:59.037 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=813 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:59.037 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=813 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:59.037 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=813 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:59.037 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=813 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:59.037 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=813 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:59.037 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=813 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:59.037 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=813 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:40:59.037 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=813 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:41:04.039 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:41:04.039 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:41:04.039 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:41:04.039 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:41:04.039 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:41:04.039 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:41:04.047 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:41:04.048 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:41:04.048 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:41:04.049 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:41:04.049 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:41:04.051 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:41:04.051 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:41:04.052 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:41:04.052 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:41:04.052 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:41:04.052 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:41:04.053 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:41:04.053 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:41:04.053 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:04.054 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:41:04.054 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:41:04.054 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:41:04.054 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:41:04.054 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:41:04.054 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:41:04.054 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:41:04.054 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:41:04.054 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:04.056 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:41:04.056 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:41:04.056 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:41:04.056 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:41:04.056 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:41:04.056 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:41:04.056 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:41:04.056 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:41:04.057 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:04.059 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:41:04.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:41:04.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:41:04.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:41:04.059 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:41:04.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:41:04.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:41:04.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:04.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:41:04.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:41:04.059 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:41:04.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:04.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:04.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:04.059 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:04.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:04.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:04.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:04.059 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:41:04.059 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:41:04.059 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:41:04.059 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:04.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:04.064 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:41:04.544 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:41:04.587 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:41:04.588 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:41:04.589 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:41:04.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:41:04.603 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:41:04.603 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:41:04.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:41:04.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:41:04.608 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:41:04.609 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:41:04.609 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:41:04.609 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:41:04.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 01:41:04.647 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:41:04.647 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:41:04.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:41:04.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:41:04.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:41:05.016 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:41:05.062 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:05.062 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:05.063 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:05.063 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:05.487 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:41:05.961 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:41:06.063 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:06.063 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:06.064 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:06.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:06.433 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:41:06.705 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:41:06.705 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:41:06.709 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:06.709 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:06.709 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:06.709 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:06.710 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:41:06.710 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:41:06.710 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:41:06.710 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:41:06.710 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:41:06.710 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:41:06.710 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:41:06.710 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=572 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:41:06.710 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=572 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:41:06.710 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=572 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:41:06.710 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=572 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:41:06.710 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=572 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:41:06.710 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=572 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:41:11.716 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:41:11.716 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:41:11.716 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:41:11.716 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:41:11.716 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:41:11.716 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:41:11.733 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:41:11.734 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:41:11.735 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:41:11.735 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:41:11.735 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:41:11.742 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:41:11.743 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:41:11.743 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:41:11.743 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:41:11.744 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:41:11.744 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:41:11.745 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:41:11.745 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:41:11.745 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:11.747 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:41:11.747 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:41:11.747 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:41:11.748 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:41:11.748 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:41:11.748 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:41:11.748 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:41:11.748 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:41:11.749 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:11.750 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:41:11.751 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:41:11.751 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:41:11.751 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:41:11.751 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:41:11.751 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:41:11.751 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:41:11.751 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:41:11.751 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:11.754 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:41:11.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:41:11.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:41:11.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:41:11.754 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:41:11.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:41:11.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:41:11.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:11.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:41:11.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:41:11.755 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:41:11.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:11.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:11.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:11.755 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:11.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:11.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:11.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:11.755 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:41:11.755 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:41:11.755 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:41:11.755 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:41:11.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:11.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:11.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:11.756 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:41:11.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:11.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:11.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:11.756 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:41:11.756 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:41:11.756 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:41:11.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:11.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:11.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:16.764 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:41:16.764 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:41:16.764 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:41:16.764 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:41:16.765 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:41:16.765 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:41:16.772 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:41:16.773 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:41:16.773 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:41:16.773 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:41:16.773 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:41:16.776 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:41:16.776 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:41:16.776 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:41:16.776 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:41:16.777 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:41:16.777 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:41:16.777 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:41:16.777 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:41:16.777 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:16.778 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:41:16.778 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:41:16.779 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:41:16.779 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:41:16.779 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:41:16.779 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:41:16.779 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:41:16.779 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:41:16.779 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:16.781 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:41:16.781 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:41:16.781 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:41:16.781 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:41:16.781 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:41:16.781 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:41:16.781 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:41:16.781 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:41:16.781 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:16.783 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:41:16.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:41:16.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:41:16.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:41:16.783 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:41:16.784 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:41:16.784 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:41:16.784 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:16.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:16.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:16.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:16.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:16.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:16.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:16.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:16.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:16.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:16.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:16.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:16.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:16.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:16.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:16.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:16.789 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:41:17.266 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:41:17.313 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:41:17.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:41:17.315 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:41:17.315 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:41:17.738 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:41:17.786 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:17.787 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:17.787 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:17.787 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:18.213 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:41:18.687 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:41:18.788 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:18.788 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:18.788 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:18.788 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:19.161 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:41:19.633 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:41:19.789 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:19.790 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:19.790 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:19.790 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:20.108 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:41:20.580 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:41:20.791 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:20.791 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:20.791 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:20.792 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:21.055 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:41:21.527 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:41:21.792 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:21.793 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:21.793 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:21.793 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:22.002 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:41:22.474 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:41:22.806 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:22.806 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:22.806 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:22.806 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:22.810 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:41:22.810 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:41:22.810 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:41:22.810 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:41:22.811 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:41:22.811 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:41:22.811 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:41:22.811 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1298 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:41:22.811 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1298 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:41:22.811 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1298 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:41:22.811 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1298 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:41:22.812 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1298 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:41:22.812 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1298 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:41:22.812 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1299 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:41:22.812 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1299 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:41:22.812 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1299 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:41:22.812 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1299 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:41:22.812 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1299 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:41:22.812 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1299 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:41:22.812 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1299 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:41:22.812 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1299 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:41:27.812 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:41:27.812 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:41:27.812 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:41:27.812 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:41:27.812 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:41:27.812 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:41:27.818 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:41:27.819 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:41:27.819 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:41:27.820 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:41:27.820 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:41:27.822 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:41:27.822 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:41:27.823 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:41:27.823 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:41:27.823 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:41:27.823 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:41:27.824 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:41:27.824 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:41:27.824 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:27.825 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:41:27.825 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:41:27.825 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:41:27.825 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:41:27.825 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:41:27.825 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:41:27.825 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:41:27.825 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:41:27.826 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:27.827 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:41:27.827 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:41:27.827 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:41:27.827 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:41:27.827 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:41:27.827 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:41:27.827 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:41:27.827 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:41:27.827 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:27.830 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:41:27.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:41:27.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:41:27.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:41:27.830 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:41:27.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:41:27.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:41:27.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:27.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:41:27.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:41:27.830 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:41:27.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:27.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:27.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:27.830 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:27.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:27.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:27.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:27.830 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:41:27.830 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:41:27.830 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:41:27.830 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:41:27.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:27.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:27.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:27.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:41:27.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:27.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:27.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:27.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:27.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:27.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:27.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:27.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:27.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:27.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:27.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:27.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:27.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:27.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:27.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:27.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:27.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:27.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:27.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:27.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:27.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:27.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:27.835 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:41:28.313 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:41:28.356 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:41:28.358 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:41:28.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:41:28.360 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:41:28.785 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:41:28.833 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:28.833 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:28.834 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:28.834 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:29.249 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:41:29.712 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:41:29.835 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:29.835 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:29.835 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:29.835 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:30.183 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:41:30.659 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:41:30.836 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:30.837 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:30.837 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:30.837 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:31.131 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:41:31.605 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:41:31.838 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:31.838 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:31.838 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:31.838 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:32.074 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:41:32.537 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:41:32.839 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:32.840 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:32.840 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:32.840 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:33.004 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:41:33.370 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:33.370 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:33.370 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:33.370 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:33.371 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:41:33.371 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:41:33.371 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:41:33.371 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:41:33.371 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:41:33.371 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:41:33.371 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:41:38.379 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:41:38.379 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:41:38.379 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:41:38.379 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:41:38.379 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:41:38.379 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:41:38.384 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:41:38.385 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:41:38.385 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:41:38.386 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:41:38.386 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:41:38.388 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:41:38.388 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:41:38.389 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:41:38.389 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:41:38.389 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:41:38.389 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:41:38.390 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:41:38.390 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:41:38.390 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:38.391 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:41:38.391 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:41:38.391 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:41:38.391 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:41:38.391 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:41:38.391 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:41:38.392 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:41:38.392 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:41:38.392 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:38.393 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:41:38.394 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:41:38.394 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:41:38.394 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:41:38.394 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:41:38.394 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:41:38.394 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:41:38.394 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:41:38.394 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:38.397 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:41:38.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:41:38.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:41:38.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:41:38.397 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:41:38.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:41:38.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:41:38.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:38.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:41:38.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:41:38.397 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:41:38.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:38.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:38.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:38.397 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:38.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:38.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:38.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:38.397 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:41:38.397 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:41:38.397 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:41:38.397 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:41:38.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:38.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:38.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:38.398 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:41:38.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:38.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:38.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:38.398 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:41:38.398 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:41:38.398 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:41:38.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:38.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:38.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:43.407 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:41:43.407 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:41:43.407 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:41:43.407 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:41:43.407 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:41:43.407 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:41:43.415 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:41:43.415 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:41:43.415 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:41:43.416 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:41:43.416 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:41:43.418 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:41:43.418 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:41:43.419 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:41:43.419 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:41:43.419 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:41:43.419 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:41:43.419 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:41:43.420 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:41:43.420 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:43.421 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:41:43.421 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:41:43.421 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:41:43.421 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:41:43.421 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:41:43.421 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:41:43.421 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:41:43.421 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:41:43.421 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:43.423 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:41:43.423 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:41:43.423 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:41:43.423 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:41:43.423 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:41:43.423 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:41:43.423 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:41:43.423 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:41:43.423 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:43.426 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:41:43.426 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:41:43.426 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:41:43.426 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:41:43.426 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:41:43.426 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:41:43.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:41:43.426 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:43.426 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:41:43.426 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:41:43.426 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:41:43.426 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:43.426 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:43.426 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:43.426 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:43.426 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:43.426 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:43.426 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:43.426 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:41:43.426 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:41:43.426 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:41:43.426 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:41:43.426 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:43.426 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:43.426 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:43.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:41:43.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:43.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:43.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:43.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:43.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:43.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:43.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:43.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:43.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:43.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:43.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:43.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:43.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:43.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:43.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:41:43.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:43.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:43.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:43.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:43.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:41:43.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:41:43.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:41:43.431 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:41:43.908 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:41:43.947 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:41:43.949 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:41:43.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:41:43.950 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:41:43.952 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:41:43.952 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:41:43.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:41:44.380 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:41:44.429 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:44.429 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:44.429 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:44.429 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:44.855 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:41:44.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:41:44.955 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:41:44.955 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:41:44.955 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:41:44.955 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:41:45.328 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:41:45.430 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:45.430 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:45.430 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:45.430 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:45.801 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:41:46.269 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:41:46.431 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:46.431 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:46.431 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:46.431 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:46.740 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:41:47.214 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:41:47.432 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:47.432 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:47.432 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:47.432 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:47.686 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:41:48.157 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:41:48.433 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:48.433 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:48.433 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:48.434 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:48.629 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:41:49.099 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:41:49.571 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:41:50.041 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:41:50.512 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:41:50.982 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:41:51.453 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:41:51.924 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:41:52.395 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:41:52.866 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:41:53.336 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:41:53.806 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:41:54.277 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:41:54.750 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:41:55.220 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:41:55.694 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:41:56.166 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:41:56.638 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:41:57.109 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:41:57.583 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:41:58.055 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:41:58.527 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:41:58.732 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:41:58.732 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:41:58.738 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:41:58.739 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:41:58.739 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:41:58.739 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:41:58.740 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:41:58.740 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:41:58.740 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:41:58.740 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:41:58.740 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:41:58.740 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:41:58.741 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:42:03.745 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:42:03.745 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:42:03.745 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:42:03.745 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:42:03.745 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:42:03.746 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:42:03.750 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:42:03.751 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:42:03.752 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:42:03.752 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:42:03.752 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:42:03.755 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:42:03.755 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:42:03.756 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:42:03.756 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:42:03.756 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:42:03.757 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:42:03.757 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:42:03.757 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:42:03.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:03.759 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:42:03.759 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:42:03.759 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:42:03.759 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:42:03.759 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:42:03.759 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:42:03.759 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:42:03.759 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:42:03.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:03.761 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:42:03.762 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:42:03.762 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:42:03.762 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:42:03.762 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:42:03.762 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:42:03.762 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:42:03.762 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:42:03.762 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:03.765 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:42:03.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:42:03.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:42:03.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:42:03.765 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:42:03.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:42:03.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:42:03.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:03.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:42:03.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:42:03.765 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:42:03.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:03.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:03.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:03.765 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:03.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:03.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:03.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:03.766 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:42:03.766 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:42:03.766 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:42:03.766 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:42:03.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:03.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:03.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:03.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:42:03.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:03.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:03.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:03.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:03.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:03.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:03.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:03.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:03.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:03.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:03.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:03.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:03.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:03.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:03.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:03.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:03.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:03.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:03.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:03.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:03.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:03.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:03.770 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:42:04.249 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:42:04.291 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:42:04.293 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:42:04.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:42:04.295 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:42:04.321 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:42:04.321 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:42:04.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:42:04.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:42:04.327 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:42:04.327 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:42:04.327 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:42:04.327 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:42:04.342 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:42:04.346 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:42:04.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:42:04.360 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:42:04.360 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:42:04.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:42:04.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:42:04.720 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:42:04.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:04.768 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:04.768 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:04.768 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:05.192 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:42:05.663 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:42:05.769 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:05.769 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:05.769 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:05.769 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:06.136 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:42:06.609 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:42:06.770 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:06.771 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:06.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:06.771 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:07.082 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:42:07.555 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:42:07.772 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:07.772 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:07.772 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:07.772 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:08.028 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:42:08.500 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:42:08.772 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:08.773 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:08.773 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:08.773 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:08.974 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:42:09.446 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:42:09.919 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:42:10.390 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:42:10.861 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:42:11.334 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:42:11.807 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:42:12.279 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:42:12.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:42:12.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:42:12.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:42:12.366 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:42:12.374 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:12.374 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:12.374 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:12.374 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:12.375 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:42:12.375 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:42:12.375 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:42:12.375 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:42:12.375 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:42:12.375 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:42:12.375 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:42:17.382 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:42:17.383 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:42:17.383 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:42:17.383 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:42:17.383 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:42:17.383 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:42:17.385 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:42:17.386 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:42:17.386 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:42:17.386 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:42:17.386 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:42:17.387 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:42:17.387 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:42:17.387 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:42:17.387 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:42:17.387 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:42:17.387 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:42:17.388 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:42:17.388 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:42:17.388 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:17.388 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:42:17.388 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:42:17.388 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:42:17.388 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:42:17.388 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:42:17.388 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:42:17.388 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:42:17.388 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:42:17.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:17.389 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:42:17.389 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:42:17.389 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:42:17.389 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:42:17.390 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:42:17.390 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:42:17.390 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:42:17.390 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:42:17.390 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:17.391 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:42:17.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:42:17.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:42:17.391 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:42:17.391 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:42:17.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:42:17.392 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:42:17.392 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:42:17.392 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:17.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:17.396 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:42:17.875 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:42:17.918 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:42:17.921 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:42:17.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:42:17.923 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:42:17.950 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:42:17.951 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:42:17.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:42:17.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:42:17.958 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:42:17.958 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:42:17.958 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:42:17.959 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:42:17.966 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:42:17.970 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:42:17.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:42:17.983 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:42:17.984 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:42:17.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:42:17.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:42:18.348 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:42:18.394 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:18.394 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:18.395 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:18.395 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:18.819 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:42:19.292 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:42:19.395 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:19.395 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:19.396 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:19.396 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:19.765 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:42:20.237 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:42:20.396 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:20.397 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:20.397 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:20.397 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:20.711 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:42:21.183 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:42:21.397 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:21.397 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:21.398 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:21.398 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:21.656 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:42:22.129 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:42:22.398 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:22.399 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:22.399 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:22.399 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:22.602 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:42:23.074 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:42:23.548 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:42:24.021 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:42:24.493 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:42:24.966 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:42:25.439 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:42:25.912 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:42:25.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:42:25.989 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:42:25.990 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:42:25.990 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:42:25.990 [WARNING] transceiver.py:257 (MS@172.18.59.22:6700) RX TRXD message (fn=1855 tn=3 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:42:26.000 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:26.000 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:26.001 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:26.001 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:26.003 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:42:26.003 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:42:26.003 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:42:26.003 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:42:26.003 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:42:26.003 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:42:26.003 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:42:26.003 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1858 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:42:26.003 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1858 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:42:26.003 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1858 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:42:26.003 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1858 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:42:26.003 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1858 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:42:26.003 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1858 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:42:31.007 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:42:31.007 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:42:31.007 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:42:31.007 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:42:31.007 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:42:31.007 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:42:31.015 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:42:31.016 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:42:31.017 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:42:31.017 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:42:31.017 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:42:31.020 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:42:31.020 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:42:31.020 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:42:31.020 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:42:31.021 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:42:31.021 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:42:31.021 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:42:31.021 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:42:31.021 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:31.022 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:42:31.022 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:42:31.023 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:42:31.023 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:42:31.023 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:42:31.023 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:42:31.023 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:42:31.023 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:42:31.023 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:31.025 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:42:31.025 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:42:31.025 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:42:31.025 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:42:31.025 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:42:31.025 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:42:31.025 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:42:31.025 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:42:31.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:31.028 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:42:31.028 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:42:31.028 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:42:31.028 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:42:31.028 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:42:31.028 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:42:31.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:42:31.028 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:31.028 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:42:31.028 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:42:31.028 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:42:31.028 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:31.028 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:31.028 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:31.028 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:31.028 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:31.028 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:31.028 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:31.028 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:42:31.028 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:42:31.028 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:42:31.028 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:42:31.028 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:31.028 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:31.028 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:31.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:42:31.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:31.029 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:31.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:31.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:31.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:31.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:31.029 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:31.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:31.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:31.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:31.029 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:31.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:31.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:31.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:31.029 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:31.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:31.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:31.029 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:31.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:31.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:31.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:31.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:31.033 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:42:31.510 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:42:31.552 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:42:31.554 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:42:31.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:42:31.558 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:42:31.580 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:42:31.581 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:42:31.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:42:31.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:42:31.585 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:42:31.586 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:42:31.586 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:42:31.586 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:42:31.602 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:42:31.605 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:42:31.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:42:31.615 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:42:31.615 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:42:31.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:42:31.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:42:31.982 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:42:32.030 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:32.030 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:32.030 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:32.031 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:32.453 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:42:32.926 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:42:33.032 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:33.032 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:33.032 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:33.032 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:33.399 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:42:33.871 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:42:34.032 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:34.033 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:34.033 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:34.033 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:34.342 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:42:34.813 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:42:35.033 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:35.034 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:35.034 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:35.034 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:35.287 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:42:35.759 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:42:36.035 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:36.035 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:36.035 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:36.035 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:36.231 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:42:36.702 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:42:37.176 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:42:37.648 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:42:38.121 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:42:38.591 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:42:39.062 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:42:39.533 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:42:39.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:42:39.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:42:39.622 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:42:39.623 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:42:39.642 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:42:39.642 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:42:39.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:42:39.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:42:39.644 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:42:39.644 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:42:39.644 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:42:39.644 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:42:39.669 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:42:39.673 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:42:39.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:42:39.686 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:42:39.686 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:42:39.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:42:39.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:42:40.006 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:42:40.479 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:42:40.951 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:42:41.422 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:42:41.895 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:42:42.368 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:42:42.840 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:42:43.314 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:42:43.787 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:42:44.259 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:42:44.732 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:42:45.205 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:42:45.677 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:42:46.151 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:42:46.623 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:42:47.095 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:42:47.566 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:42:47.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:42:47.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:42:47.693 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:42:47.693 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:42:47.702 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:47.702 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:47.703 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:47.703 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:47.705 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:42:47.705 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:42:47.705 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:42:47.705 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:42:47.705 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:42:47.705 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:42:47.705 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:42:47.705 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3602 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:42:47.705 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3602 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:42:47.705 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3602 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:42:47.705 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3602 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:42:47.705 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3602 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:42:47.705 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3602 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:42:52.708 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:42:52.708 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:42:52.708 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:42:52.708 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:42:52.708 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:42:52.708 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:42:52.716 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:42:52.717 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:42:52.717 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:42:52.717 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:42:52.717 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:42:52.720 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:42:52.721 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:42:52.721 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:42:52.721 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:42:52.722 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:42:52.722 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:42:52.722 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:42:52.722 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:42:52.722 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:52.724 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:42:52.724 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:42:52.724 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:42:52.724 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:42:52.724 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:42:52.724 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:42:52.725 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:42:52.725 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:42:52.725 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:52.726 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:42:52.726 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:42:52.726 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:42:52.726 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:42:52.726 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:42:52.726 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:42:52.726 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:42:52.726 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:42:52.727 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:52.729 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:42:52.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:42:52.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:42:52.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:42:52.729 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:42:52.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:42:52.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:42:52.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:52.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:42:52.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:42:52.729 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:42:52.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:52.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:52.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:42:52.730 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:42:52.730 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:42:52.730 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:42:52.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:52.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:42:52.734 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:42:53.213 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:42:53.255 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:42:53.258 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:42:53.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:42:53.261 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:42:53.289 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:42:53.289 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:42:53.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:42:53.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:42:53.297 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:42:53.297 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:42:53.297 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:42:53.297 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:42:53.306 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:42:53.308 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:42:53.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:42:53.325 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:42:53.325 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:42:53.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:42:53.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:42:53.686 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:42:53.732 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:53.732 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:53.732 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:53.733 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:54.157 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:42:54.627 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:42:54.733 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:54.733 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:54.733 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:54.733 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:55.098 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:42:55.569 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:42:55.734 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:55.734 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:55.734 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:55.735 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:56.042 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:42:56.515 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:42:56.735 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:56.735 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:56.735 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:56.735 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:56.988 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:42:57.461 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:42:57.736 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:42:57.736 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:42:57.736 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:42:57.736 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:42:57.933 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:42:58.405 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:42:58.878 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:42:59.351 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:42:59.823 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:43:00.294 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:43:00.765 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:43:01.238 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:43:01.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:43:01.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:43:01.332 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:43:01.332 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:43:01.332 [WARNING] transceiver.py:257 (MS@172.18.59.22:6700) RX TRXD message (fn=1859 tn=1 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:43:01.350 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:43:01.350 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:43:01.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:43:01.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:43:01.352 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:43:01.352 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:43:01.352 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:43:01.352 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:43:01.371 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:43:01.375 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:43:01.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:43:01.382 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:43:01.383 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:43:01.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:43:01.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:43:01.710 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:43:02.182 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:43:02.654 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:43:03.124 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:43:03.598 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:43:04.070 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:43:04.542 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:43:05.013 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:43:05.487 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:43:05.960 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:43:06.432 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:43:06.903 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:43:07.377 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:43:07.849 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:43:08.321 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:43:08.795 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:43:09.267 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:43:09.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:43:09.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:43:09.389 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:43:09.389 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:43:09.399 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:43:09.399 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:43:09.399 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:43:09.399 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:43:09.401 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:43:09.401 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:43:09.401 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:43:09.401 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:43:09.401 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:43:09.401 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:43:09.401 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:43:14.409 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:43:14.409 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:43:14.410 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:43:14.410 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:43:14.410 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:43:14.410 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:43:14.415 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:43:14.416 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:43:14.416 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:43:14.416 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:43:14.416 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:43:14.418 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:43:14.419 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:43:14.419 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:43:14.419 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:43:14.419 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:43:14.420 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:43:14.420 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:43:14.420 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:43:14.420 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:43:14.421 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:43:14.421 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:43:14.421 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:43:14.421 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:43:14.421 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:43:14.421 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:43:14.421 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:43:14.421 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:43:14.422 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:43:14.424 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:43:14.424 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:43:14.424 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:43:14.424 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:43:14.424 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:43:14.424 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:43:14.424 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:43:14.424 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:43:14.424 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:43:14.426 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:43:14.426 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:43:14.426 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:43:14.426 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:43:14.426 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:43:14.426 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:43:14.427 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:43:14.427 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:43:14.427 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:43:14.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:43:14.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:43:14.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:43:14.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:43:14.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:43:14.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:43:14.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:43:14.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:43:14.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:43:14.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:43:14.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:43:14.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:43:14.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:43:14.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:43:14.432 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:43:14.909 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:43:14.956 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:43:14.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:43:14.957 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:43:14.958 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:43:14.979 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:43:14.979 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:43:14.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:43:14.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:43:14.986 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:43:14.986 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:43:14.986 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:43:14.986 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:43:15.001 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:43:15.005 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:43:15.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:43:15.015 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:43:15.015 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:43:15.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:43:15.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:43:15.381 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:43:15.429 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:43:15.429 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:43:15.430 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:43:15.430 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:43:15.852 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:43:16.323 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:43:16.431 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:43:16.431 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:43:16.431 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:43:16.431 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:43:16.796 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:43:17.269 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:43:17.431 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:43:17.432 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:43:17.432 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:43:17.432 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:43:17.741 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:43:18.215 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:43:18.432 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:43:18.432 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:43:18.432 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:43:18.432 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:43:18.687 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:43:19.160 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:43:19.434 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:43:19.434 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:43:19.434 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:43:19.434 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:43:19.633 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:43:20.105 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:43:20.577 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:43:21.048 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:43:21.522 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:43:21.995 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:43:22.466 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:43:22.938 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:43:23.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:43:23.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:43:23.023 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:43:23.023 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:43:23.042 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:43:23.042 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:43:23.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:43:23.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:43:23.044 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:43:23.044 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:43:23.044 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:43:23.044 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:43:23.074 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:43:23.079 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:43:23.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:43:23.088 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:43:23.088 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:43:23.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:43:23.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:43:23.408 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:43:23.879 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:43:24.353 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:43:24.825 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:43:25.297 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:43:25.768 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:43:26.242 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:43:26.714 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:43:27.186 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:43:27.657 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:43:28.131 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:43:28.603 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:43:29.076 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:43:29.549 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:43:30.022 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:43:30.494 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:43:30.965 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:43:31.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:43:31.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:43:31.096 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:43:31.096 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:43:31.107 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:43:31.107 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:43:31.107 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:43:31.107 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:43:31.111 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:43:31.112 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:43:31.112 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:43:31.112 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:43:31.112 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:43:31.112 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:43:31.112 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:43:31.112 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3604 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:43:31.113 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3604 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:43:31.113 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3604 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:43:31.113 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3604 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:43:31.113 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3604 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:43:31.113 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3604 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:43:36.118 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:43:36.119 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:43:36.119 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:43:36.119 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:43:36.119 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:43:36.119 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:43:36.128 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:43:36.129 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:43:36.129 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:43:36.130 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:43:36.130 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:43:36.133 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:43:36.134 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:43:36.134 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:43:36.134 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:43:36.134 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:43:36.134 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:43:36.134 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:43:36.134 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:43:36.135 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:43:36.138 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:43:36.138 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:43:36.138 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:43:36.138 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:43:36.138 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:43:36.138 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:43:36.139 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:43:36.139 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:43:36.139 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:43:36.142 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:43:36.142 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:43:36.142 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:43:36.142 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:43:36.142 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:43:36.142 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:43:36.142 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:43:36.142 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:43:36.142 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:43:36.147 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:43:36.147 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:43:36.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:43:36.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:43:36.147 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:43:36.147 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:43:36.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:43:36.147 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:43:36.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:43:36.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:43:36.147 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:43:36.147 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:43:36.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:43:36.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:43:36.147 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:43:36.147 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:43:36.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:43:36.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:43:36.148 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:43:36.148 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:43:36.148 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:43:36.148 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:43:36.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:43:36.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:43:36.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:43:36.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:43:36.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:43:36.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:43:36.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:43:36.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:43:36.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:43:36.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:43:36.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:43:36.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:43:36.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:43:36.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:43:36.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:43:36.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:43:36.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:43:36.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:43:36.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:43:36.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:43:36.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:43:36.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:43:36.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:43:36.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:43:36.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:43:36.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:43:36.153 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:43:36.631 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:43:36.676 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:43:36.679 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:43:36.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:43:36.681 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:43:36.708 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:43:36.708 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:43:36.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:43:36.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:43:36.713 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:43:36.713 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:43:36.713 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:43:36.713 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:43:36.722 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:43:36.724 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:43:36.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:43:36.737 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:43:36.737 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:43:36.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:43:36.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:43:37.103 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:43:37.150 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:43:37.151 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:43:37.151 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:43:37.152 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:43:37.575 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:43:38.046 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:43:38.151 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:43:38.152 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:43:38.152 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:43:38.152 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:43:38.519 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:43:38.991 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:43:39.152 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:43:39.153 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:43:39.153 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:43:39.153 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:43:39.464 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:43:39.934 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:43:40.154 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:43:40.154 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:43:40.154 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:43:40.154 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:43:40.405 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:43:40.879 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:43:41.156 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:43:41.156 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:43:41.156 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:43:41.156 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:43:41.352 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:43:41.824 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:43:42.297 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:43:42.770 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:43:43.242 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:43:43.713 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:43:44.183 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:43:44.655 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:43:44.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:43:44.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:43:44.743 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:43:44.743 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:43:44.761 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:43:44.761 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:43:44.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:43:44.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:43:44.763 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:43:44.763 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:43:44.763 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:43:44.763 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:43:44.791 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:43:44.795 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:43:44.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:43:44.806 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:43:44.807 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:43:44.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:43:44.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:43:45.127 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:43:45.601 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:43:46.073 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:43:46.546 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:43:47.019 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:43:47.492 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:43:47.962 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:43:48.433 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:43:48.904 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:43:49.374 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:43:49.845 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:43:50.318 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:43:50.788 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:43:51.257 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:43:51.728 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:43:52.202 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:43:52.674 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:43:52.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:43:52.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:43:52.812 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:43:52.812 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:43:52.828 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:43:52.828 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:43:52.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:43:52.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:43:52.830 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:43:52.830 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:43:52.830 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:43:52.830 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:43:52.859 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:43:52.861 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:43:52.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:43:52.871 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:43:52.871 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:43:52.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:43:52.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:43:53.147 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 01:43:53.618 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 01:43:54.090 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 01:43:54.563 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 01:43:55.035 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 01:43:55.505 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 01:43:55.976 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 01:43:56.448 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 01:43:56.921 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 01:43:57.394 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 01:43:57.866 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 01:43:58.339 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 01:43:58.812 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 01:43:59.284 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 01:43:59.755 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 01:44:00.226 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 01:44:00.697 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 01:44:00.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:44:00.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:44:00.877 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:44:00.877 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:44:00.893 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:44:00.893 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:44:00.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:44:00.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:44:00.895 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:44:00.895 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:44:00.895 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:44:00.895 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:44:00.930 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:44:00.936 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:44:00.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:44:00.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:44:00.945 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:44:00.945 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:44:00.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:44:00.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:44:01.167 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 01:44:01.638 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 01:44:02.111 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 01:44:02.584 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 01:44:03.057 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 01:44:03.530 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 01:44:04.003 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 01:44:04.476 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 01:44:04.949 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 01:44:05.421 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 01:44:05.894 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 01:44:06.364 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 01:44:06.835 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 01:44:07.309 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 01:44:07.781 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 01:44:08.254 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 01:44:08.727 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 01:44:08.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:44:08.950 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:44:08.951 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:44:08.951 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:44:08.960 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:44:08.960 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:44:08.960 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:44:08.960 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:44:08.962 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:44:08.963 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:44:08.963 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:44:08.963 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:44:08.963 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:44:08.963 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:44:08.963 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:44:13.967 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:44:13.968 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:44:13.968 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:44:13.968 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:44:13.968 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:44:13.968 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:44:13.977 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:44:13.978 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:44:13.979 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:44:13.979 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:44:13.979 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:44:13.985 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:44:13.985 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:44:13.985 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:44:13.985 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:44:13.985 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:44:13.985 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:44:13.986 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:44:13.986 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:44:13.986 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:44:13.989 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:44:13.990 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:44:13.990 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:44:13.990 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:44:13.990 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:44:13.990 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:44:13.990 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:44:13.990 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:44:13.990 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:44:13.994 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:44:13.994 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:44:13.994 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:44:13.994 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:44:13.994 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:44:13.995 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:44:13.995 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:44:13.995 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:44:13.995 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:44:13.999 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:44:13.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:44:13.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:44:13.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:44:13.999 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:44:13.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:44:13.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:44:13.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:44:13.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:44:13.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:44:13.999 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:44:13.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:44:13.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:44:13.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:44:13.999 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:44:13.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:44:14.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:44:14.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:44:14.000 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:44:14.000 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:44:14.000 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:44:14.000 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:44:14.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:44:14.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:44:14.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:44:14.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:44:14.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:44:14.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:44:14.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:44:14.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:44:14.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:44:14.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:44:14.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:44:14.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:44:14.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:44:14.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:44:14.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:44:14.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:44:14.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:44:14.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:44:14.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:44:14.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:44:14.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:44:14.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:44:14.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:44:14.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:44:14.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:44:14.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:44:14.005 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:44:14.482 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:44:14.531 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:44:14.532 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:44:14.534 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:44:14.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:44:14.556 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:44:14.556 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:44:14.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:44:14.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:44:14.561 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:44:14.561 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:44:14.562 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:44:14.562 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:44:14.574 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:44:14.577 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:44:14.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:44:14.585 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:44:14.585 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:44:14.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:44:14.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:44:14.953 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:44:15.003 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:44:15.004 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:44:15.004 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:44:15.005 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:44:15.425 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:44:15.896 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:44:16.005 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:44:16.005 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:44:16.005 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:44:16.005 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:44:16.367 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:44:16.840 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:44:17.006 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:44:17.007 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:44:17.007 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:44:17.007 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:44:17.313 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:44:17.785 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:44:18.007 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:44:18.008 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:44:18.008 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:44:18.008 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:44:18.256 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:44:18.729 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:44:19.008 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:44:19.008 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:44:19.009 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:44:19.009 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:44:19.201 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:44:19.674 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:44:20.145 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:44:20.618 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:44:21.090 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:44:21.563 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:44:22.034 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:44:22.504 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:44:22.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:44:22.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:44:22.590 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:44:22.590 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:44:22.608 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:44:22.608 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:44:22.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:44:22.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:44:22.610 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:44:22.610 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:44:22.610 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:44:22.610 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:44:22.641 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:44:22.646 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:44:22.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:44:22.654 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:44:22.654 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:44:22.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:44:22.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:44:22.975 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:44:23.449 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:44:23.921 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:44:24.393 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:44:24.864 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:44:25.335 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:44:25.806 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:44:26.277 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:44:26.750 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:44:27.222 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:44:27.694 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:44:28.166 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:44:28.639 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:44:29.111 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:44:29.583 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:44:30.054 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:44:30.525 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:44:30.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:44:30.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:44:30.660 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:44:30.661 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:44:30.671 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:44:30.671 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:44:30.671 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:44:30.672 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:44:30.675 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:44:30.676 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:44:30.676 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:44:30.676 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:44:30.676 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:44:30.676 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:44:30.676 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:44:30.677 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3604 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:44:30.677 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3604 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:44:30.677 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3604 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:44:30.677 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3604 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:44:30.677 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3604 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:44:30.677 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3604 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:44:30.677 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3604 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:44:30.677 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3605 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:44:30.677 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3605 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:44:30.677 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3605 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:44:30.678 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3605 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:44:35.679 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:44:35.679 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:44:35.679 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:44:35.679 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:44:35.679 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:44:35.679 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:44:35.687 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:44:35.688 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:44:35.688 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:44:35.689 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:44:35.689 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:44:35.692 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:44:35.692 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:44:35.692 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:44:35.693 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:44:35.693 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:44:35.693 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:44:35.694 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:44:35.694 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:44:35.694 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:44:35.695 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:44:35.695 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:44:35.695 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:44:35.695 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:44:35.696 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:44:35.696 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:44:35.696 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:44:35.696 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:44:35.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:44:35.698 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:44:35.698 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:44:35.698 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:44:35.698 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:44:35.698 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:44:35.698 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:44:35.698 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:44:35.698 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:44:35.699 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:44:35.701 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:44:35.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:44:35.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:44:35.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:44:35.701 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:44:35.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:44:35.702 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:44:35.702 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:44:35.702 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:44:35.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:44:35.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:44:35.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:44:35.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:44:35.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:44:35.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:44:35.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:44:35.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:44:35.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:44:35.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:44:35.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:44:35.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:44:35.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:44:35.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:44:35.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:44:35.707 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:44:36.185 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:44:36.223 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:44:36.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:44:36.225 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:44:36.226 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:44:36.238 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:44:36.239 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:44:36.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:44:36.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:44:36.245 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:44:36.245 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:44:36.245 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:44:36.245 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:44:36.277 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:44:36.281 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:44:36.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:44:36.298 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:44:36.299 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:44:36.299 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:44:36.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:44:36.657 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:44:36.704 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:44:36.704 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:44:36.705 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:44:36.705 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:44:37.128 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:44:37.601 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:44:37.704 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:44:37.705 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:44:37.705 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:44:37.705 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:44:38.074 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:44:38.546 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:44:38.706 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:44:38.706 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:44:38.706 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:44:38.706 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:44:39.020 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:44:39.492 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:44:39.707 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:44:39.707 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:44:39.707 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:44:39.707 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:44:39.964 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:44:40.435 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:44:40.708 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:44:40.709 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:44:40.709 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:44:40.709 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:44:40.908 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:44:41.381 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:44:41.852 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:44:42.324 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:44:42.797 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:44:43.269 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:44:43.741 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:44:44.213 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:44:44.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:44:44.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:44:44.304 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:44:44.304 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:44:44.322 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:44:44.322 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:44:44.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:44:44.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:44:44.324 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:44:44.325 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:44:44.325 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:44:44.325 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:44:44.349 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:44:44.354 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:44:44.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:44:44.362 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:44:44.362 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:44:44.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:44:44.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:44:44.685 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:44:45.158 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:44:45.631 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:44:46.104 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:44:46.577 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:44:47.049 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:44:47.522 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:44:47.995 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:44:48.467 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:44:48.938 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:44:49.411 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:44:49.884 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:44:50.356 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:44:50.826 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:44:51.297 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:44:51.771 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:44:52.243 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:44:52.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:44:52.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:44:52.368 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:44:52.368 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:44:52.387 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:44:52.387 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:44:52.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:44:52.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:44:52.390 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:44:52.390 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:44:52.390 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:44:52.390 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:44:52.428 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:44:52.433 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:44:52.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:44:52.446 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:44:52.446 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:44:52.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:44:52.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:44:52.715 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 01:44:53.186 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 01:44:53.660 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 01:44:54.132 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 01:44:54.604 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 01:44:55.078 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 01:44:55.550 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 01:44:56.022 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 01:44:56.496 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 01:44:56.968 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 01:44:57.440 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 01:44:57.914 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 01:44:58.386 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 01:44:58.858 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 01:44:59.329 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 01:44:59.800 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 01:45:00.274 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 01:45:00.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:45:00.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:00.451 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:45:00.452 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:45:00.470 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:45:00.470 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:45:00.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:45:00.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:00.472 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:45:00.472 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:45:00.472 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:45:00.472 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:45:00.505 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:45:00.509 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:45:00.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:45:00.519 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:45:00.519 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:45:00.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:00.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:00.745 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 01:45:01.217 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 01:45:01.688 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 01:45:02.162 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 01:45:02.634 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 01:45:03.106 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 01:45:03.577 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 01:45:04.051 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 01:45:04.523 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 01:45:04.995 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 01:45:05.466 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 01:45:05.940 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 01:45:06.412 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 01:45:06.884 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 01:45:07.355 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 01:45:07.826 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 01:45:08.298 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 01:45:08.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:45:08.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:08.525 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:45:08.525 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:45:08.531 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:45:08.531 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:45:08.531 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:45:08.531 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:45:08.532 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:45:08.532 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:45:08.532 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:45:08.532 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:45:08.532 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:45:08.532 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:45:08.532 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:45:13.539 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:45:13.539 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:45:13.539 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:45:13.539 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:45:13.539 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:45:13.539 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:45:13.547 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:45:13.549 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:45:13.549 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:45:13.549 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:45:13.549 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:45:13.553 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:45:13.553 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:45:13.553 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:45:13.554 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:45:13.554 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:45:13.554 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:45:13.555 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:45:13.555 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:45:13.555 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:45:13.556 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:45:13.557 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:45:13.557 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:45:13.557 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:45:13.557 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:45:13.557 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:45:13.558 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:45:13.558 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:45:13.558 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:45:13.559 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:45:13.559 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:45:13.559 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:45:13.559 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:45:13.560 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:45:13.560 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:45:13.560 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:45:13.560 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:45:13.560 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:45:13.563 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:45:13.563 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:45:13.563 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:45:13.563 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:45:13.563 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:45:13.563 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:45:13.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:45:13.563 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:45:13.563 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:45:13.563 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:45:13.563 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:45:13.563 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:45:13.563 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:45:13.563 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:45:13.563 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:45:13.563 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:45:13.563 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:45:13.563 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:45:13.563 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:45:13.563 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:45:13.563 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:45:13.563 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:45:13.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:45:13.568 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:45:14.041 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:45:14.093 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:45:14.095 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:45:14.097 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:45:14.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:45:14.123 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:45:14.123 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:45:14.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:45:14.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:14.130 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:45:14.130 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:45:14.130 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:45:14.130 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:45:14.181 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:45:14.185 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:45:14.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:45:14.201 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:45:14.201 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:45:14.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:14.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:14.513 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:45:14.566 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:45:14.567 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:45:14.567 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:45:14.567 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:45:14.984 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:45:15.457 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:45:15.568 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:45:15.568 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:45:15.568 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:45:15.568 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:45:15.930 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:45:16.401 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:45:16.569 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:45:16.570 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:45:16.570 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:45:16.570 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:45:16.873 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:45:17.346 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:45:17.571 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:45:17.571 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:45:17.571 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:45:17.571 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:45:17.818 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:45:18.290 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:45:18.572 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:45:18.572 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:45:18.572 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:45:18.572 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:45:18.761 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:45:19.235 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:45:19.707 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:45:20.179 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:45:20.650 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:45:21.121 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:45:21.594 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:45:22.067 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:45:22.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:45:22.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:22.207 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:45:22.207 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:45:22.226 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:45:22.226 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:45:22.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:45:22.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:22.227 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:45:22.227 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:45:22.227 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:45:22.227 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:45:22.250 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:45:22.253 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:45:22.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:45:22.263 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:45:22.263 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:45:22.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:22.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:22.538 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:45:23.010 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:45:23.480 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:45:23.954 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:45:24.426 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:45:24.898 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:45:25.369 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:45:25.843 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:45:26.316 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:45:26.787 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:45:27.260 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:45:27.732 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:45:28.204 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:45:28.675 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:45:29.148 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:45:29.620 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:45:30.092 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:45:30.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:45:30.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:30.268 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:45:30.268 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:45:30.274 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:45:30.274 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:45:30.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:45:30.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:30.276 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:45:30.276 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:45:30.276 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:45:30.276 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:45:30.326 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:45:30.332 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:45:30.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:45:30.342 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:45:30.342 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:45:30.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:30.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:30.563 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 01:45:31.036 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 01:45:31.509 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 01:45:31.981 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 01:45:32.452 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 01:45:32.924 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 01:45:33.398 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 01:45:33.869 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 01:45:34.340 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 01:45:34.814 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 01:45:35.286 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 01:45:35.758 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 01:45:36.229 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 01:45:36.702 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 01:45:37.175 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 01:45:37.646 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 01:45:38.118 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 01:45:38.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:45:38.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:38.347 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:45:38.347 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:45:38.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:45:38.366 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:45:38.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:45:38.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:38.368 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:45:38.368 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:45:38.368 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:45:38.368 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:45:38.398 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:45:38.402 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:45:38.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:45:38.409 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:45:38.409 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:45:38.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:38.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:38.589 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 01:45:39.062 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 01:45:39.535 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 01:45:40.006 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 01:45:40.478 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 01:45:40.948 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 01:45:41.419 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 01:45:41.893 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 01:45:42.365 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 01:45:42.837 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 01:45:43.308 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 01:45:43.781 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 01:45:44.254 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 01:45:44.726 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 01:45:45.197 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 01:45:45.668 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 01:45:46.141 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 01:45:46.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:45:46.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:46.416 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:45:46.416 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:45:46.433 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:45:46.433 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:45:46.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:45:46.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:46.435 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:45:46.435 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:45:46.435 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:45:46.435 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:45:46.464 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:45:46.469 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:45:46.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:45:46.477 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:45:46.477 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:45:46.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:46.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:46.612 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 01:45:47.084 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 01:45:47.556 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 01:45:48.029 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 01:45:48.501 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-06 01:45:48.973 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-06 01:45:49.444 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-06 01:45:49.918 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-06 01:45:50.390 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-06 01:45:50.862 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-06 01:45:51.333 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-06 01:45:51.806 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-06 01:45:52.279 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-06 01:45:52.751 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-06 01:45:53.222 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-06 01:45:53.695 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-06 01:45:54.167 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-06 01:45:54.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:45:54.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:54.483 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:45:54.483 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:45:54.502 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:45:54.502 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:45:54.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:45:54.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:54.504 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:45:54.504 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:45:54.504 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:45:54.504 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:45:54.541 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:45:54.544 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:45:54.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:45:54.555 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:45:54.556 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:45:54.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:54.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:45:54.639 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-06 01:45:55.111 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-06 01:45:55.584 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-06 01:45:56.056 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-06 01:45:56.528 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-06 01:45:56.999 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-06 01:45:57.472 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-06 01:45:57.945 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-06 01:45:58.417 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-06 01:45:58.888 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-06 01:45:59.361 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-06 01:45:59.834 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-06 01:46:00.306 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-06 01:46:00.777 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-06 01:46:01.250 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-06 01:46:01.722 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-06 01:46:02.195 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-06 01:46:02.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:46:02.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:46:02.561 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:46:02.562 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:46:02.581 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:46:02.581 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:46:02.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:46:02.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:46:02.584 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:46:02.584 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:46:02.584 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:46:02.584 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:46:02.613 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:46:02.617 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:46:02.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:46:02.635 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:46:02.636 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:46:02.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:46:02.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:46:02.666 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-06 01:46:03.139 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-06 01:46:03.611 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-06 01:46:04.083 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-06 01:46:04.554 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-06 01:46:05.025 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-06 01:46:05.496 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-06 01:46:05.966 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-06 01:46:06.437 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-06 01:46:06.908 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-06 01:46:07.382 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-06 01:46:07.853 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-06 01:46:08.325 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-06 01:46:08.796 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-06 01:46:09.267 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-06 01:46:09.738 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-06 01:46:10.209 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-06 01:46:10.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:46:10.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:46:10.642 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:46:10.642 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:46:10.660 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:46:10.661 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:46:10.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:46:10.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:46:10.663 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:46:10.663 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:46:10.663 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:46:10.663 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:46:10.675 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:46:10.676 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:46:10.679 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-06 01:46:10.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:46:10.682 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:46:10.683 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:46:10.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:46:10.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:46:11.150 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-06 01:46:11.623 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-06 01:46:12.096 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-06 01:46:12.568 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-06 01:46:13.039 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-06 01:46:13.512 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-06 01:46:13.985 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-06 01:46:14.456 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-06 01:46:14.928 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-06 01:46:15.401 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-06 01:46:15.874 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-06 01:46:16.346 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-06 01:46:16.816 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-06 01:46:17.287 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-06 01:46:17.758 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-06 01:46:18.229 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-06 01:46:18.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:46:18.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:46:18.688 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:46:18.688 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:46:18.701 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:46:18.702 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:46:18.702 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:46:18.702 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-06 01:46:18.702 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:46:18.703 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:46:18.703 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:46:18.703 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:46:18.703 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:46:18.703 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:46:18.703 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:46:18.703 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:46:18.703 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=14079 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:46:18.703 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=14079 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:46:18.703 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=14079 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:46:18.703 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=14079 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:46:18.703 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=14079 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:46:18.703 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=14079 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:46:23.712 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:46:23.712 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:46:23.712 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:46:23.712 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:46:23.712 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:46:23.713 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:46:23.719 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:46:23.719 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:46:23.719 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:46:23.720 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:46:23.720 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:46:23.722 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:46:23.722 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:46:23.722 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:46:23.722 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:46:23.722 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:46:23.722 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:46:23.723 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:46:23.723 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:46:23.723 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:46:23.724 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:46:23.724 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:46:23.724 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:46:23.724 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:46:23.724 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:46:23.724 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:46:23.724 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:46:23.724 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:46:23.724 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:46:23.725 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:46:23.726 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:46:23.726 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:46:23.726 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:46:23.726 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:46:23.726 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:46:23.726 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:46:23.726 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:46:23.726 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:46:23.728 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:46:23.728 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:46:23.728 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:46:23.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:46:23.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:46:23.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:46:23.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:46:23.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:46:23.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:46:23.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:46:23.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:46:23.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:46:23.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:46:23.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:46:23.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:46:23.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:46:23.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:46:23.733 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:46:24.210 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:46:24.251 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:46:24.253 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:46:24.254 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:46:24.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:46:24.266 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:46:24.266 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:46:24.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:46:24.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:46:24.270 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:46:24.270 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:46:24.270 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:46:24.270 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:46:24.303 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:46:24.307 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:46:24.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:46:24.316 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:46:24.316 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:46:24.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:46:24.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:46:24.682 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:46:24.731 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:46:24.731 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:46:24.731 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:46:24.731 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:46:25.154 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:46:25.624 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:46:25.732 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:46:25.732 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:46:25.733 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:46:25.733 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:46:26.095 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:46:26.566 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:46:26.734 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:46:26.734 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:46:26.734 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:46:26.734 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:46:27.037 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:46:27.508 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:46:27.735 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:46:27.735 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:46:27.735 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:46:27.735 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:46:27.981 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:46:28.453 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:46:28.736 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:46:28.736 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:46:28.736 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:46:28.737 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:46:28.926 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:46:29.399 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:46:29.871 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:46:30.344 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:46:30.817 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:46:31.290 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:46:31.762 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:46:32.233 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:46:32.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:46:32.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:46:32.322 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:46:32.322 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:46:32.338 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:46:32.338 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:46:32.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:46:32.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:46:32.340 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:46:32.340 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:46:32.340 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:46:32.340 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:46:32.369 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:46:32.373 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:46:32.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:46:32.384 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:46:32.384 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:46:32.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:46:32.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:46:32.704 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:46:33.177 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:46:33.650 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:46:34.122 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:46:34.593 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:46:35.063 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:46:35.534 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:46:36.005 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:46:36.476 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:46:36.947 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:46:37.420 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:46:37.893 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:46:38.365 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:46:38.836 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:46:39.309 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:46:39.781 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:46:40.253 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:46:40.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:46:40.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:46:40.389 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:46:40.390 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:46:40.401 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:46:40.401 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:46:40.401 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:46:40.402 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:46:40.403 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:46:40.403 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:46:40.403 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:46:40.403 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:46:40.403 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:46:40.403 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:46:40.403 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:46:45.409 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:46:45.409 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:46:45.409 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:46:45.409 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:46:45.409 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:46:45.409 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:46:45.418 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:46:45.420 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:46:45.420 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:46:45.421 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:46:45.421 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:46:45.427 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:46:45.427 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:46:45.428 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:46:45.428 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:46:45.428 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:46:45.429 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:46:45.429 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:46:45.429 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:46:45.430 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:46:45.432 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:46:45.432 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:46:45.433 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:46:45.433 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:46:45.433 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:46:45.433 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:46:45.433 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:46:45.433 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:46:45.433 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:46:45.436 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:46:45.436 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:46:45.437 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:46:45.437 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:46:45.437 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:46:45.437 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:46:45.437 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:46:45.437 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:46:45.437 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:46:45.441 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:46:45.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:46:45.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:46:45.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:46:45.441 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:46:45.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:46:45.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:46:45.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:46:45.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:46:45.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:46:45.442 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:46:45.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:46:45.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:46:45.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:46:45.442 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:46:45.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:46:45.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:46:45.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:46:45.442 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:46:45.442 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:46:45.442 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:46:45.442 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:46:45.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:46:45.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:46:45.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:46:45.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:46:45.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:46:45.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:46:45.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:46:45.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:46:45.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:46:45.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:46:45.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:46:45.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:46:45.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:46:45.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:46:45.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:46:45.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:46:45.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:46:45.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:46:45.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:46:45.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:46:45.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:46:45.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:46:45.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:46:45.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:46:45.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:46:45.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:46:45.447 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:46:45.925 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:46:45.964 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:46:45.965 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:46:45.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:46:45.967 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:46:45.985 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:46:45.986 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:46:45.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:46:45.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:46:45.991 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:46:45.992 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:46:45.992 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:46:45.992 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:46:46.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:46:46.031 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:46:46.032 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:46:46.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:46:46.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:46:46.397 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:46:46.445 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:46:46.445 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:46:46.446 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:46:46.446 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:46:46.868 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:46:47.342 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:46:47.447 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:46:47.447 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:46:47.447 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:46:47.447 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:46:47.814 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:46:48.287 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:46:48.447 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:46:48.448 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:46:48.448 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:46:48.448 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:46:48.760 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:46:49.233 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:46:49.449 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:46:49.449 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:46:49.450 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:46:49.450 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:46:49.705 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:46:50.176 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:46:50.451 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:46:50.451 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:46:50.451 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:46:50.451 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:46:50.649 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:46:51.122 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:46:51.594 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:46:52.068 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:46:52.541 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:46:53.013 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:46:53.484 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:46:53.957 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:46:54.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:46:54.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:46:54.040 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:46:54.040 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:46:54.057 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:46:54.057 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:46:54.057 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:46:54.057 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:46:54.060 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:46:54.060 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:46:54.060 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:46:54.060 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:46:54.060 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:46:54.060 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:46:54.061 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:46:54.061 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1861 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:46:54.061 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1861 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:46:54.061 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1861 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:46:54.061 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1861 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:46:54.061 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1861 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:46:54.061 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1861 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:46:59.064 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:46:59.064 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:46:59.064 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:46:59.064 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:46:59.064 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:46:59.064 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:46:59.072 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:46:59.073 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:46:59.073 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:46:59.074 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:46:59.074 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:46:59.077 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:46:59.077 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:46:59.077 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:46:59.077 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:46:59.078 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:46:59.078 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:46:59.078 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:46:59.078 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:46:59.078 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:46:59.080 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:46:59.080 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:46:59.080 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:46:59.080 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:46:59.081 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:46:59.081 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:46:59.081 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:46:59.081 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:46:59.081 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:46:59.082 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:46:59.082 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:46:59.082 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:46:59.082 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:46:59.082 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:46:59.082 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:46:59.083 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:46:59.083 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:46:59.083 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:46:59.085 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:46:59.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:46:59.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:46:59.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:46:59.085 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:46:59.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:46:59.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:46:59.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:46:59.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:46:59.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:46:59.085 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:46:59.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:46:59.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:46:59.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:46:59.085 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:46:59.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:46:59.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:46:59.086 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:46:59.086 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:46:59.086 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:46:59.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:46:59.090 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:46:59.567 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:46:59.607 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:46:59.608 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:46:59.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:46:59.609 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:46:59.626 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:46:59.626 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:46:59.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:46:59.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:46:59.632 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:46:59.632 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:46:59.632 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:46:59.632 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:46:59.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:46:59.671 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:46:59.671 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:46:59.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:46:59.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:47:00.039 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:47:00.088 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:00.088 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:00.088 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:00.088 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:00.511 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:47:00.984 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:47:01.089 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:01.089 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:01.089 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:01.090 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:01.456 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:47:01.928 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:47:02.090 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:02.090 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:02.091 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:02.091 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:02.400 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:47:02.873 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:47:03.091 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:03.091 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:03.091 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:03.092 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:03.345 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:47:03.818 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:47:04.091 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:04.092 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:04.092 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:04.092 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:04.291 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:47:04.764 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:47:05.235 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:47:05.707 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:47:06.180 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:47:06.653 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:47:07.125 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:47:07.596 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:47:07.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:47:07.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:47:07.680 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:47:07.680 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:47:07.697 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:07.698 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:07.698 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:07.698 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:07.701 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:47:07.702 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:47:07.702 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:47:07.702 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:47:07.702 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:47:07.702 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:47:07.702 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:47:07.703 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1861 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:47:07.703 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1861 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:47:07.703 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1861 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:47:07.703 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1861 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:47:07.703 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1861 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:47:07.703 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1861 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:47:12.705 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:47:12.705 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:47:12.705 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:47:12.705 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:47:12.705 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:47:12.705 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:47:12.713 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:47:12.714 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:47:12.714 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:47:12.715 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:47:12.715 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:47:12.719 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:47:12.719 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:47:12.719 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:47:12.720 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:47:12.720 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:47:12.720 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:47:12.721 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:47:12.721 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:47:12.721 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:12.723 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:47:12.723 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:47:12.723 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:47:12.724 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:47:12.724 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:47:12.724 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:47:12.724 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:47:12.724 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:47:12.725 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:12.726 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:47:12.726 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:47:12.726 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:47:12.726 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:47:12.727 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:47:12.727 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:47:12.727 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:47:12.727 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:47:12.727 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:12.730 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:47:12.730 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:47:12.730 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:47:12.730 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:47:12.730 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:47:12.730 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:47:12.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:47:12.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:12.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:47:12.731 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:47:12.731 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:47:12.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:12.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:12.731 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:12.731 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:12.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:12.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:12.731 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:12.731 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:47:12.731 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:47:12.731 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:47:12.731 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:47:12.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:12.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:12.731 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:12.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:47:12.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:12.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:12.731 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:12.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:47:12.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:12.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:12.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:12.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:47:12.732 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:12.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:12.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:12.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:47:12.732 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:12.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:12.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:12.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:47:12.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:12.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:12.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:47:12.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:47:12.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:47:12.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:47:12.736 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:47:13.215 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:47:13.245 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:47:13.246 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:47:13.246 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:47:13.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:47:13.262 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:47:13.262 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:47:13.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:47:13.267 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:47:13.267 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:47:13.268 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:47:13.268 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:47:13.268 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:47:13.687 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:47:13.733 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:13.734 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:13.734 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:13.734 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:14.158 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:47:14.629 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:47:14.734 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:14.734 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:14.735 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:14.735 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:15.100 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:47:15.573 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:47:15.734 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:15.735 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:15.735 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:15.736 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:16.045 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:47:16.517 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:47:16.736 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:16.736 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:16.737 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:16.737 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:16.988 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:47:17.461 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:47:17.737 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:17.738 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:17.738 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:17.738 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:17.934 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:47:18.406 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:47:18.877 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:47:19.350 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:47:19.822 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:47:19.950 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:47:19.950 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:47:19.956 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:19.956 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:19.956 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:19.956 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:19.956 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:47:19.957 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:47:19.957 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:47:19.957 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:47:19.957 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:47:19.957 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:47:19.957 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:47:19.957 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1561 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:47:19.957 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1561 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:47:19.957 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1561 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:47:19.957 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1561 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:47:19.957 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1561 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:47:19.957 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1561 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:47:24.964 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:47:24.964 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:47:24.964 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:47:24.964 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:47:24.964 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:47:24.964 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:47:24.972 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:47:24.972 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:47:24.972 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:47:24.973 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:47:24.973 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:47:24.975 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:47:24.975 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:47:24.975 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:47:24.975 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:47:24.976 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:47:24.976 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:47:24.976 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:47:24.976 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:47:24.976 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:24.978 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:47:24.978 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:47:24.978 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:47:24.978 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:47:24.978 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:47:24.979 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:47:24.979 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:47:24.979 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:47:24.979 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:24.981 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:47:24.981 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:47:24.981 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:47:24.981 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:47:24.981 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:47:24.981 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:47:24.981 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:47:24.981 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:47:24.981 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:24.984 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:47:24.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:47:24.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:47:24.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:47:24.984 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:47:24.985 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:47:24.985 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:47:24.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:47:24.985 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:24.985 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:24.985 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:47:24.985 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:47:24.985 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:24.985 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:24.985 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:24.985 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:24.985 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:47:24.985 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:47:24.985 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:47:24.985 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:47:24.985 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:24.985 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:24.985 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:24.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:47:24.986 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:24.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:47:24.986 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:24.986 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:24.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:47:24.986 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:24.986 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:24.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:47:24.986 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:24.986 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:24.986 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:24.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:47:24.986 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:24.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:47:24.986 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:24.986 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:24.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:47:24.986 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:24.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:47:24.986 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:24.986 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:24.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:47:24.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:24.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:24.990 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:47:25.467 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:47:25.509 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:47:25.510 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:47:25.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:47:25.512 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:47:25.528 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:47:25.529 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:47:25.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:47:25.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:47:25.539 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:47:25.539 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:47:25.539 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:47:25.539 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:47:25.939 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:47:25.988 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:25.989 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:25.989 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:25.989 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:26.411 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:47:26.884 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:47:26.990 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:26.990 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:26.990 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:26.991 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:27.356 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:47:27.828 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:47:27.991 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:27.992 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:27.992 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:27.992 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:28.299 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:47:28.773 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:47:28.993 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:28.993 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:28.993 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:28.993 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:29.245 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:47:29.717 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:47:29.993 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:29.994 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:29.994 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:29.994 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:30.188 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:47:30.216 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:30.217 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:30.217 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:30.217 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:30.220 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:47:30.220 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:47:30.220 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:47:30.220 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:47:30.220 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:47:30.220 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:47:30.221 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1131 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:47:30.221 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1131 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:47:30.221 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1131 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:47:30.221 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1131 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:47:30.221 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1131 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:47:30.221 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1131 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:47:30.221 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1131 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:47:30.667 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:47:31.147 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:47:31.628 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:47:32.106 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:47:32.585 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:47:33.066 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:47:33.546 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:47:34.026 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:47:34.507 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:47:34.989 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:47:35.222 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:47:35.222 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:47:35.222 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:47:35.224 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:47:35.224 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:47:35.224 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:47:35.224 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:47:35.224 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:47:35.224 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:47:35.234 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:47:35.237 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:47:35.237 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:47:35.237 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:47:35.237 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:47:35.245 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:47:35.245 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:47:35.245 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:47:35.245 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:47:35.246 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:47:35.246 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:47:35.246 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:47:35.246 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:47:35.246 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:35.252 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:47:35.252 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:47:35.252 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:47:35.252 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:47:35.252 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:47:35.252 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:47:35.252 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:47:35.252 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:47:35.252 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:35.258 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:47:35.258 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:47:35.258 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:47:35.258 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:47:35.258 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:47:35.258 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:47:35.258 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:47:35.258 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:47:35.259 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:35.260 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:47:35.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:47:35.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:47:35.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:47:35.260 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:47:35.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:47:35.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:47:35.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:35.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:47:35.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:47:35.260 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:47:35.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:35.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:35.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:35.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:35.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:35.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:35.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:35.261 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:47:35.261 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:47:35.261 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:47:35.261 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:47:35.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:35.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:35.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:35.261 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:47:35.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:35.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:35.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:35.261 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:47:35.261 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:47:35.261 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:47:35.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:35.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:35.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:40.268 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:47:40.268 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:47:40.268 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:47:40.268 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:47:40.268 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:47:40.268 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:47:40.276 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:47:40.277 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:47:40.277 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:47:40.277 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:47:40.277 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:47:40.279 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:47:40.279 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:47:40.280 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:47:40.280 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:47:40.280 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:47:40.280 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:47:40.281 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:47:40.281 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:47:40.281 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:40.282 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:47:40.282 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:47:40.282 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:47:40.282 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:47:40.282 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:47:40.282 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:47:40.282 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:47:40.282 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:47:40.282 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:40.284 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:47:40.284 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:47:40.284 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:47:40.284 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:47:40.284 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:47:40.284 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:47:40.284 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:47:40.284 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:47:40.285 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:40.287 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:47:40.287 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:47:40.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:47:40.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:47:40.287 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:47:40.287 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:47:40.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:47:40.287 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:40.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:47:40.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:47:40.287 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:47:40.287 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:40.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:40.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:40.287 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:40.287 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:40.287 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:47:40.287 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:47:40.287 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:47:40.287 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:47:40.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:40.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:40.287 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:47:40.288 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:47:40.292 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:47:40.771 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:47:40.814 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:47:40.816 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:47:40.818 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:47:40.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:47:40.838 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:47:40.838 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:47:40.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:47:40.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:47:40.848 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:47:40.849 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:47:40.849 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:47:40.849 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:47:41.243 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:47:41.289 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:41.290 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:41.290 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:41.290 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:41.714 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:47:42.185 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:47:42.290 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:42.291 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:42.291 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:42.291 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:42.659 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:47:43.131 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:47:43.292 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:43.292 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:43.292 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:43.292 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:43.602 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:47:44.074 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:47:44.293 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:44.293 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:44.293 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:44.294 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:44.547 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:47:45.019 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:47:45.295 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:45.295 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:47:45.295 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:47:45.295 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:47:45.491 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:47:45.962 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:47:46.436 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:47:46.511 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:46.908 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:47:47.380 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:47:47.512 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:47.851 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:47:48.324 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:47:48.514 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:48.797 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:47:49.269 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:47:49.515 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:49.740 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:47:50.213 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:47:50.516 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:50.517 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:47:50.686 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:47:51.157 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:47:51.633 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:47:52.103 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:47:52.567 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:47:53.030 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:47:53.493 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:47:53.957 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:47:54.431 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:47:54.516 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:47:54.902 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:47:55.374 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:47:55.516 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:55.844 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:47:56.318 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:47:56.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:56.790 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:47:57.262 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 01:47:57.518 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:57.733 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 01:47:58.206 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 01:47:58.520 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:58.678 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 01:47:59.150 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 01:47:59.521 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:47:59.622 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 01:48:00.095 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 01:48:00.567 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 01:48:01.039 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 01:48:01.512 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 01:48:01.636 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:48:01.637 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:48:01.643 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:48:01.643 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:48:01.643 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:48:01.643 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:48:01.643 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:48:01.643 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:48:01.643 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:48:01.643 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:48:01.643 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:48:01.643 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:48:01.644 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:48:06.652 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:48:06.652 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:48:06.652 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:48:06.652 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:48:06.652 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:48:06.652 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:48:06.665 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:48:06.666 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:48:06.666 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:48:06.666 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:48:06.666 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:48:06.668 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:48:06.668 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:48:06.669 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:48:06.669 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:48:06.669 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:48:06.669 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:48:06.669 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:48:06.669 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:48:06.670 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:48:06.670 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:48:06.671 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:48:06.671 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:48:06.671 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:48:06.671 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:48:06.671 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:48:06.671 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:48:06.671 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:48:06.671 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:48:06.672 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:48:06.672 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:48:06.672 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:48:06.672 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:48:06.672 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:48:06.672 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:48:06.672 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:48:06.672 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:48:06.673 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:48:06.674 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:48:06.674 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:48:06.674 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:48:06.674 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:48:06.674 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:48:06.674 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:48:06.674 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:48:06.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:48:06.674 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:48:06.674 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:48:06.674 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:48:06.675 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:48:06.675 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:48:06.675 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:48:06.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:48:06.679 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:48:07.159 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:48:07.199 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:48:07.201 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:48:07.203 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:48:07.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:48:07.228 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:48:07.228 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:48:07.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:48:07.233 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:48:07.233 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:48:07.233 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:48:07.234 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:48:07.234 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:48:07.251 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:48:07.255 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:48:07.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 01:48:07.264 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:48:07.264 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:48:07.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:48:07.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:48:07.631 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:48:07.677 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:48:07.677 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:48:07.678 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:48:07.678 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:48:08.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 01:48:08.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:48:08.066 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:48:08.066 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:48:08.075 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:48:08.076 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:48:08.076 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:48:08.076 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:48:08.080 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:48:08.080 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:48:08.080 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:48:08.080 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:48:08.080 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:48:08.080 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:48:08.080 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:48:08.081 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=303 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:48:08.081 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=303 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:48:08.081 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=303 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:48:08.081 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=303 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:48:08.081 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=303 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:48:08.081 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=303 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:48:08.081 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=303 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:48:13.083 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:48:13.083 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:48:13.083 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:48:13.083 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:48:13.083 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:48:13.083 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:48:13.091 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:48:13.093 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:48:13.093 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:48:13.093 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:48:13.093 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:48:13.096 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:48:13.096 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:48:13.097 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:48:13.097 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:48:13.097 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:48:13.098 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:48:13.098 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:48:13.098 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:48:13.098 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:48:13.099 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:48:13.100 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:48:13.100 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:48:13.100 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:48:13.100 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:48:13.100 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:48:13.100 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:48:13.100 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:48:13.100 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:48:13.102 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:48:13.102 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:48:13.102 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:48:13.102 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:48:13.103 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:48:13.103 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:48:13.103 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:48:13.103 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:48:13.103 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:48:13.106 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:48:13.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:48:13.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:48:13.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:48:13.106 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:48:13.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:48:13.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:48:13.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:48:13.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:48:13.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:48:13.106 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:48:13.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:48:13.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:48:13.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:48:13.106 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:48:13.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:48:13.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:48:13.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:48:13.106 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:48:13.106 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:48:13.106 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:48:13.106 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:48:13.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:48:13.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:48:13.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:48:13.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:48:13.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:48:13.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:48:13.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:48:13.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:48:13.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:48:13.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:48:13.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:48:13.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:48:13.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:48:13.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:48:13.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:48:13.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:48:13.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:48:13.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:48:13.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:48:13.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:48:13.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:48:13.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:48:13.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:48:13.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:48:13.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:48:13.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:48:13.111 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:48:13.588 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:48:13.635 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:48:13.638 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:48:13.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:48:13.640 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:48:13.667 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:48:13.667 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:48:13.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:48:13.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:48:13.675 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:48:13.675 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:48:13.676 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:48:13.676 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:48:13.681 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:48:13.684 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:48:13.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 01:48:13.691 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:48:13.691 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:48:13.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:48:13.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:48:14.054 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:48:14.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:48:14.109 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:48:14.109 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:48:14.109 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:48:14.483 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 01:48:14.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:48:14.487 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:48:14.487 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:48:14.496 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:48:14.496 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:48:14.496 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:48:14.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:48:14.497 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:48:14.497 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:48:14.497 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:48:14.497 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:48:14.497 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:48:14.497 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:48:14.497 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:48:19.502 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:48:19.503 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:48:19.503 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:48:19.503 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:48:19.503 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:48:19.503 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:48:19.511 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:48:19.512 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:48:19.512 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:48:19.512 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:48:19.512 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:48:19.515 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:48:19.515 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:48:19.515 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:48:19.515 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:48:19.516 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:48:19.516 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:48:19.516 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:48:19.516 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:48:19.516 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:48:19.517 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:48:19.517 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:48:19.518 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:48:19.518 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:48:19.518 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:48:19.518 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:48:19.518 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:48:19.518 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:48:19.518 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:48:19.520 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:48:19.520 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:48:19.520 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:48:19.520 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:48:19.520 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:48:19.520 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:48:19.520 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:48:19.520 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:48:19.520 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:48:19.522 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:48:19.522 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:48:19.522 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:48:19.522 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:48:19.522 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:48:19.522 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:48:19.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:48:19.522 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:48:19.523 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:48:19.523 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:48:19.523 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:48:19.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:48:19.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:48:19.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:48:19.527 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:48:20.004 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:48:20.051 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:48:20.053 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:48:20.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:48:20.056 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:48:20.081 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:48:20.081 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:48:20.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:48:20.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:48:20.085 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:48:20.085 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:48:20.085 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:48:20.085 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:48:20.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:48:20.107 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:48:20.107 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:48:20.108 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:48:20.108 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:48:20.476 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:48:20.526 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:48:20.526 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:48:20.526 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:48:20.526 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:48:20.948 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:48:21.421 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:48:21.527 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:48:21.528 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:48:21.528 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:48:21.528 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:48:21.894 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:48:22.366 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:48:22.528 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:48:22.529 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:48:22.529 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:48:22.529 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:48:22.840 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:48:23.312 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:48:23.529 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:48:23.529 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:48:23.530 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:48:23.530 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:48:23.785 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:48:24.258 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:48:24.530 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:48:24.530 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:48:24.531 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:48:24.531 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:48:24.731 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:48:25.203 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:48:25.677 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:48:26.149 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:48:26.621 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:48:27.093 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:48:27.566 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:48:28.039 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:48:28.511 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:48:28.982 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:48:29.456 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:48:29.928 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:48:30.399 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:48:30.873 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:48:31.345 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:48:31.818 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:48:32.291 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:48:32.764 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:48:33.236 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:48:33.710 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:48:34.182 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:48:34.655 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:48:35.128 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:48:35.601 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:48:35.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:48:35.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:48:35.911 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:48:35.911 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:48:35.921 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:48:35.921 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:48:35.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:48:35.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:48:35.923 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:48:35.923 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:48:35.923 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:48:35.923 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:48:35.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:48:35.927 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:48:35.927 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:48:35.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:48:35.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:48:36.073 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:48:36.544 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 01:48:37.017 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 01:48:37.489 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 01:48:37.962 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 01:48:38.435 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 01:48:38.908 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 01:48:39.380 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 01:48:39.853 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 01:48:40.326 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 01:48:40.798 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 01:48:41.269 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 01:48:41.742 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 01:48:42.215 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 01:48:42.687 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 01:48:43.161 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 01:48:43.633 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 01:48:44.106 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 01:48:44.579 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 01:48:45.052 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 01:48:45.523 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 01:48:45.996 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 01:48:46.469 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 01:48:46.941 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 01:48:47.415 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 01:48:47.887 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 01:48:48.358 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 01:48:48.832 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 01:48:49.304 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 01:48:49.777 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 01:48:50.250 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 01:48:50.723 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 01:48:51.195 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 01:48:51.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:48:51.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:48:51.388 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:48:51.388 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:48:51.407 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:48:51.407 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:48:51.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:48:51.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:48:51.409 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:48:51.409 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:48:51.410 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:48:51.410 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:48:51.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:48:51.434 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:48:51.434 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:48:51.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:48:51.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:48:51.666 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 01:48:52.137 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 01:48:52.610 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 01:48:53.083 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 01:48:53.555 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 01:48:54.029 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 01:48:54.501 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-06 01:48:54.974 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-06 01:48:55.447 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-06 01:48:55.920 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-06 01:48:56.392 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-06 01:48:56.863 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-06 01:48:57.337 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-06 01:48:57.813 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-06 01:48:58.286 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-06 01:48:58.757 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-06 01:48:59.230 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-06 01:48:59.703 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-06 01:49:00.175 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-06 01:49:00.646 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-06 01:49:01.119 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-06 01:49:01.592 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-06 01:49:02.065 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-06 01:49:02.538 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-06 01:49:03.011 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-06 01:49:03.482 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-06 01:49:03.955 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-06 01:49:04.428 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-06 01:49:04.900 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-06 01:49:05.374 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-06 01:49:05.847 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-06 01:49:06.319 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-06 01:49:06.790 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-06 01:49:06.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:49:06.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:49:06.868 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:49:06.868 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:49:06.881 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:49:06.881 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:49:06.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:49:06.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:49:06.882 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:49:06.882 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:49:06.882 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:49:06.882 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:49:06.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:49:06.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:49:06.938 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:49:06.938 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:49:06.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:49:06.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:49:07.263 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-06 01:49:07.735 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-06 01:49:08.207 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-06 01:49:08.679 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-06 01:49:09.152 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-06 01:49:09.625 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-06 01:49:10.097 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-06 01:49:10.571 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-06 01:49:11.043 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-06 01:49:11.516 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-06 01:49:11.989 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-06 01:49:12.462 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-06 01:49:12.934 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-06 01:49:13.408 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-06 01:49:13.880 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-06 01:49:14.352 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-06 01:49:14.826 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-06 01:49:15.298 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-06 01:49:15.770 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-06 01:49:16.244 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-06 01:49:16.717 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-06 01:49:17.189 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-06 01:49:17.663 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-06 01:49:18.135 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-06 01:49:18.608 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-06 01:49:19.081 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-06 01:49:19.554 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-06 01:49:20.026 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-06 01:49:20.500 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-06 01:49:20.972 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-06 01:49:21.445 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-06 01:49:21.916 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-06 01:49:22.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:49:22.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:49:22.365 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:49:22.366 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:49:22.378 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:49:22.378 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:49:22.378 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:49:22.378 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:49:22.380 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:49:22.380 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:49:22.380 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:49:22.380 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:49:22.380 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:49:22.380 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:49:22.380 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:49:22.380 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=13567 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:49:22.380 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=13567 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:49:22.380 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=13567 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:49:22.380 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=13567 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:49:22.380 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=13567 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:49:22.380 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=13567 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:49:27.389 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:49:27.390 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:49:27.390 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:49:27.390 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:49:27.390 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:49:27.390 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:49:27.400 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:49:27.401 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:49:27.401 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:49:27.401 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:49:27.401 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:49:27.403 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:49:27.403 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:49:27.403 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:49:27.403 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:49:27.403 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:49:27.403 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:49:27.404 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:49:27.404 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:49:27.404 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:49:27.406 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:49:27.406 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:49:27.406 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:49:27.406 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:49:27.406 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:49:27.406 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:49:27.406 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:49:27.406 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:49:27.406 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:49:27.408 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:49:27.408 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:49:27.408 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:49:27.409 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:49:27.409 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:49:27.409 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:49:27.409 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:49:27.409 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:49:27.409 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:49:27.412 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:49:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:49:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:49:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:49:27.412 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:49:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:49:27.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:49:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:49:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:49:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:49:27.412 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:49:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:49:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:49:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:49:27.412 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:49:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:49:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:49:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:49:27.412 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:49:27.412 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:49:27.413 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:49:27.413 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:49:27.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:49:27.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:49:27.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:49:27.414 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:49:27.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:49:27.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:49:27.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:49:27.414 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:49:27.414 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:49:27.414 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:49:27.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:49:27.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:49:27.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:49:32.420 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:49:32.420 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:49:32.420 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:49:32.420 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:49:32.420 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:49:32.420 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:49:32.431 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:49:32.432 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:49:32.432 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:49:32.432 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:49:32.432 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:49:32.435 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:49:32.435 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:49:32.435 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:49:32.435 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:49:32.436 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:49:32.436 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:49:32.436 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:49:32.436 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:49:32.436 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:49:32.437 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:49:32.438 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:49:32.438 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:49:32.438 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:49:32.438 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:49:32.438 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:49:32.438 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:49:32.438 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:49:32.438 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:49:32.440 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:49:32.440 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:49:32.440 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:49:32.440 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:49:32.440 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:49:32.440 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:49:32.440 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:49:32.440 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:49:32.440 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:49:32.443 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:49:32.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:49:32.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:49:32.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:49:32.443 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:49:32.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:49:32.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:49:32.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:49:32.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:49:32.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:49:32.443 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:49:32.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:49:32.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:49:32.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:49:32.443 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:49:32.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:49:32.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:49:32.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:49:32.443 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:49:32.443 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:49:32.443 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:49:32.443 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:49:32.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:49:32.448 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:49:32.923 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:49:32.969 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:49:32.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:49:32.972 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:49:32.974 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:49:33.008 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:49:33.008 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:49:33.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:49:33.016 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:49:33.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:49:33.018 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:49:33.018 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:49:33.018 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:49:33.018 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:49:33.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:49:33.074 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:49:33.074 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:49:33.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:49:33.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:49:33.395 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:49:33.445 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:49:33.446 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:49:33.446 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:49:33.447 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:49:33.866 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:49:34.339 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:49:34.447 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:49:34.447 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:49:34.447 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:49:34.448 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:49:34.812 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:49:35.284 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:49:35.447 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:49:35.448 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:49:35.448 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:49:35.448 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:49:35.755 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:49:36.226 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:49:36.448 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:49:36.449 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:49:36.449 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:49:36.449 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:49:36.700 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:49:37.172 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:49:37.450 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:49:37.450 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:49:37.450 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:49:37.451 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:49:37.645 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:49:38.115 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:49:38.589 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:49:39.062 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:49:39.534 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:49:40.007 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:49:40.480 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:49:40.952 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:49:41.423 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:49:41.897 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:49:42.369 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:49:42.842 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:49:43.312 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:49:43.786 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:49:43.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:49:43.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:49:43.886 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:49:43.886 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:49:43.889 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:49:43.889 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:49:43.889 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:49:43.889 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:49:43.890 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:49:43.890 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:49:43.890 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:49:43.890 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:49:43.890 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:49:43.890 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:49:43.890 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:49:48.898 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:49:48.898 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:49:48.898 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:49:48.898 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:49:48.898 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:49:48.898 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:49:48.906 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:49:48.908 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:49:48.908 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:49:48.909 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:49:48.909 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:49:48.914 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:49:48.915 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:49:48.915 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:49:48.915 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:49:48.916 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:49:48.916 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:49:48.917 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:49:48.917 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:49:48.917 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:49:48.918 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:49:48.918 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:49:48.919 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:49:48.919 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:49:48.919 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:49:48.919 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:49:48.919 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:49:48.919 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:49:48.919 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:49:48.922 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:49:48.922 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:49:48.922 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:49:48.922 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:49:48.922 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:49:48.922 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:49:48.922 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:49:48.922 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:49:48.922 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:49:48.925 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:49:48.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:49:48.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:49:48.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:49:48.925 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:49:48.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:49:48.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:49:48.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:49:48.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:49:48.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:49:48.926 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:49:48.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:49:48.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:49:48.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:49:48.926 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:49:48.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:49:48.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:49:48.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:49:48.926 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:49:48.926 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:49:48.926 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:49:48.926 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:49:48.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:49:48.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:49:48.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:49:48.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:49:48.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:49:48.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:49:48.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:49:48.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:49:48.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:49:48.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:49:48.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:49:48.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:49:48.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:49:48.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:49:48.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:49:48.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:49:48.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:49:48.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:49:48.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:49:48.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:49:48.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:49:48.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:49:48.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:49:48.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:49:48.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:49:48.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:49:48.931 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:49:49.407 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:49:49.449 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:49:49.449 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:49:49.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:49:49.452 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:49:49.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:49:49.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:49:49.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:49:49.490 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:49:49.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:49:49.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:49:49.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:49:49.493 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:49:49.493 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:49:49.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:49:49.501 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:49:49.501 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:49:49.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:49:49.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:49:49.876 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:49:49.929 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:49:49.929 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:49:49.929 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:49:49.929 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:49:50.350 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:49:50.823 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:49:50.930 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:49:50.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:49:50.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:49:50.931 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:49:51.296 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:49:51.769 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:49:51.931 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:49:51.932 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:49:51.932 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:49:51.932 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:49:52.241 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:49:52.712 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:49:52.932 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:49:52.933 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:49:52.933 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:49:52.933 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:49:53.185 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:49:53.658 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:49:53.933 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:49:53.934 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:49:53.934 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:49:53.934 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:49:54.130 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:49:54.601 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:49:55.075 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:49:55.547 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:49:56.019 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:49:56.490 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:49:56.963 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:49:57.436 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:49:57.909 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:49:58.379 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:49:58.850 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:49:59.321 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:49:59.794 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:49:59.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:49:59.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:49:59.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:49:59.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:49:59.898 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:49:59.898 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:49:59.899 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:49:59.899 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:49:59.900 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:49:59.900 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:49:59.900 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:49:59.900 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:49:59.901 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:49:59.901 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:49:59.901 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:50:04.905 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:50:04.905 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:50:04.905 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:50:04.905 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:50:04.905 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:50:04.905 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:50:04.908 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:50:04.909 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:50:04.909 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:50:04.909 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:50:04.909 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:50:04.911 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:50:04.912 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:50:04.912 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:50:04.912 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:50:04.912 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:50:04.912 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:50:04.912 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:50:04.912 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:50:04.912 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:50:04.915 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:50:04.915 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:50:04.915 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:50:04.915 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:50:04.915 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:50:04.916 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:50:04.916 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:50:04.916 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:50:04.916 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:50:04.918 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:50:04.918 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:50:04.918 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:50:04.918 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:50:04.919 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:50:04.919 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:50:04.919 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:50:04.919 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:50:04.919 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:50:04.923 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:50:04.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:50:04.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:50:04.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:50:04.923 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:50:04.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:50:04.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:50:04.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:50:04.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:50:04.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:50:04.923 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:50:04.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:50:04.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:50:04.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:50:04.923 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:50:04.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:50:04.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:50:04.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:50:04.924 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:50:04.924 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:50:04.924 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:50:04.924 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:50:04.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:50:04.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:50:04.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:50:04.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:50:04.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:50:04.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:50:04.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:50:04.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:50:04.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:50:04.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:50:04.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:50:04.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:50:04.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:50:04.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:50:04.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:50:04.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:50:04.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:50:04.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:50:04.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:50:04.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:50:04.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:50:04.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:50:04.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:50:04.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:50:04.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:50:04.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:50:04.929 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:50:05.407 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:50:05.450 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:50:05.452 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:50:05.454 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:50:05.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:50:05.486 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:50:05.486 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:50:05.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:50:05.491 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:50:05.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:50:05.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:50:05.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:50:05.493 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:50:05.493 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:50:05.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:50:05.501 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:50:05.501 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:50:05.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:50:05.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:50:05.880 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:50:05.926 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:50:05.927 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:50:05.927 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:50:05.928 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:50:06.351 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:50:06.365 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 01:50:06.824 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:50:06.927 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:50:06.928 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:50:06.928 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:50:06.929 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:50:07.297 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:50:07.769 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:50:07.929 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:50:07.929 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:50:07.929 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:50:07.929 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:50:08.240 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:50:08.714 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:50:08.930 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:50:08.930 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:50:08.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:50:08.931 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:50:09.186 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:50:09.658 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:50:09.931 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:50:09.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:50:09.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:50:09.931 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:50:10.129 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:50:10.603 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:50:11.075 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:50:11.548 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:50:12.019 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:50:12.489 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:50:12.960 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:50:13.434 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:50:13.906 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:50:14.379 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:50:14.850 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:50:15.320 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:50:15.794 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:50:16.267 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:50:16.738 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:50:17.211 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:50:17.684 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:50:18.156 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:50:18.630 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:50:19.102 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:50:19.575 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:50:20.048 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:50:20.521 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:50:20.993 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:50:21.464 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:50:21.938 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 01:50:22.410 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 01:50:22.883 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 01:50:23.356 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 01:50:23.829 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 01:50:24.301 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 01:50:24.772 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 01:50:25.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:50:25.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:50:25.096 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:50:25.096 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:50:25.108 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:50:25.109 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:50:25.109 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:50:25.109 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:50:25.111 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:50:25.111 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:50:25.111 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:50:25.111 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:50:25.111 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:50:25.111 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:50:25.111 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:50:30.115 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:50:30.115 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:50:30.115 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:50:30.115 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:50:30.115 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:50:30.115 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:50:30.123 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:50:30.123 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:50:30.123 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:50:30.123 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:50:30.123 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:50:30.126 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:50:30.126 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:50:30.126 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:50:30.126 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:50:30.126 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:50:30.126 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:50:30.126 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:50:30.126 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:50:30.126 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:50:30.129 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:50:30.129 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:50:30.129 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:50:30.129 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:50:30.129 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:50:30.129 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:50:30.129 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:50:30.129 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:50:30.129 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:50:30.131 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:50:30.131 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:50:30.131 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:50:30.131 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:50:30.132 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:50:30.132 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:50:30.132 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:50:30.132 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:50:30.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:50:30.135 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:50:30.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:50:30.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:50:30.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:50:30.135 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:50:30.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:50:30.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:50:30.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:50:30.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:50:30.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:50:30.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:50:30.135 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:50:30.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:50:30.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:50:30.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:50:30.136 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:50:30.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:50:30.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:50:30.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:50:30.136 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:50:30.136 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:50:30.136 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:50:30.136 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:50:30.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:50:30.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:50:30.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:50:30.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:50:30.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:50:30.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:50:30.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:50:30.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:50:30.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:50:30.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:50:30.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:50:30.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:50:30.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:50:30.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:50:30.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:50:30.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:50:30.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:50:30.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:50:30.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:50:30.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:50:30.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:50:30.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:50:30.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:50:30.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:50:30.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:50:30.141 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:50:30.620 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:50:30.659 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:50:30.660 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:50:30.663 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:50:30.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:50:30.700 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:50:30.701 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:50:30.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:50:30.708 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:50:30.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:50:30.711 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:50:30.711 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:50:30.711 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:50:30.711 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:50:30.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:50:30.770 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:50:30.770 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:50:30.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:50:30.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:50:31.092 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:50:31.138 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:50:31.139 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:50:31.139 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:50:31.139 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:50:31.563 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:50:32.034 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:50:32.058 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 01:50:32.139 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:50:32.140 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:50:32.140 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:50:32.140 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:50:32.507 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:50:32.980 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:50:33.024 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 01:50:33.140 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:50:33.141 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:50:33.141 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:50:33.141 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:50:33.453 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:50:33.926 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:50:33.984 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 01:50:34.142 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:50:34.142 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:50:34.142 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:50:34.142 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:50:34.399 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:50:34.871 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:50:34.950 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 01:50:35.142 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:50:35.143 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:50:35.143 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:50:35.143 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:50:35.345 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:50:35.817 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:50:35.916 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 01:50:36.290 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:50:36.763 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:50:36.876 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 01:50:37.236 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:50:37.708 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:50:37.842 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 01:50:38.179 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:50:38.650 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:50:38.802 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 01:50:39.123 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:50:39.595 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:50:39.768 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 01:50:40.068 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:50:40.539 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:50:40.728 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 01:50:41.012 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:50:41.485 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:50:41.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:50:41.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:50:41.587 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:50:41.587 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:50:41.598 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:50:41.599 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:50:41.599 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:50:41.599 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:50:41.603 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:50:41.603 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:50:41.603 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:50:41.603 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:50:41.603 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:50:41.604 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:50:41.604 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:50:41.604 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2475 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:50:41.604 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2475 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:50:41.604 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2475 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:50:41.604 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2475 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:50:41.604 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2475 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:50:41.605 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2475 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:50:46.607 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:50:46.607 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:50:46.607 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:50:46.607 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:50:46.607 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:50:46.607 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:50:46.613 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:50:46.614 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:50:46.614 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:50:46.615 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:50:46.615 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:50:46.618 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:50:46.618 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:50:46.619 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:50:46.619 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:50:46.619 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:50:46.620 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:50:46.620 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:50:46.620 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:50:46.620 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:50:46.622 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:50:46.622 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:50:46.622 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:50:46.622 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:50:46.623 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:50:46.623 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:50:46.623 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:50:46.623 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:50:46.623 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:50:46.624 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:50:46.625 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:50:46.625 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:50:46.625 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:50:46.625 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:50:46.625 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:50:46.625 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:50:46.625 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:50:46.625 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:50:46.631 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:50:46.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:50:46.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:50:46.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:50:46.631 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:50:46.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:50:46.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:50:46.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:50:46.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:50:46.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:50:46.632 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:50:46.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:50:46.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:50:46.632 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:50:46.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:50:46.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:50:46.632 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:50:46.632 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:50:46.632 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:50:46.632 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:50:46.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:50:46.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:50:46.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:50:46.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:50:46.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:50:46.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:50:46.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:50:46.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:50:46.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:50:46.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:50:46.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:50:46.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:50:46.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:50:46.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:50:46.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:50:46.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:50:46.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:50:46.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:50:46.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:50:46.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:50:46.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:50:46.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:50:46.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:50:46.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:50:46.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:50:46.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:50:46.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:50:46.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:50:46.637 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:50:47.113 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:50:47.160 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:50:47.162 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:50:47.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:50:47.164 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:50:47.198 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:50:47.198 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:50:47.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:50:47.203 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:50:47.204 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:50:47.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:50:47.205 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:50:47.206 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:50:47.206 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:50:47.206 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:50:47.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:50:47.265 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:50:47.265 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:50:47.265 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:50:47.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:50:47.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:50:47.583 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:50:47.636 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:50:47.636 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:50:47.636 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:50:47.636 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:50:48.056 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:50:48.529 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:50:48.552 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 01:50:48.637 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:50:48.638 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:50:48.638 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:50:48.638 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:50:49.002 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:50:49.475 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:50:49.638 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:50:49.638 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:50:49.638 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:50:49.639 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:50:49.947 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:50:50.421 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:50:50.639 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:50:50.640 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:50:50.640 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:50:50.640 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:50:50.892 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:50:51.365 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:50:51.641 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:50:51.641 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:50:51.641 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:50:51.641 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:50:51.835 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:50:52.309 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:50:52.782 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:50:53.253 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:50:53.726 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:50:54.199 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:50:54.671 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:50:55.144 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:50:55.617 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:50:56.089 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:50:56.560 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:50:57.031 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:50:57.505 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:50:57.977 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:50:58.188 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:50:58.449 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:50:58.920 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:50:59.391 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:50:59.864 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:51:00.337 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:51:00.809 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:51:01.280 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:51:01.754 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:51:02.226 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:51:02.698 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:51:03.169 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:51:03.643 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 01:51:03.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:03.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:03.968 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:51:03.968 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:51:03.979 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:03.979 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:03.979 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:03.979 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:03.983 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:51:03.984 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:51:03.984 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:51:03.984 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:51:03.984 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:51:03.984 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:51:03.985 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:51:03.985 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3748 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:03.985 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3748 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:03.985 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3748 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:03.985 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3748 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:03.985 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3748 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:03.985 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3748 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:08.986 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:51:08.986 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:51:08.986 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:51:08.986 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:51:08.986 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:51:08.986 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:51:08.994 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:51:08.996 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:51:08.996 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:51:08.997 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:51:08.997 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:51:09.003 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:51:09.004 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:51:09.004 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:51:09.004 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:51:09.005 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:51:09.005 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:51:09.005 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:51:09.006 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:51:09.006 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:09.008 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:51:09.009 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:51:09.009 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:51:09.009 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:51:09.010 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:51:09.010 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:51:09.010 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:51:09.010 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:51:09.010 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:09.012 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:51:09.012 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:51:09.013 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:51:09.013 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:51:09.013 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:51:09.013 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:51:09.013 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:51:09.013 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:51:09.013 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:09.017 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:51:09.017 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:51:09.017 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:51:09.017 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:51:09.017 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:51:09.017 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:51:09.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:51:09.017 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:09.017 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:51:09.017 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:51:09.017 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:51:09.017 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:09.017 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:09.017 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:09.017 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:09.017 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:09.017 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:09.017 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:09.017 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:51:09.017 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:51:09.017 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:51:09.018 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:51:09.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:09.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:09.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:09.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:51:09.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:09.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:09.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:09.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:09.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:09.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:09.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:09.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:09.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:09.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:09.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:09.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:09.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:09.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:09.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:09.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:09.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:09.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:09.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:09.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:09.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:09.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:09.022 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:51:09.499 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:51:09.545 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:51:09.546 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:51:09.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:09.548 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:51:09.564 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:51:09.564 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:51:09.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:51:09.569 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:51:09.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:09.572 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:51:09.572 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:51:09.573 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:51:09.573 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:51:09.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:09.602 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:51:09.602 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:51:09.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:09.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:09.970 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:51:10.021 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:10.021 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:10.022 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:10.022 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:10.442 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:51:10.457 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 01:51:10.913 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:51:11.023 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:11.023 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:11.023 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:11.024 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:11.387 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:51:11.859 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:51:12.024 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:12.024 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:12.024 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:12.024 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:12.331 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:51:12.802 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:51:13.025 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:13.026 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:13.026 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:13.026 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:13.273 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:51:13.747 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:51:14.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:14.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:14.027 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:14.027 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:14.219 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:51:14.692 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:51:15.162 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:51:15.636 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:51:16.109 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:51:16.581 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:51:17.052 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:51:17.523 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:51:17.996 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:51:18.468 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:51:18.941 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:51:19.412 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:51:19.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:19.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:19.608 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:51:19.609 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:51:19.620 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:19.620 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:19.620 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:19.620 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:19.622 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:51:19.623 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:51:19.623 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:51:19.623 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:51:19.623 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:51:19.623 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:51:19.623 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:51:19.623 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2292 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:19.623 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2292 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:19.623 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2292 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:19.623 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2292 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:19.623 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2292 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:19.623 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2292 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:24.628 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:51:24.628 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:51:24.628 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:51:24.628 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:51:24.628 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:51:24.628 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:51:24.635 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:51:24.636 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:51:24.636 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:51:24.636 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:51:24.636 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:51:24.638 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:51:24.638 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:51:24.639 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:51:24.639 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:51:24.639 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:51:24.639 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:51:24.640 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:51:24.640 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:51:24.640 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:24.641 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:51:24.641 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:51:24.641 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:51:24.641 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:51:24.641 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:51:24.641 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:51:24.641 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:51:24.641 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:51:24.641 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:24.643 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:51:24.643 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:51:24.643 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:51:24.643 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:51:24.643 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:51:24.643 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:51:24.643 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:51:24.643 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:51:24.643 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:24.645 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:51:24.645 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:51:24.645 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:51:24.645 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:51:24.645 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:51:24.645 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:51:24.646 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:51:24.646 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:51:24.646 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:24.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:24.647 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:24.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:24.647 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:24.647 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:24.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:24.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:24.651 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:51:25.127 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:51:25.174 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:51:25.176 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:51:25.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:25.179 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:51:25.199 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:51:25.200 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:51:25.200 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:51:25.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:25.205 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:51:25.205 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:51:25.205 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:51:25.205 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:51:25.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:25.229 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:51:25.229 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:51:25.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:25.230 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:25.599 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:51:25.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:25.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:25.611 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:51:25.611 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:51:25.628 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:51:25.628 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:51:25.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:51:25.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:25.630 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:51:25.630 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:51:25.630 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:51:25.630 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:51:25.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:25.647 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:51:25.648 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:51:25.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:25.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:25.648 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:25.648 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:25.648 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:25.648 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:26.070 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:51:26.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:26.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:26.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:51:26.330 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:51:26.347 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:51:26.348 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:51:26.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:51:26.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:26.349 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:51:26.349 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:51:26.349 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:51:26.349 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:51:26.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:26.408 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:51:26.408 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:51:26.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:26.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:26.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:26.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:26.510 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:51:26.511 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:51:26.526 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:51:26.526 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:51:26.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:51:26.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:26.528 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:51:26.528 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:51:26.528 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:51:26.528 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:51:26.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:26.538 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:51:26.538 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:51:26.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:26.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:26.540 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:51:26.650 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:26.650 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:26.650 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:26.650 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:26.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:26.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:26.935 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:51:26.935 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:51:26.943 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:26.943 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:26.943 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:26.943 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:26.944 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:51:26.944 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:51:26.944 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:51:26.944 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:51:26.944 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:51:26.944 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:51:26.944 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:51:31.956 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:51:31.956 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:51:31.956 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:51:31.956 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:51:31.956 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:51:31.956 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:51:31.970 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:51:31.971 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:51:31.971 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:51:31.971 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:51:31.972 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:51:31.974 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:51:31.975 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:51:31.975 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:51:31.975 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:51:31.975 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:51:31.976 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:51:31.976 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:51:31.976 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:51:31.976 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:31.979 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:51:31.980 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:51:31.980 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:51:31.980 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:51:31.981 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:51:31.981 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:51:31.982 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:51:31.982 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:51:31.982 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:31.984 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:51:31.985 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:51:31.985 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:51:31.985 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:51:31.985 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:51:31.985 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:51:31.986 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:51:31.986 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:51:31.986 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:31.992 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:51:31.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:51:31.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:51:31.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:51:31.992 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:51:31.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:51:31.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:51:31.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:31.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:51:31.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:51:31.993 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:51:31.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:31.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:31.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:31.993 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:31.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:31.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:31.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:31.993 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:51:31.993 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:51:31.993 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:51:31.993 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:51:31.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:31.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:31.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:31.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:51:31.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:31.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:31.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:31.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:31.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:31.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:31.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:31.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:31.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:31.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:31.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:31.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:31.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:31.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:31.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:31.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:31.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:31.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:31.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:31.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:31.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:31.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:31.998 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:51:32.475 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:51:32.531 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:51:32.533 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:51:32.535 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:51:32.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:32.560 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:51:32.560 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:51:32.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:51:32.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:32.564 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:51:32.564 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:51:32.564 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:51:32.564 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:51:32.614 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:51:32.620 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 01:51:32.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:32.628 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:51:32.629 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:51:32.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:32.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:32.947 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:51:32.998 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:32.999 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:32.999 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:33.001 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:33.419 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:51:33.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:33.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:33.441 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:51:33.441 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:51:33.450 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:33.450 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:33.451 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:33.451 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:33.454 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:51:33.454 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:51:33.455 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:51:33.455 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:51:33.455 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:51:33.455 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:51:33.455 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:51:33.455 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=316 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:33.455 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=316 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:33.456 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=316 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:33.456 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=316 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:33.456 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=316 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:33.456 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=316 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:38.456 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:51:38.456 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:51:38.456 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:51:38.456 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:51:38.456 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:51:38.456 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:51:38.461 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:51:38.462 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:51:38.462 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:51:38.463 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:51:38.463 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:51:38.465 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:51:38.465 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:51:38.466 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:51:38.466 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:51:38.466 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:51:38.466 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:51:38.467 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:51:38.467 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:51:38.467 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:38.468 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:51:38.468 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:51:38.468 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:51:38.468 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:51:38.468 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:51:38.468 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:51:38.469 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:51:38.469 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:51:38.469 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:38.471 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:51:38.471 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:51:38.471 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:51:38.471 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:51:38.471 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:51:38.471 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:51:38.471 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:51:38.471 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:51:38.471 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:38.474 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:51:38.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:51:38.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:51:38.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:51:38.474 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:51:38.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:51:38.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:51:38.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:38.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:51:38.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:51:38.474 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:51:38.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:38.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:38.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:38.474 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:38.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:38.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:38.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:38.474 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:51:38.474 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:51:38.474 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:51:38.474 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:51:38.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:38.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:38.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:38.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:51:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:38.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:38.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:38.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:38.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:38.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:38.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:38.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:38.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:38.479 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:51:38.956 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:51:39.001 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:51:39.003 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:51:39.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:39.006 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:51:39.031 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:51:39.031 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:51:39.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:51:39.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:39.034 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:51:39.034 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:51:39.034 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:51:39.034 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:51:39.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:39.055 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:51:39.055 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:51:39.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:39.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:39.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:39.427 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:51:39.477 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:39.477 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:39.477 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:39.477 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:39.899 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:51:40.373 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:51:40.479 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:40.479 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:40.479 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:40.479 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:40.845 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:51:41.318 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:51:41.479 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:41.480 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:41.480 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:41.480 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:41.791 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:51:42.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:42.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:42.166 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:51:42.166 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:51:42.185 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:51:42.185 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:51:42.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:51:42.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:42.186 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:51:42.186 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:51:42.186 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:51:42.186 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:51:42.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:42.212 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:51:42.212 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:51:42.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:42.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:42.263 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:51:42.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:42.481 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:42.481 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:42.481 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:42.482 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:42.735 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:51:43.206 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:51:43.482 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:43.482 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:43.482 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:43.483 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:43.677 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:51:44.148 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:51:44.621 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:51:45.094 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:51:45.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:45.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:45.395 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:51:45.395 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:51:45.416 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:51:45.416 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:51:45.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:51:45.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:45.417 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:51:45.417 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:51:45.417 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:51:45.417 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:51:45.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:45.479 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:51:45.480 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:51:45.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:45.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:45.566 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:51:45.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:46.037 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:51:46.510 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:51:46.983 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:51:47.455 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:51:47.926 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:51:48.399 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:51:48.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:48.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:48.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:51:48.801 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:51:48.812 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:51:48.812 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:51:48.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:51:48.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:48.813 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:51:48.813 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:51:48.813 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:51:48.813 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:51:48.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:48.868 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:51:48.868 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:51:48.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:48.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:48.871 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:51:49.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:49.343 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:51:49.814 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:51:50.287 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:51:50.759 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:51:51.231 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:51:51.702 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:51:52.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:52.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:52.035 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:51:52.036 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:51:52.046 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:52.047 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:52.047 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:52.047 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:52.049 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:51:52.049 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:51:52.049 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:51:52.049 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:51:52.049 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:51:52.049 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:51:52.049 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:51:52.049 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2933 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:52.049 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2933 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:52.049 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2933 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:52.049 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2933 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:52.049 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2933 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:52.049 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2933 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:52.049 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2933 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:51:57.054 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:51:57.054 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:51:57.054 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:51:57.054 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:51:57.054 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:51:57.054 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:51:57.062 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:51:57.063 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:51:57.063 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:51:57.063 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:51:57.063 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:51:57.065 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:51:57.066 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:51:57.066 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:51:57.066 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:51:57.066 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:51:57.066 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:51:57.067 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:51:57.067 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:51:57.067 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:57.068 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:51:57.068 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:51:57.068 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:51:57.068 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:51:57.068 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:51:57.068 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:51:57.068 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:51:57.068 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:51:57.068 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:57.070 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:51:57.070 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:51:57.070 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:51:57.070 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:51:57.070 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:51:57.070 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:51:57.070 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:51:57.070 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:51:57.071 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:51:57.073 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:51:57.073 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:51:57.073 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:57.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:57.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:57.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:57.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:57.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:57.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:57.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:57.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:57.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:57.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:57.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:51:57.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:57.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:57.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:57.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:51:57.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:57.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:57.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:51:57.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:57.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:51:57.078 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:51:57.556 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:51:57.591 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:51:57.592 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:51:57.594 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:51:57.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:51:57.595 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:51:57.595 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:51:57.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:51:57.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:51:57.596 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:51:57.596 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:51:57.596 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:51:57.596 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:51:58.027 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:51:58.076 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:58.076 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:58.076 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:58.076 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:58.499 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:51:58.970 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:51:59.078 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:51:59.078 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:51:59.078 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:51:59.078 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:51:59.443 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:51:59.915 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:52:00.078 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:52:00.079 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:52:00.079 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:52:00.079 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:52:00.387 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:52:00.858 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:52:01.079 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:52:01.080 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:52:01.080 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:52:01.080 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:52:01.329 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:52:01.803 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:52:02.080 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:52:02.081 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:52:02.081 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:52:02.081 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:52:02.275 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:52:02.747 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:52:03.218 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:52:03.692 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:52:04.164 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:52:04.635 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:52:05.107 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:52:05.580 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:52:06.052 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:52:06.524 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:52:06.998 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:52:07.470 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:52:07.942 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:52:08.416 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:52:08.888 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:52:09.360 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:52:09.831 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:52:10.304 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:52:10.777 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:52:11.249 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:52:11.533 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:52:11.533 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:52:11.536 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:52:11.536 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:52:11.536 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:52:11.536 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:52:11.537 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:52:11.537 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:52:11.537 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:52:11.537 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:52:11.537 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:52:11.537 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:52:11.537 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:52:16.545 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:52:16.545 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:52:16.545 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:52:16.545 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:52:16.545 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:52:16.545 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:52:16.548 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:52:16.548 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:52:16.548 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:52:16.548 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:52:16.548 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:52:16.549 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:52:16.549 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:52:16.549 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:52:16.549 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:52:16.549 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:52:16.549 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:52:16.550 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:52:16.550 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:52:16.550 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:52:16.550 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:52:16.550 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:52:16.550 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:52:16.550 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:52:16.550 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:52:16.550 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:52:16.550 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:52:16.550 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:52:16.550 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:52:16.551 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:52:16.552 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:52:16.552 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:52:16.552 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:52:16.552 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:52:16.552 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:52:16.552 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:52:16.552 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:52:16.552 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:52:16.553 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:52:16.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:52:16.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:52:16.554 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:52:16.554 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:52:16.554 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:52:16.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:52:16.559 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:52:17.037 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:52:17.077 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:52:17.078 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:52:17.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:52:17.080 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:52:17.097 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:52:17.097 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:52:17.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:52:17.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:52:17.101 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:52:17.101 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:52:17.101 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:52:17.101 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:52:17.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:52:17.143 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:52:17.143 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:52:17.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:52:17.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:52:17.509 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:52:17.556 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:52:17.566 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:52:17.566 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:52:17.566 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:52:17.981 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:52:18.454 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:52:18.566 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:52:18.567 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:52:18.567 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:52:18.567 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:52:18.927 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:52:19.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:52:19.144 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:52:19.144 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:52:19.145 [WARNING] transceiver.py:257 (MS@172.18.59.22:6700) RX TRXD message (fn=559 tn=0 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:52:19.145 [WARNING] transceiver.py:257 (MS@172.18.59.22:6700) RX TRXD message (fn=559 tn=1 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:52:19.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:52:19.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:52:19.148 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:52:19.148 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:52:19.148 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:52:19.148 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:52:19.399 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:52:19.568 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:52:19.568 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:52:19.568 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:52:19.568 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:52:19.870 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:52:20.343 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:52:20.569 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:52:20.569 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:52:20.570 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:52:20.570 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:52:20.816 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:52:21.288 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:52:21.570 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:52:21.570 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:52:21.570 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:52:21.570 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:52:21.759 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:52:22.230 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:52:22.703 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:52:23.175 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:52:23.647 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:52:24.118 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:52:24.591 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:52:25.064 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:52:25.536 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:52:26.007 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:52:26.480 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:52:26.952 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:52:27.424 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:52:27.895 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:52:28.369 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:52:28.841 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:52:29.313 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:52:29.784 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:52:30.258 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:52:30.730 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:52:31.202 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:52:31.673 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:52:32.147 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:52:32.619 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:52:33.091 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:52:33.562 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 01:52:33.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:52:33.848 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:52:33.848 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:52:33.861 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:52:33.861 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:52:33.861 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:52:33.862 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:52:33.863 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:52:33.863 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:52:33.863 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:52:33.863 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:52:33.863 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:52:33.863 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:52:33.863 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:52:38.868 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:52:38.868 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:52:38.868 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:52:38.868 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:52:38.868 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:52:38.868 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:52:38.877 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:52:38.878 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:52:38.879 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:52:38.879 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:52:38.879 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:52:38.883 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:52:38.883 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:52:38.883 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:52:38.883 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:52:38.884 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:52:38.884 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:52:38.884 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:52:38.884 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:52:38.884 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:52:38.887 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:52:38.887 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:52:38.888 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:52:38.888 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:52:38.888 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:52:38.888 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:52:38.888 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:52:38.888 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:52:38.888 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:52:38.891 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:52:38.891 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:52:38.891 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:52:38.891 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:52:38.891 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:52:38.891 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:52:38.891 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:52:38.891 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:52:38.892 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:52:38.895 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:52:38.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:52:38.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:52:38.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:52:38.895 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:52:38.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:52:38.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:52:38.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:52:38.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:52:38.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:52:38.895 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:52:38.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:52:38.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:52:38.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:52:38.896 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:52:38.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:52:38.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:52:38.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:52:38.896 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:52:38.896 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:52:38.896 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:52:38.896 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:52:38.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:52:38.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:52:38.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:52:38.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:52:38.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:52:38.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:52:38.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:52:38.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:52:38.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:52:38.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:52:38.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:52:38.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:52:38.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:52:38.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:52:38.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:52:38.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:52:38.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:52:38.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:52:38.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:52:38.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:52:38.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:52:38.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:52:38.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:52:38.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:52:38.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:52:38.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:52:38.901 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:52:39.377 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:52:39.418 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:52:39.419 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:52:39.421 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:52:39.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:52:39.425 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:52:39.425 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:52:39.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:52:39.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:52:39.426 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:52:39.426 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:52:39.426 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:52:39.426 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:52:39.849 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:52:39.899 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:52:39.899 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:52:39.899 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:52:39.900 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:52:40.320 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:52:40.793 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:52:40.900 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:52:40.901 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:52:40.901 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:52:40.901 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:52:41.266 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:52:41.738 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:52:41.902 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:52:41.902 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:52:41.902 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:52:41.903 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:52:42.212 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:52:42.684 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:52:42.903 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:52:42.904 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:52:42.904 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:52:42.904 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:52:43.156 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:52:43.627 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:52:43.905 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:52:43.905 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:52:43.905 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:52:43.905 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:52:44.100 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:52:44.572 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:52:45.044 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:52:45.518 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:52:45.990 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:52:46.462 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:52:46.933 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:52:47.407 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:52:47.879 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:52:48.351 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:52:48.824 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:52:49.297 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:52:49.769 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:52:50.243 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:52:50.715 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:52:51.187 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:52:51.658 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:52:52.131 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:52:52.604 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:52:53.076 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:52:53.547 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:52:54.017 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:52:54.488 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:52:54.962 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:52:55.434 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:52:55.906 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 01:52:56.377 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 01:52:56.851 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 01:52:57.322 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 01:52:57.795 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 01:52:58.265 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 01:52:58.738 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 01:52:59.211 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 01:52:59.683 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 01:53:00.154 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 01:53:00.627 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 01:53:00.913 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:53:00.913 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:53:00.918 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:53:00.918 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:53:00.918 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:53:00.918 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:53:00.922 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:53:00.922 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:53:00.922 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:53:00.922 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:53:00.923 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:53:00.923 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:53:00.923 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:53:00.923 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4758 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:53:00.923 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4758 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:53:00.923 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4758 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:53:00.924 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4758 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:53:00.924 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4758 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:53:00.924 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4758 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:53:05.925 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:53:05.925 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:53:05.925 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:53:05.925 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:53:05.925 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:53:05.925 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:53:05.932 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:53:05.932 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:53:05.932 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:53:05.933 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:53:05.933 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:53:05.935 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:53:05.935 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:53:05.935 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:53:05.935 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:53:05.935 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:53:05.935 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:53:05.935 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:53:05.935 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:53:05.935 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:53:05.937 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:53:05.937 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:53:05.938 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:53:05.938 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:53:05.938 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:53:05.938 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:53:05.938 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:53:05.938 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:53:05.938 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:53:05.940 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:53:05.940 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:53:05.940 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:53:05.940 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:53:05.940 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:53:05.940 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:53:05.940 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:53:05.940 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:53:05.940 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:53:05.942 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:53:05.942 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:53:05.942 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:53:05.942 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:53:05.942 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:53:05.943 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:53:05.943 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:53:05.943 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:53:05.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:53:05.944 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:53:05.944 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:53:05.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:53:05.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:53:05.944 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:53:05.944 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:53:05.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:53:05.944 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:53:05.944 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:53:05.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:53:05.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:53:05.948 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:53:06.426 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:53:06.466 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:53:06.468 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:53:06.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:53:06.470 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:53:06.473 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:53:06.473 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:53:06.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:53:06.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:53:06.474 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:53:06.474 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:53:06.474 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:53:06.474 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:53:06.898 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:53:06.945 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:53:06.945 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:53:06.945 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:53:06.945 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:53:07.369 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:53:07.843 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:53:07.945 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:53:07.946 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:53:07.946 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:53:07.946 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:53:08.315 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:53:08.787 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:53:08.947 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:53:08.948 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:53:08.948 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:53:08.948 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:53:09.261 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:53:09.733 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:53:09.948 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:53:09.949 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:53:09.949 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:53:09.949 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:53:10.205 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:53:10.676 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:53:10.950 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:53:10.950 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:53:10.950 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:53:10.950 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:53:11.149 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:53:11.621 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:53:12.093 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:53:12.567 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:53:13.040 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:53:13.511 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:53:13.983 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:53:14.456 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:53:14.928 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:53:15.400 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:53:15.872 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:53:16.345 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:53:16.817 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:53:17.289 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:53:17.760 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:53:18.234 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:53:18.706 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:53:19.178 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:53:19.649 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:53:20.123 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:53:20.595 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:53:21.067 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:53:21.538 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:53:22.012 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:53:22.484 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:53:22.956 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 01:53:23.429 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 01:53:23.902 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 01:53:24.374 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 01:53:24.847 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 01:53:25.320 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 01:53:25.792 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 01:53:26.263 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 01:53:26.736 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 01:53:27.208 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 01:53:27.680 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 01:53:27.957 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:53:27.957 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:53:27.961 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:53:27.961 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:53:27.961 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:53:27.961 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:53:27.961 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:53:27.961 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:53:27.961 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:53:27.961 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:53:27.961 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:53:27.962 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:53:27.962 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:53:32.968 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:53:32.968 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:53:32.968 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:53:32.968 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:53:32.968 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:53:32.968 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:53:32.978 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:53:32.979 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:53:32.979 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:53:32.980 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:53:32.980 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:53:32.983 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:53:32.983 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:53:32.983 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:53:32.983 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:53:32.983 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:53:32.983 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:53:32.984 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:53:32.984 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:53:32.984 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:53:32.987 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:53:32.988 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:53:32.988 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:53:32.988 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:53:32.988 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:53:32.988 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:53:32.988 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:53:32.988 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:53:32.988 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:53:32.991 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:53:32.991 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:53:32.991 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:53:32.991 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:53:32.991 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:53:32.991 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:53:32.991 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:53:32.991 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:53:32.991 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:53:32.994 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:53:32.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:53:32.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:53:32.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:53:32.994 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:53:32.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:53:32.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:53:32.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:53:32.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:53:32.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:53:32.995 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:53:32.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:53:32.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:53:32.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:53:32.995 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:53:32.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:53:32.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:53:32.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:53:32.995 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:53:32.995 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:53:32.995 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:53:32.995 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:53:32.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:53:32.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:53:32.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:53:32.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:53:32.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:53:32.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:53:32.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:53:32.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:53:32.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:53:32.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:53:32.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:53:32.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:53:32.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:53:32.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:53:32.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:53:32.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:53:32.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:53:32.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:53:32.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:53:32.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:53:32.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:53:32.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:53:32.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:53:32.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:53:32.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:53:32.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:53:33.000 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:53:33.478 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:53:33.520 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:53:33.521 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:53:33.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:53:33.522 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:53:33.524 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:53:33.524 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:53:33.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:53:33.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:53:33.524 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:53:33.524 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:53:33.525 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:53:33.525 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:53:33.950 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:53:33.998 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:53:33.998 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:53:33.999 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:53:33.999 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:53:34.421 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:53:34.894 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:53:35.000 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:53:35.000 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:53:35.000 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:53:35.000 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:53:35.367 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:53:35.839 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:53:36.000 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:53:36.001 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:53:36.001 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:53:36.001 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:53:36.310 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:53:36.784 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:53:37.001 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:53:37.002 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:53:37.002 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:53:37.002 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:53:37.256 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:53:37.728 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:53:38.003 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:53:38.003 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:53:38.003 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:53:38.004 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:53:38.199 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:53:38.670 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:53:39.143 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:53:39.615 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:53:40.087 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:53:40.561 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:53:41.033 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:53:41.506 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:53:41.979 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:53:42.451 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:53:42.923 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:53:43.394 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:53:43.865 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:53:44.339 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:53:44.810 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:53:45.283 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:53:45.756 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:53:46.228 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:53:46.701 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:53:47.171 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:53:47.642 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:53:48.116 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:53:48.588 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:53:49.060 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:53:49.531 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:53:50.005 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 01:53:50.477 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 01:53:50.949 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 01:53:51.420 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 01:53:51.893 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 01:53:52.366 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 01:53:52.838 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 01:53:53.312 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 01:53:53.784 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 01:53:54.256 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 01:53:54.727 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 01:53:55.200 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 01:53:55.673 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 01:53:56.145 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 01:53:56.616 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 01:53:57.089 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 01:53:57.561 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 01:53:58.033 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 01:53:58.504 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 01:53:58.977 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 01:53:59.450 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 01:53:59.922 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 01:54:00.393 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 01:54:00.866 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 01:54:01.338 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 01:54:01.810 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 01:54:02.281 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 01:54:02.754 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 01:54:03.227 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 01:54:03.699 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 01:54:04.170 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 01:54:04.643 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 01:54:05.116 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 01:54:05.588 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 01:54:06.061 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 01:54:06.534 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 01:54:07.006 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 01:54:07.016 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:54:07.016 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:54:07.021 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:54:07.021 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:54:07.022 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:54:07.022 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:54:07.023 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:54:07.023 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:54:07.023 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:54:07.023 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:54:07.023 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:54:07.023 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:54:07.023 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:54:07.023 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7350 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:07.023 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7350 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:07.023 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7350 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:07.023 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7350 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:07.023 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7350 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:07.023 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7350 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:07.023 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7350 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:07.023 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7350 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:12.029 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:54:12.029 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:54:12.029 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:54:12.029 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:54:12.029 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:54:12.029 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:54:12.035 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:54:12.036 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:54:12.036 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:54:12.036 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:54:12.036 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:54:12.038 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:54:12.038 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:54:12.039 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:54:12.039 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:54:12.039 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:54:12.039 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:54:12.039 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:54:12.039 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:54:12.039 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:54:12.043 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:54:12.043 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:54:12.043 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:54:12.043 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:54:12.043 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:54:12.043 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:54:12.043 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:54:12.043 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:54:12.044 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:54:12.046 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:54:12.046 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:54:12.047 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:54:12.047 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:54:12.047 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:54:12.047 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:54:12.047 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:54:12.047 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:54:12.047 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:54:12.051 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:54:12.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:54:12.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:54:12.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:54:12.051 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:54:12.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:54:12.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:54:12.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:12.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:54:12.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:54:12.051 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:54:12.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:12.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:12.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:12.051 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:54:12.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:12.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:12.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:12.051 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:54:12.051 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:54:12.051 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:54:12.052 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:54:12.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:12.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:12.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:12.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:54:12.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:12.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:12.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:12.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:12.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:12.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:12.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:12.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:12.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:12.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:12.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:12.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:12.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:12.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:12.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:12.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:12.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:12.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:12.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:12.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:12.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:12.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:12.056 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:54:12.532 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:54:12.578 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:54:12.581 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:54:12.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:54:12.585 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:54:12.588 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:54:12.588 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:54:12.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:54:12.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:54:12.589 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:54:12.589 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:54:12.590 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:54:12.590 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:54:13.002 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:54:13.054 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:54:13.054 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:54:13.054 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:54:13.055 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:54:13.470 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:54:13.941 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:54:14.055 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:54:14.055 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:54:14.055 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:54:14.056 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:54:14.412 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:54:14.883 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:54:15.056 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:54:15.056 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:54:15.057 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:54:15.057 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:54:15.356 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:54:15.829 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:54:16.058 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:54:16.058 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:54:16.058 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:54:16.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:54:16.301 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:54:16.772 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:54:17.059 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:54:17.060 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:54:17.060 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:54:17.060 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:54:17.245 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:54:17.717 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:54:18.190 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:54:18.663 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:54:19.135 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:54:19.608 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:54:20.081 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:54:20.553 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:54:21.026 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:54:21.496 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:54:21.970 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:54:22.442 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:54:22.914 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:54:23.385 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:54:23.858 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:54:24.330 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:54:24.803 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:54:25.276 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:54:25.748 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:54:26.221 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:54:26.694 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:54:27.166 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:54:27.638 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:54:28.109 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:54:28.582 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:54:29.054 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 01:54:29.526 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 01:54:29.997 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 01:54:30.471 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 01:54:30.943 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 01:54:31.415 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 01:54:31.886 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 01:54:32.359 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 01:54:32.831 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 01:54:33.304 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 01:54:33.775 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 01:54:34.248 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 01:54:34.720 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 01:54:35.192 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 01:54:35.664 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 01:54:36.134 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 01:54:36.607 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 01:54:37.079 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 01:54:37.551 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 01:54:38.022 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 01:54:38.496 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 01:54:38.968 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 01:54:39.440 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 01:54:39.911 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 01:54:40.070 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:54:40.070 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:54:40.075 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:54:40.075 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:54:40.075 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:54:40.076 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:54:40.077 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:54:40.077 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:54:40.077 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:54:40.077 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:54:40.077 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:54:40.077 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:54:40.077 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:54:40.077 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6056 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:40.077 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6056 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:40.077 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6056 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:40.077 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6056 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:40.077 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6056 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:40.077 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6056 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:45.082 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:54:45.082 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:54:45.082 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:54:45.083 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:54:45.083 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:54:45.083 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:54:45.090 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:54:45.090 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:54:45.091 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:54:45.091 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:54:45.091 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:54:45.094 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:54:45.095 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:54:45.095 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:54:45.095 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:54:45.096 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:54:45.096 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:54:45.097 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:54:45.097 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:54:45.097 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:54:45.099 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:54:45.099 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:54:45.099 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:54:45.099 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:54:45.100 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:54:45.100 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:54:45.100 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:54:45.100 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:54:45.100 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:54:45.102 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:54:45.103 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:54:45.103 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:54:45.103 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:54:45.103 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:54:45.103 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:54:45.103 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:54:45.103 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:54:45.103 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:54:45.106 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:54:45.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:54:45.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:54:45.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:54:45.107 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:54:45.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:54:45.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:54:45.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:45.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:54:45.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:54:45.107 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:54:45.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:45.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:45.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:45.107 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:54:45.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:45.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:45.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:45.107 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:54:45.107 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:54:45.107 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:54:45.107 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:54:45.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:45.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:45.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:45.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:54:45.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:45.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:45.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:45.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:45.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:45.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:45.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:45.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:45.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:45.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:45.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:45.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:45.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:45.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:45.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:45.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:45.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:45.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:45.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:45.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:45.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:45.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:45.112 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:54:45.589 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:54:45.634 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:54:45.636 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:54:45.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:54:45.637 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:54:45.647 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:54:45.647 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:54:45.647 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:54:45.647 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:54:45.651 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:54:45.651 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:54:45.651 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:54:45.652 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:54:45.652 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:54:45.652 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:54:45.652 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:54:45.652 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:45.652 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:45.653 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:45.653 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:45.653 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:45.653 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:45.653 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:50.654 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:54:50.654 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:54:50.654 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:54:50.654 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:54:50.654 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:54:50.654 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:54:50.662 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:54:50.663 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:54:50.664 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:54:50.664 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:54:50.665 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:54:50.669 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:54:50.670 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:54:50.670 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:54:50.670 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:54:50.671 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:54:50.671 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:54:50.671 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:54:50.672 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:54:50.672 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:54:50.674 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:54:50.674 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:54:50.675 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:54:50.675 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:54:50.675 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:54:50.676 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:54:50.676 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:54:50.676 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:54:50.676 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:54:50.678 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:54:50.678 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:54:50.678 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:54:50.678 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:54:50.679 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:54:50.679 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:54:50.679 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:54:50.679 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:54:50.679 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:54:50.682 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:54:50.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:54:50.682 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:54:50.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:54:50.682 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:54:50.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:54:50.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:54:50.683 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:50.683 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:54:50.683 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:54:50.683 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:54:50.683 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:50.683 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:50.683 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:50.683 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:54:50.683 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:50.683 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:50.683 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:50.683 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:54:50.683 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:54:50.683 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:54:50.683 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:54:50.683 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:50.683 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:50.683 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:50.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:54:50.683 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:50.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:50.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:50.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:50.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:50.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:50.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:50.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:50.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:50.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:50.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:50.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:50.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:50.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:50.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:50.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:50.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:50.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:50.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:50.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:50.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:50.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:50.688 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:54:51.162 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:54:51.212 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:54:51.213 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:54:51.214 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:54:51.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:54:51.224 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:54:51.225 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:54:51.225 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:54:51.225 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:54:51.227 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:54:51.227 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:54:51.227 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:54:51.227 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:54:51.227 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:54:51.227 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:54:51.227 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:54:51.227 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:51.227 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:51.227 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:51.228 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:51.228 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:51.228 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:51.228 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:51.228 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:51.228 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:51.228 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:51.228 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:56.232 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:54:56.233 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:54:56.233 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:54:56.233 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:54:56.233 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:54:56.233 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:54:56.240 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:54:56.241 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:54:56.241 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:54:56.241 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:54:56.241 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:54:56.244 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:54:56.244 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:54:56.244 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:54:56.244 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:54:56.244 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:54:56.244 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:54:56.244 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:54:56.244 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:54:56.245 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:54:56.246 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:54:56.246 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:54:56.247 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:54:56.247 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:54:56.247 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:54:56.247 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:54:56.247 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:54:56.247 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:54:56.247 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:54:56.248 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:54:56.248 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:54:56.248 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:54:56.248 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:54:56.249 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:54:56.249 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:54:56.249 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:54:56.249 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:54:56.249 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:54:56.251 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:54:56.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:54:56.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:54:56.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:54:56.251 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:54:56.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:54:56.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:54:56.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:56.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:54:56.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:54:56.251 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:54:56.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:56.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:56.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:56.251 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:54:56.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:56.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:56.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:56.251 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:54:56.251 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:54:56.251 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:54:56.251 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:54:56.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:54:56.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:54:56.256 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:54:56.735 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:54:56.771 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:54:56.772 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:54:56.774 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:54:56.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:54:56.785 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:54:56.785 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:54:56.785 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:54:56.786 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:54:56.789 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:54:56.789 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:54:56.789 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:54:56.790 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:54:56.790 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:54:56.790 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:54:56.790 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:54:56.790 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:56.790 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:56.791 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:56.791 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:56.791 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:54:56.791 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:01.793 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:55:01.793 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:55:01.793 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:55:01.793 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:55:01.793 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:55:01.793 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:55:01.799 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:55:01.799 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:55:01.799 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:55:01.800 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:55:01.800 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:55:01.800 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:55:01.801 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:55:01.801 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:55:01.801 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:55:01.801 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:55:01.801 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:55:01.801 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:55:01.801 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:55:01.802 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:01.804 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:55:01.804 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:55:01.804 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:55:01.804 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:55:01.804 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:55:01.804 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:55:01.804 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:55:01.804 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:55:01.805 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:01.806 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:55:01.806 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:55:01.807 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:55:01.807 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:55:01.807 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:55:01.807 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:55:01.807 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:55:01.807 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:55:01.807 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:01.809 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:55:01.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:55:01.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:55:01.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:55:01.810 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:55:01.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:55:01.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:55:01.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:55:01.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:01.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:55:01.810 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:55:01.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:01.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:01.810 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:01.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:01.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:01.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:01.810 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:55:01.810 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:55:01.810 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:55:01.810 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:55:01.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:01.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:01.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:01.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:55:01.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:01.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:01.811 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:01.811 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:01.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:01.811 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:01.811 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:01.811 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:01.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:01.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:01.811 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:01.811 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:01.811 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:01.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:01.811 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:01.811 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:01.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:01.811 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:01.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:01.811 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:01.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:01.811 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:01.811 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:01.815 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:55:02.291 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:55:02.336 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:55:02.339 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:55:02.341 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:55:02.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:55:02.344 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:55:02.344 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:55:02.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:55:02.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:55:02.345 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:55:02.346 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:55:02.346 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:55:02.346 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:55:02.763 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:55:02.813 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:02.813 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:02.813 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:02.813 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:03.234 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:55:03.707 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:55:03.814 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:03.815 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:03.815 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:03.815 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:04.180 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:55:04.652 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:55:04.816 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:04.816 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:04.816 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:04.816 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:05.123 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:55:05.596 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:55:05.817 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:05.818 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:05.818 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:05.818 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:06.068 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:55:06.540 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:55:06.819 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:06.819 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:06.819 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:06.819 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:07.014 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:55:07.486 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:55:07.958 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:55:08.429 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:55:08.902 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:55:09.375 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:55:09.847 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:55:10.318 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:55:10.392 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:55:10.392 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:55:10.394 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:10.394 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:10.394 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:10.394 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:10.397 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:55:10.398 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:55:10.398 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:55:10.398 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:55:10.398 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:55:10.399 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:55:10.399 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:55:10.399 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:10.399 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:10.399 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:10.399 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:10.399 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:10.399 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:15.403 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:55:15.403 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:55:15.403 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:55:15.403 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:55:15.403 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:55:15.403 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:55:15.411 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:55:15.411 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:55:15.411 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:55:15.412 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:55:15.412 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:55:15.414 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:55:15.415 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:55:15.415 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:55:15.415 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:55:15.415 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:55:15.416 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:55:15.416 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:55:15.416 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:55:15.416 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:15.417 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:55:15.417 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:55:15.417 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:55:15.417 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:55:15.418 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:55:15.418 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:55:15.418 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:55:15.418 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:55:15.418 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:15.419 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:55:15.420 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:55:15.420 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:55:15.420 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:55:15.420 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:55:15.420 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:55:15.420 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:55:15.420 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:55:15.420 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:15.422 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:55:15.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:55:15.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:55:15.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:55:15.422 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:55:15.423 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:55:15.423 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:55:15.423 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:15.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:15.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:15.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:15.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:15.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:15.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:15.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:15.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:15.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:15.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:15.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:15.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:15.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:15.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:15.428 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:55:15.906 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:55:15.947 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:55:15.948 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:55:15.949 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:55:15.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:55:15.951 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:55:15.951 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:55:15.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:55:15.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:55:15.951 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:55:15.951 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:55:15.951 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:55:15.951 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:55:16.378 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:55:16.425 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:16.425 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:16.425 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:16.425 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:16.849 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:55:17.322 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:55:17.426 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:17.426 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:17.426 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:17.426 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:17.795 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:55:18.267 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:55:18.426 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:18.427 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:18.427 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:18.427 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:18.738 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:55:19.211 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:55:19.428 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:19.428 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:19.428 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:19.428 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:19.683 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:55:20.155 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:55:20.428 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:20.429 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:20.429 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:20.429 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:20.626 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:55:21.100 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:55:21.572 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:55:22.044 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:55:22.515 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:55:22.989 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:55:23.461 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:55:23.933 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:55:24.006 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:55:24.006 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:55:24.011 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:24.011 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:24.011 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:24.012 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:24.015 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:55:24.016 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:55:24.016 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:55:24.016 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:55:24.016 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:55:24.016 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:55:24.016 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:55:24.017 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1856 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:24.017 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1856 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:24.017 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1856 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:24.017 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1856 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:24.017 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1856 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:24.017 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1856 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:29.019 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:55:29.019 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:55:29.019 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:55:29.019 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:55:29.019 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:55:29.019 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:55:29.027 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:55:29.027 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:55:29.028 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:55:29.028 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:55:29.028 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:55:29.030 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:55:29.031 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:55:29.031 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:55:29.031 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:55:29.031 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:55:29.032 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:55:29.032 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:55:29.032 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:55:29.032 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:29.033 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:55:29.033 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:55:29.033 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:55:29.033 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:55:29.033 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:55:29.033 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:55:29.034 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:55:29.034 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:55:29.034 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:29.035 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:55:29.035 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:55:29.036 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:55:29.036 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:55:29.036 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:55:29.036 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:55:29.036 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:55:29.036 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:55:29.036 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:29.038 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:55:29.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:55:29.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:55:29.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:55:29.038 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:55:29.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:55:29.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:55:29.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:29.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:55:29.039 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:55:29.039 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:55:29.039 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:29.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:29.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:29.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:29.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:29.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:29.043 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:55:29.522 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:55:29.564 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:55:29.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:55:29.568 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:55:29.570 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:55:29.574 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:55:29.574 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:55:29.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:55:29.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:55:29.577 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:55:29.577 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:55:29.578 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:55:29.578 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:55:29.994 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:55:30.041 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:30.041 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:30.041 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:30.041 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:30.465 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:55:30.939 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:55:31.041 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:31.042 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:31.042 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:31.042 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:31.411 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:55:31.882 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:55:32.042 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:32.043 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:32.043 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:32.043 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:32.354 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:55:32.827 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:55:33.044 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:33.044 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:33.044 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:33.044 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:33.300 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:55:33.771 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:55:34.044 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:34.045 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:34.045 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:34.045 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:34.243 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:55:34.716 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:55:35.188 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:55:35.660 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:55:36.134 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:55:36.606 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:55:37.078 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:55:37.549 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:55:37.619 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:55:37.619 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:55:37.624 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:37.625 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:37.625 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:37.625 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:37.626 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:55:37.626 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:55:37.626 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:55:37.626 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:55:37.626 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:55:37.626 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:55:37.626 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:55:37.627 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:37.627 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:37.627 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:37.627 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:37.627 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:37.627 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:42.632 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:55:42.632 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:55:42.632 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:55:42.632 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:55:42.632 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:55:42.632 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:55:42.635 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:55:42.635 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:55:42.635 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:55:42.636 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:55:42.636 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:55:42.637 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:55:42.637 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:55:42.637 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:55:42.637 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:55:42.637 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:55:42.637 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:55:42.637 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:55:42.637 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:55:42.637 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:42.638 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:55:42.638 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:55:42.638 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:55:42.638 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:55:42.638 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:55:42.638 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:55:42.638 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:55:42.638 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:55:42.638 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:42.639 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:55:42.639 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:55:42.639 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:55:42.639 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:55:42.639 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:55:42.639 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:55:42.639 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:55:42.639 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:55:42.640 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:42.641 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:55:42.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:55:42.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:55:42.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:55:42.641 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:55:42.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:55:42.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:55:42.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:42.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:55:42.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:55:42.641 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:55:42.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:42.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:42.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:42.641 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:42.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:42.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:42.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:42.641 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:55:42.641 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:55:42.642 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:55:42.642 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:42.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:42.646 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:55:43.124 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:55:43.167 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:55:43.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:55:43.171 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:55:43.175 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:55:43.180 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:55:43.180 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:55:43.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:55:43.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:55:43.180 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:55:43.180 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:55:43.181 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:55:43.181 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:55:43.597 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:55:43.643 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:43.643 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:43.644 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:43.644 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:44.068 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:55:44.541 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:55:44.644 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:44.644 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:44.644 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:44.645 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:45.013 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:55:45.485 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:55:45.645 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:45.645 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:45.645 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:45.646 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:45.959 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:55:46.431 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:55:46.645 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:46.646 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:46.646 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:46.646 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:46.904 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:55:47.377 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:55:47.646 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:47.646 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:47.647 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:47.647 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:47.850 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:55:48.322 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:55:48.793 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:55:49.266 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:55:49.738 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:55:50.210 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:55:50.681 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:55:51.152 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:55:51.223 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:55:51.223 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:55:51.228 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:51.228 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:51.228 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:51.228 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:51.232 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:55:51.233 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:55:51.233 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:55:51.233 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:55:51.233 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:55:51.233 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:55:51.233 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:55:51.233 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:51.234 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:51.234 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:51.234 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:51.234 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:51.234 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:55:56.235 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:55:56.235 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:55:56.235 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:55:56.235 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:55:56.235 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:55:56.236 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:55:56.243 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:55:56.245 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:55:56.245 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:55:56.245 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:55:56.246 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:55:56.249 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:55:56.249 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:55:56.249 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:55:56.249 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:55:56.250 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:55:56.250 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:55:56.251 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:55:56.251 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:55:56.251 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:56.252 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:55:56.253 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:55:56.253 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:55:56.253 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:55:56.253 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:55:56.253 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:55:56.253 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:55:56.253 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:55:56.254 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:56.255 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:55:56.256 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:55:56.256 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:55:56.256 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:55:56.256 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:55:56.256 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:55:56.256 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:55:56.256 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:55:56.256 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:56.259 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:55:56.259 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:55:56.259 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:55:56.259 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:55:56.259 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:55:56.259 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:55:56.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:55:56.259 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:55:56.259 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:55:56.259 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:55:56.259 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:56.259 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:56.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:56.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:56.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:56.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:56.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:56.260 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:55:56.260 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:55:56.260 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:55:56.260 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:55:56.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:56.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:56.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:56.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:55:56.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:56.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:56.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:56.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:56.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:56.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:56.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:56.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:56.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:56.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:56.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:56.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:56.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:56.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:56.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:55:56.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:56.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:56.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:56.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:55:56.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:56.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:55:56.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:56.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:55:56.264 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:55:56.743 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:55:56.789 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:55:56.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:55:56.792 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:55:56.794 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:55:56.798 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:55:56.798 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:55:56.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:55:56.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:55:56.799 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:55:56.799 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:55:56.799 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:55:56.799 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:55:57.215 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:55:57.262 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:57.262 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:57.262 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:57.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:57.687 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:55:58.160 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:55:58.262 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:58.263 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:58.263 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:58.263 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:58.632 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:55:59.104 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:55:59.264 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:55:59.264 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:55:59.264 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:55:59.264 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:55:59.575 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:56:00.046 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:56:00.265 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:56:00.266 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:56:00.266 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:56:00.266 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:56:00.519 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:56:00.992 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:56:01.267 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:56:01.267 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:56:01.267 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:56:01.267 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:56:01.464 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:56:01.935 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:56:02.408 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:56:02.880 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:56:03.352 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:56:03.823 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:56:04.297 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:56:04.769 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:56:04.842 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:56:04.842 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:56:04.846 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:56:04.846 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:56:04.846 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:56:04.846 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:56:04.847 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:56:04.847 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:56:04.847 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:56:04.847 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:56:04.847 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:56:04.847 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:56:04.847 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:56:09.852 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:56:09.852 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:56:09.852 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:56:09.852 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:56:09.852 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:56:09.852 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:56:09.859 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:56:09.860 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:56:09.860 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:56:09.860 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:56:09.860 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:56:09.863 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:56:09.863 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:56:09.864 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:56:09.864 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:56:09.864 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:56:09.864 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:56:09.865 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:56:09.865 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:56:09.865 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:56:09.868 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:56:09.868 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:56:09.869 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:56:09.869 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:56:09.869 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:56:09.870 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:56:09.870 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:56:09.870 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:56:09.871 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:56:09.872 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:56:09.873 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:56:09.873 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:56:09.873 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:56:09.873 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:56:09.873 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:56:09.873 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:56:09.873 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:56:09.873 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:56:09.878 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:56:09.878 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:56:09.878 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:56:09.878 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:56:09.878 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:56:09.878 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:56:09.878 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:56:09.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:56:09.878 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:56:09.878 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:56:09.878 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:56:09.878 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:56:09.878 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:56:09.878 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:56:09.878 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:56:09.878 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:56:09.878 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:56:09.879 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:56:09.879 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:56:09.879 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:56:09.879 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:56:09.879 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:56:09.879 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:56:09.879 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:56:09.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:56:09.879 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:56:09.879 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:56:09.879 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:56:09.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:56:09.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:56:09.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:56:09.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:56:09.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:56:09.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:56:09.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:56:09.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:56:09.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:56:09.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:56:09.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:56:09.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:56:09.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:56:09.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:56:09.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:56:09.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:56:09.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:56:09.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:56:09.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:56:09.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:56:09.883 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:56:10.360 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:56:10.407 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:56:10.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:56:10.410 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:56:10.412 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:56:10.415 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:56:10.415 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:56:10.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:56:10.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:56:10.417 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:56:10.417 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:56:10.417 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:56:10.417 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:56:10.832 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:56:10.882 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:56:10.882 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:56:10.883 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:56:10.883 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:56:11.303 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:56:11.777 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:56:11.884 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:56:11.884 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:56:11.884 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:56:11.885 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:56:12.249 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:56:12.721 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:56:12.885 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:56:12.885 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:56:12.885 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:56:12.885 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:56:13.191 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:56:13.662 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:56:13.887 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:56:13.887 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:56:13.887 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:56:13.887 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:56:14.133 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:56:14.607 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:56:14.888 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:56:14.888 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:56:14.888 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:56:14.889 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:56:15.079 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:56:15.551 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:56:16.022 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:56:16.496 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:56:16.968 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:56:17.440 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:56:17.911 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:56:18.384 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:56:18.857 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:56:19.329 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:56:19.800 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:56:20.273 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:56:20.745 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:56:21.217 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:56:21.688 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:56:22.162 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:56:22.634 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:56:23.105 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:56:23.576 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:56:24.050 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:56:24.522 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:56:24.994 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:56:25.465 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:56:25.938 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:56:26.411 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:56:26.468 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:56:26.469 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:56:26.473 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:56:26.474 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:56:26.474 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:56:26.474 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:56:26.477 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:56:26.478 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:56:26.478 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:56:26.478 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:56:26.478 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:56:26.478 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:56:26.478 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:56:26.479 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3586 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:56:26.479 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3586 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:56:26.479 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3586 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:56:26.479 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3586 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:56:26.479 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3586 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:56:26.479 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3586 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:56:31.481 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:56:31.481 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:56:31.481 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:56:31.481 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:56:31.481 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:56:31.481 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:56:31.488 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:56:31.489 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:56:31.489 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:56:31.490 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:56:31.490 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:56:31.492 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:56:31.493 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:56:31.493 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:56:31.493 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:56:31.493 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:56:31.494 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:56:31.494 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:56:31.494 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:56:31.494 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:56:31.495 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:56:31.495 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:56:31.495 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:56:31.495 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:56:31.496 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:56:31.496 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:56:31.496 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:56:31.496 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:56:31.496 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:56:31.498 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:56:31.498 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:56:31.498 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:56:31.498 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:56:31.498 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:56:31.498 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:56:31.498 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:56:31.498 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:56:31.498 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:56:31.501 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:56:31.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:56:31.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:56:31.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:56:31.502 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:56:31.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:56:31.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:56:31.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:56:31.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:56:31.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:56:31.502 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:56:31.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:56:31.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:56:31.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:56:31.502 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:56:31.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:56:31.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:56:31.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:56:31.502 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:56:31.502 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:56:31.502 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:56:31.502 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:56:31.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:56:31.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:56:31.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:56:31.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:56:31.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:56:31.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:56:31.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:56:31.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:56:31.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:56:31.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:56:31.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:56:31.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:56:31.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:56:31.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:56:31.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:56:31.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:56:31.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:56:31.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:56:31.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:56:31.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:56:31.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:56:31.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:56:31.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:56:31.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:56:31.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:56:31.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:56:31.507 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:56:31.983 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:56:32.030 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:56:32.032 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:56:32.034 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:56:32.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:56:32.046 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:56:32.046 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:56:32.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:56:32.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:56:32.046 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:56:32.047 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:56:32.047 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:56:32.047 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:56:32.454 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:56:32.505 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:56:32.505 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:56:32.505 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:56:32.506 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:56:32.926 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:56:33.399 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:56:33.506 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:56:33.507 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:56:33.507 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:56:33.507 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:56:33.871 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:56:34.343 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:56:34.508 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:56:34.508 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:56:34.508 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:56:34.508 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:56:34.814 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:56:35.287 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:56:35.509 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:56:35.509 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:56:35.510 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:56:35.510 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:56:35.760 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:56:36.232 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:56:36.511 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:56:36.511 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:56:36.511 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:56:36.511 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:56:36.705 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:56:37.178 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:56:37.649 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:56:38.120 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:56:38.594 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:56:39.066 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:56:39.538 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:56:40.009 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:56:40.085 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:56:40.085 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:56:40.096 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:56:40.096 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:56:40.096 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:56:40.096 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:56:40.100 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:56:40.100 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:56:40.101 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:56:40.101 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:56:40.101 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:56:40.101 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:56:40.101 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:56:40.101 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1858 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:56:40.101 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1858 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:56:40.101 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1858 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:56:40.102 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1858 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:56:40.102 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1858 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:56:40.102 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1858 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:56:45.103 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:56:45.103 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:56:45.103 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:56:45.103 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:56:45.103 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:56:45.103 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:56:45.111 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:56:45.112 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:56:45.112 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:56:45.113 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:56:45.113 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:56:45.115 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:56:45.115 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:56:45.116 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:56:45.116 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:56:45.116 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:56:45.116 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:56:45.117 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:56:45.117 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:56:45.117 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:56:45.118 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:56:45.118 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:56:45.118 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:56:45.118 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:56:45.118 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:56:45.118 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:56:45.118 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:56:45.118 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:56:45.119 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:56:45.120 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:56:45.120 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:56:45.120 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:56:45.120 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:56:45.120 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:56:45.121 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:56:45.121 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:56:45.121 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:56:45.121 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:56:45.123 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:56:45.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:56:45.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:56:45.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:56:45.123 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:56:45.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:56:45.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:56:45.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:56:45.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:56:45.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:56:45.123 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:56:45.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:56:45.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:56:45.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:56:45.123 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:56:45.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:56:45.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:56:45.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:56:45.123 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:56:45.123 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:56:45.123 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:56:45.124 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:56:45.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:56:45.128 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:56:45.601 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:56:45.650 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:56:45.652 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:56:45.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:56:45.654 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:56:45.658 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:56:45.658 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:56:45.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:56:45.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:56:45.658 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:56:45.658 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:56:45.658 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:56:45.658 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:56:46.073 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:56:46.126 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:56:46.126 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:56:46.126 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:56:46.127 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:56:46.544 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:56:47.018 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:56:47.127 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:56:47.127 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:56:47.127 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:56:47.128 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:56:47.490 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:56:47.962 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:56:48.128 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:56:48.128 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:56:48.129 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:56:48.129 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:56:48.433 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:56:48.907 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:56:49.129 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:56:49.129 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:56:49.130 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:56:49.130 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:56:49.379 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:56:49.851 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:56:50.131 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:56:50.131 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:56:50.131 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:56:50.131 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:56:50.322 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:56:50.795 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:56:51.268 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:56:51.740 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:56:52.211 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:56:52.682 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:56:53.156 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:56:53.627 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:56:54.099 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:56:54.572 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:56:55.044 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:56:55.516 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:56:55.987 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:56:56.458 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:56:56.931 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:56:57.404 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:56:57.876 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:56:58.347 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:56:58.820 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:56:59.293 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:56:59.765 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:57:00.239 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:57:00.710 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:57:01.182 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:57:01.653 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:57:01.709 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:57:01.710 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:57:01.726 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:57:01.726 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:57:01.726 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:57:01.726 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:57:01.730 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:57:01.730 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:57:01.730 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:57:01.730 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:57:01.730 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:57:01.730 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:57:01.730 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:57:06.734 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:57:06.734 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:57:06.734 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:57:06.734 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:57:06.734 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:57:06.734 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:57:06.741 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:57:06.743 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:57:06.743 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:06.743 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:57:06.743 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:57:06.748 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:57:06.748 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:57:06.749 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:57:06.749 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:06.749 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:57:06.749 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:57:06.749 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:57:06.749 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:57:06.750 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:57:06.753 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:57:06.753 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:57:06.753 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:57:06.753 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:06.754 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:57:06.754 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:57:06.754 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:57:06.754 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:57:06.754 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:57:06.757 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:57:06.757 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:57:06.757 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:57:06.757 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:06.757 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:57:06.757 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:57:06.758 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:57:06.758 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:57:06.758 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:57:06.762 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:57:06.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:57:06.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:57:06.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:57:06.762 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:57:06.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:57:06.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:57:06.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:06.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:57:06.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:57:06.762 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:57:06.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:06.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:06.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:06.762 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:57:06.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:06.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:06.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:06.763 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:57:06.763 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:57:06.763 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:57:06.763 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:57:06.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:06.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:06.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:06.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:57:06.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:06.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:06.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:06.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:06.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:06.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:06.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:06.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:06.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:06.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:06.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:06.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:06.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:06.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:06.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:06.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:06.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:06.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:06.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:06.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:06.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:06.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:06.767 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:57:07.244 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:57:07.285 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:57:07.287 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:57:07.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:57:07.288 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:57:07.307 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:57:07.307 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:57:07.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:57:07.323 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:57:07.323 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:57:07.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:57:07.323 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:57:07.325 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:57:07.325 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:57:07.325 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:57:07.325 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:57:07.326 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:57:07.326 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:57:07.326 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:57:07.326 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:57:07.326 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:57:07.326 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:57:07.326 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:57:07.326 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:57:07.326 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:57:12.330 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:57:12.330 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:57:12.331 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:57:12.331 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:57:12.331 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:57:12.331 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:57:12.338 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:57:12.338 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:57:12.338 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:12.339 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:57:12.339 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:57:12.341 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:57:12.341 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:57:12.342 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:57:12.342 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:12.342 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:57:12.343 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:57:12.343 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:57:12.343 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:57:12.343 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:57:12.345 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:57:12.345 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:57:12.346 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:57:12.346 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:12.346 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:57:12.346 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:57:12.346 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:57:12.346 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:57:12.347 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:57:12.349 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:57:12.349 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:57:12.349 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:57:12.349 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:12.350 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:57:12.350 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:57:12.350 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:57:12.350 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:57:12.350 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:57:12.354 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:57:12.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:57:12.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:57:12.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:57:12.355 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:57:12.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:57:12.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:57:12.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:12.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:57:12.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:57:12.355 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:57:12.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:12.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:12.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:12.355 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:57:12.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:12.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:12.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:12.356 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:57:12.356 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:57:12.356 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:57:12.356 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:57:12.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:12.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:12.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:12.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:57:12.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:12.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:12.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:12.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:12.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:12.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:12.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:12.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:12.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:12.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:12.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:12.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:12.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:12.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:12.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:12.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:12.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:12.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:12.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:12.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:12.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:12.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:12.361 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:57:12.837 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:57:12.885 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:57:12.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:57:12.888 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:57:12.891 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:57:12.915 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:57:12.916 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:57:12.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:57:12.951 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:57:12.951 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:57:12.952 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:57:12.952 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:57:12.953 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:57:12.953 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:57:12.953 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:57:12.953 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:57:12.953 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:57:12.953 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:57:12.953 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:57:12.953 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=129 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:57:12.953 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=129 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:57:12.953 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=129 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:57:12.953 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=129 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:57:12.953 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=129 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:57:12.953 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=129 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:57:12.953 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=129 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:57:17.959 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:57:17.959 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:57:17.959 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:57:17.959 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:57:17.959 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:57:17.959 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:57:17.963 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:57:17.963 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:57:17.963 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:17.964 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:57:17.964 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:57:17.966 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:57:17.966 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:57:17.966 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:57:17.966 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:17.966 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:57:17.967 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:57:17.967 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:57:17.967 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:57:17.967 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:57:17.968 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:57:17.968 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:57:17.968 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:57:17.968 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:17.968 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:57:17.968 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:57:17.968 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:57:17.968 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:57:17.969 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:57:17.970 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:57:17.970 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:57:17.970 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:57:17.970 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:17.970 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:57:17.970 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:57:17.970 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:57:17.970 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:57:17.970 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:57:17.972 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:57:17.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:57:17.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:57:17.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:57:17.972 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:57:17.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:57:17.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:57:17.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:57:17.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:57:17.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:17.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:17.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:17.972 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:57:17.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:17.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:17.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:17.972 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:57:17.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:57:17.973 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:57:17.973 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:57:17.973 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:17.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:17.977 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:57:18.456 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:57:18.495 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:57:18.497 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:57:18.500 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:57:18.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:57:18.524 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:57:18.524 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:57:18.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:57:18.561 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:57:18.561 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:57:18.561 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:57:18.561 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:57:18.561 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:57:18.561 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:57:18.561 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:57:18.561 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:57:18.562 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:57:18.562 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:57:18.562 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:57:23.567 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:57:23.568 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:57:23.568 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:57:23.568 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:57:23.568 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:57:23.568 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:57:23.573 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:57:23.574 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:57:23.574 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:23.575 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:57:23.575 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:57:23.577 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:57:23.578 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:57:23.578 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:57:23.578 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:23.578 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:57:23.579 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:57:23.579 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:57:23.579 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:57:23.579 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:57:23.580 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:57:23.580 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:57:23.580 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:57:23.580 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:23.581 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:57:23.581 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:57:23.581 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:57:23.581 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:57:23.581 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:57:23.583 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:57:23.583 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:57:23.583 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:57:23.583 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:23.583 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:57:23.583 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:57:23.583 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:57:23.583 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:57:23.583 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:57:23.585 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:57:23.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:57:23.586 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:57:23.586 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:57:23.586 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:57:23.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:57:23.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:57:23.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:23.586 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:57:23.586 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:57:23.586 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:57:23.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:23.586 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:23.586 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:23.586 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:57:23.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:23.586 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:23.586 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:23.586 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:57:23.586 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:57:23.586 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:57:23.586 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:57:23.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:23.586 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:23.586 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:23.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:57:23.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:23.586 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:23.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:23.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:23.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:23.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:23.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:23.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:23.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:23.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:23.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:23.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:23.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:23.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:23.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:23.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:23.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:23.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:23.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:23.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:23.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:23.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:23.591 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:57:24.067 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:57:24.112 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:57:24.114 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:57:24.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:57:24.116 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:57:24.141 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:57:24.141 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:57:24.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:57:24.156 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:57:24.156 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:57:24.156 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:57:24.156 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:57:24.159 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:57:24.159 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:57:24.159 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:57:24.159 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:57:24.159 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:57:24.159 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:57:24.159 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:57:24.159 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:57:29.163 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:57:29.163 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:57:29.163 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:57:29.163 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:57:29.163 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:57:29.163 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:57:29.171 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:57:29.172 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:57:29.172 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:29.172 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:57:29.173 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:57:29.176 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:57:29.176 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:57:29.176 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:57:29.176 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:29.177 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:57:29.177 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:57:29.178 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:57:29.178 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:57:29.178 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:57:29.179 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:57:29.180 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:57:29.180 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:57:29.180 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:29.180 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:57:29.180 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:57:29.180 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:57:29.180 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:57:29.180 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:57:29.183 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:57:29.183 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:57:29.183 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:57:29.183 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:29.183 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:57:29.183 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:57:29.183 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:57:29.183 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:57:29.183 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:57:29.186 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:57:29.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:57:29.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:57:29.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:57:29.186 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:57:29.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:57:29.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:57:29.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:29.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:57:29.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:57:29.187 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:57:29.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:29.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:29.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:29.187 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:57:29.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:29.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:29.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:29.187 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:57:29.187 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:57:29.187 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:57:29.187 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:57:29.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:29.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:29.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:29.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:57:29.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:29.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:29.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:29.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:29.188 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:29.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:29.188 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:29.188 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:29.188 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:29.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:29.188 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:29.188 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:29.188 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:29.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:29.188 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:29.188 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:29.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:29.188 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:29.188 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:29.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:29.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:29.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:29.192 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:57:29.668 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:57:29.711 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:57:29.712 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:57:29.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:57:29.713 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:57:29.733 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:57:29.733 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:57:29.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:57:29.750 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:57:29.750 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:57:29.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:57:29.754 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:57:29.754 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:57:29.754 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:57:29.754 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:57:29.755 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:57:29.755 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:57:29.755 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:57:29.755 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:57:29.755 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:57:29.755 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:57:29.755 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:57:34.761 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:57:34.761 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:57:34.761 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:57:34.761 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:57:34.761 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:57:34.761 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:57:34.768 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:57:34.769 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:57:34.769 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:34.770 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:57:34.770 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:57:34.773 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:57:34.774 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:57:34.774 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:57:34.774 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:34.774 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:57:34.774 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:57:34.774 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:57:34.775 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:57:34.775 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:57:34.778 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:57:34.778 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:57:34.778 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:57:34.779 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:34.779 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:57:34.779 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:57:34.779 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:57:34.780 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:57:34.780 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:57:34.781 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:57:34.781 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:57:34.781 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:57:34.781 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:34.782 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:57:34.782 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:57:34.782 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:57:34.782 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:57:34.782 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:57:34.785 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:57:34.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:57:34.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:57:34.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:57:34.786 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:57:34.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:57:34.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:57:34.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:34.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:57:34.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:57:34.786 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:57:34.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:34.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:34.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:34.786 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:57:34.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:34.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:34.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:34.787 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:57:34.787 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:57:34.787 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:57:34.787 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:57:34.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:34.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:34.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:34.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:57:34.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:34.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:34.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:34.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:34.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:34.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:34.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:34.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:34.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:34.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:34.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:34.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:34.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:34.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:34.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:34.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:34.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:34.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:34.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:34.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:34.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:34.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:34.792 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:57:35.268 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:57:35.315 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:57:35.317 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:57:35.319 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:57:35.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:57:35.337 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:57:35.337 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:57:35.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:57:35.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:57:35.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:57:35.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:57:35.357 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:57:35.357 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:57:35.357 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:57:35.357 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:57:35.357 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:57:35.357 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:57:35.358 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:57:35.358 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:57:35.358 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:57:35.358 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:57:35.358 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:57:40.364 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:57:40.364 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:57:40.364 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:57:40.364 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:57:40.364 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:57:40.364 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:57:40.372 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:57:40.373 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:57:40.373 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:40.373 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:57:40.373 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:57:40.376 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:57:40.377 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:57:40.377 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:57:40.377 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:40.377 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:57:40.378 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:57:40.378 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:57:40.378 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:57:40.378 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:57:40.379 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:57:40.379 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:57:40.379 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:57:40.379 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:40.380 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:57:40.380 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:57:40.380 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:57:40.380 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:57:40.380 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:57:40.382 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:57:40.382 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:57:40.382 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:57:40.382 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:57:40.382 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:57:40.382 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:57:40.382 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:57:40.382 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:57:40.382 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:57:40.385 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:57:40.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:57:40.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:57:40.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:57:40.385 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:57:40.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:57:40.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:57:40.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:40.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:57:40.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:57:40.385 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:57:40.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:40.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:40.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:40.385 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:57:40.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:40.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:40.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:40.385 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:57:40.385 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:57:40.385 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:57:40.385 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:57:40.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:40.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:40.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:40.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:57:40.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:40.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:40.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:40.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:40.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:40.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:40.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:40.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:40.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:40.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:40.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:40.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:40.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:40.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:40.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:57:40.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:40.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:40.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:40.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:40.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:57:40.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:57:40.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:57:40.390 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:57:40.867 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:57:40.909 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:57:40.911 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:57:40.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:57:40.914 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:57:40.921 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:57:40.921 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:57:40.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:57:40.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:57:40.923 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:57:40.923 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:57:40.923 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:57:40.923 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:57:41.339 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:57:41.388 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:57:41.388 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:57:41.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:57:41.388 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:57:41.812 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:57:42.285 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:57:42.389 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:57:42.389 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:57:42.389 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:57:42.390 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:57:42.757 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:57:43.228 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:57:43.391 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:57:43.391 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:57:43.391 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:57:43.391 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:57:43.702 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:57:44.174 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:57:44.392 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:57:44.392 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:57:44.392 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:57:44.392 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:57:44.646 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:57:45.116 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:57:45.392 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:57:45.393 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:57:45.393 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:57:45.393 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:57:45.590 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:57:46.062 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:57:46.535 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:57:47.007 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:57:47.480 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:57:47.952 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:57:48.423 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:57:48.896 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:57:49.369 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 01:57:49.840 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 01:57:50.312 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 01:57:50.785 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 01:57:51.258 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 01:57:51.730 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 01:57:52.203 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 01:57:52.676 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 01:57:53.148 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 01:57:53.619 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 01:57:54.092 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 01:57:54.565 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 01:57:55.037 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 01:57:55.508 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 01:57:55.981 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 01:57:56.454 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 01:57:56.926 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 01:57:57.397 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 01:57:57.868 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 01:57:58.341 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 01:57:58.814 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 01:57:59.286 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 01:57:59.757 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 01:58:00.230 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 01:58:00.703 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 01:58:01.174 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 01:58:01.646 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 01:58:02.119 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 01:58:02.591 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 01:58:03.063 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 01:58:03.535 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 01:58:04.008 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 01:58:04.480 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 01:58:04.952 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 01:58:05.423 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 01:58:05.896 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 01:58:06.369 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 01:58:06.841 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 01:58:07.314 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 01:58:07.787 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 01:58:08.259 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 01:58:08.730 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 01:58:09.203 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 01:58:09.676 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 01:58:10.148 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 01:58:10.619 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 01:58:11.092 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 01:58:11.565 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 01:58:12.037 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 01:58:12.508 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 01:58:12.981 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 01:58:13.453 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 01:58:13.925 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 01:58:14.396 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 01:58:14.407 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:58:14.407 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:58:14.413 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:14.413 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:14.413 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:14.413 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:14.417 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:58:14.417 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:58:14.417 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:58:14.418 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:58:14.418 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:58:14.418 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:58:14.418 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:58:14.418 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7350 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:14.418 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7350 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:14.418 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7350 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:14.419 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7350 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:14.419 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7350 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:14.419 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7351 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:14.419 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7351 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:14.419 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7351 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:14.419 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7351 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:14.419 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7351 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:14.419 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7351 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:14.419 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7351 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:14.419 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7351 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:19.420 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:58:19.420 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:58:19.420 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:58:19.420 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:58:19.420 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:58:19.420 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:58:19.428 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:58:19.430 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:58:19.430 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:58:19.430 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:58:19.430 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:58:19.433 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:58:19.433 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:58:19.434 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:58:19.434 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:58:19.434 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:58:19.435 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:58:19.435 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:58:19.435 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:58:19.436 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:19.437 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:58:19.438 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:58:19.438 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:58:19.438 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:58:19.438 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:58:19.439 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:58:19.439 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:58:19.439 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:58:19.439 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:19.442 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:58:19.442 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:58:19.442 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:58:19.442 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:58:19.442 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:58:19.443 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:58:19.443 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:58:19.443 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:58:19.443 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:19.447 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:58:19.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:58:19.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:58:19.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:58:19.447 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:58:19.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:58:19.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:58:19.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:19.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:58:19.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:58:19.448 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:58:19.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:19.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:19.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:19.448 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:19.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:19.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:19.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:19.448 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:58:19.448 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:58:19.448 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:58:19.448 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:58:19.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:19.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:19.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:19.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:58:19.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:19.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:19.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:19.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:19.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:19.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:19.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:19.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:19.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:19.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:19.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:19.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:19.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:19.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:19.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:19.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:19.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:19.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:19.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:19.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:19.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:19.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:19.453 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:58:19.931 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:58:19.977 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:58:19.979 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:58:19.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:58:19.982 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:58:20.403 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:58:20.453 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:20.453 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:20.453 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:20.454 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:20.879 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:58:21.350 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:58:21.455 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:21.455 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:21.455 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:21.455 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:21.824 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:58:22.297 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:58:22.456 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:22.456 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:22.456 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:22.456 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:22.768 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:58:22.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:58:22.999 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:22.999 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:22.999 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:22.999 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:23.000 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:58:23.000 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:58:23.000 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:58:23.000 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:58:23.000 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:58:23.000 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:58:23.000 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:58:28.006 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:58:28.006 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:58:28.006 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:58:28.006 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:58:28.006 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:58:28.006 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:58:28.011 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:58:28.012 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:58:28.012 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:58:28.012 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:58:28.013 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:58:28.015 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:58:28.015 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:58:28.015 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:58:28.015 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:58:28.016 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:58:28.016 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:58:28.016 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:58:28.016 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:58:28.017 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:28.018 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:58:28.018 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:58:28.019 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:58:28.019 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:58:28.019 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:58:28.019 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:58:28.019 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:58:28.019 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:58:28.019 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:28.022 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:58:28.022 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:58:28.023 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:58:28.023 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:58:28.023 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:58:28.023 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:58:28.023 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:58:28.023 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:58:28.023 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:28.027 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:58:28.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:58:28.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:58:28.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:58:28.027 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:58:28.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:58:28.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:58:28.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:28.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:58:28.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:58:28.027 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:58:28.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:28.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:28.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:28.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:28.028 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:28.028 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:28.028 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:28.028 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:58:28.028 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:58:28.028 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:58:28.028 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:58:28.028 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:28.028 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:28.028 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:28.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:58:28.028 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:28.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:28.028 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:28.028 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:28.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:28.028 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:28.028 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:28.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:28.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:28.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:28.029 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:28.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:28.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:28.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:28.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:28.029 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:28.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:28.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:28.029 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:28.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:28.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:28.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:28.033 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:58:28.509 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:58:28.557 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:58:28.559 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:58:28.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:58:28.561 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:58:28.981 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:58:29.032 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:29.032 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:29.032 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:29.032 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:29.456 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:58:29.928 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:58:30.033 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:30.033 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:30.033 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:30.034 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:30.399 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:58:30.872 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:58:31.034 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:31.035 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:31.035 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:31.035 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:31.345 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:58:31.815 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:58:32.036 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:32.036 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:32.036 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:32.037 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:32.287 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:58:32.759 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:58:33.037 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:33.038 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:33.038 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:33.038 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:33.232 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:58:33.705 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:58:34.177 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:58:34.575 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:34.575 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:34.575 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:34.575 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:34.576 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:58:34.576 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:58:34.576 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:58:34.576 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:58:34.576 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:58:34.576 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:58:34.576 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:58:39.581 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:58:39.581 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:58:39.581 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:58:39.581 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:58:39.581 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:58:39.581 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:58:39.592 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:58:39.593 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:58:39.593 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:58:39.594 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:58:39.594 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:58:39.597 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:58:39.597 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:58:39.598 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:58:39.598 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:58:39.598 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:58:39.598 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:58:39.599 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:58:39.599 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:58:39.599 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:39.602 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:58:39.602 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:58:39.602 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:58:39.602 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:58:39.602 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:58:39.603 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:58:39.603 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:58:39.603 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:58:39.603 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:39.605 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:58:39.605 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:58:39.605 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:58:39.605 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:58:39.605 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:58:39.605 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:58:39.605 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:58:39.605 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:58:39.605 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:39.608 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:58:39.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:58:39.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:58:39.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:58:39.608 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:58:39.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:58:39.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:58:39.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:58:39.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:39.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:58:39.608 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:58:39.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:39.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:39.608 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:39.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:39.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:39.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:58:39.609 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:58:39.609 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:58:39.609 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:39.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:39.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:39.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:39.613 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:58:40.090 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:58:40.136 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:58:40.138 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:58:40.140 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:58:40.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:58:40.562 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:58:40.612 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:40.612 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:40.612 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:40.612 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:41.037 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:58:41.509 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:58:41.613 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:41.614 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:41.614 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:41.614 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:41.985 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:58:42.457 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:58:42.615 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:42.615 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:42.615 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:42.615 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:42.932 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:58:43.404 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:58:43.616 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:43.616 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:43.617 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:43.617 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:43.875 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:58:44.350 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:58:44.618 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:44.618 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:44.618 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:44.618 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:44.822 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:58:45.293 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:58:45.763 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:58:46.154 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:46.155 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:46.155 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:46.155 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:46.157 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:58:46.158 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:58:46.158 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:58:46.158 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:58:46.158 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:58:46.158 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:58:46.158 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:58:46.158 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1413 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:46.158 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1413 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:46.158 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1413 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:46.158 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1413 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:46.158 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1413 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:46.158 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1413 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:51.161 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:58:51.161 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:58:51.161 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:58:51.161 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:58:51.161 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:58:51.161 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:58:51.168 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:58:51.170 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:58:51.170 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:58:51.170 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:58:51.170 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:58:51.174 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:58:51.174 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:58:51.175 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:58:51.175 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:58:51.175 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:58:51.175 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:58:51.175 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:58:51.175 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:58:51.176 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:51.178 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:58:51.179 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:58:51.179 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:58:51.179 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:58:51.180 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:58:51.180 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:58:51.180 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:58:51.180 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:58:51.181 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:51.182 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:58:51.182 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:58:51.182 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:58:51.182 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:58:51.182 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:58:51.182 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:58:51.182 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:58:51.182 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:58:51.183 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:51.186 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:58:51.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:58:51.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:58:51.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:58:51.186 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:58:51.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:58:51.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:58:51.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:51.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:58:51.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:58:51.186 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:58:51.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:51.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:51.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:51.186 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:51.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:51.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:51.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:51.186 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:58:51.186 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:58:51.186 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:58:51.187 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:51.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:58:51.191 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:58:51.670 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:58:51.712 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:58:51.714 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:58:51.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:58:51.717 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:58:52.142 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:58:52.190 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:52.190 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:52.190 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:52.191 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:52.617 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:58:53.088 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:58:53.191 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:53.206 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:53.206 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:53.206 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:53.564 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:58:54.036 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:58:54.206 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:54.207 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:54.207 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:54.207 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:54.511 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:58:54.983 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:58:55.208 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:55.208 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:55.208 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:55.208 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:55.458 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:58:55.930 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:58:56.209 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:56.210 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:56.210 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:56.210 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:56.405 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:58:56.877 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:58:57.353 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:58:57.731 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:58:57.731 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:58:57.731 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:58:57.731 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:58:57.735 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:58:57.736 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:58:57.736 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:58:57.736 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:58:57.736 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:58:57.736 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:58:57.737 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:58:57.737 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1410 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:57.737 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1410 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:57.737 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1410 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:57.737 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1410 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:57.737 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1410 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:57.737 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1410 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:58:57.737 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1410 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:59:02.739 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:59:02.739 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:59:02.739 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:59:02.739 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:59:02.739 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:59:02.740 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:59:02.745 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:59:02.745 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:59:02.745 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:02.745 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:59:02.745 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:59:02.746 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:59:02.746 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:59:02.747 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:59:02.747 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:02.747 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:59:02.747 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:59:02.747 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:59:02.747 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:59:02.747 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:02.748 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:59:02.749 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:59:02.749 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:59:02.749 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:02.749 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:59:02.749 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:59:02.749 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:59:02.749 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:59:02.749 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:02.750 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:59:02.750 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:59:02.750 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:59:02.750 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:02.750 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:59:02.750 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:59:02.750 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:59:02.750 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:59:02.750 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:02.752 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:59:02.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:59:02.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:59:02.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:59:02.752 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:59:02.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:59:02.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:59:02.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:59:02.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:59:02.752 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:59:02.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:02.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:02.752 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:02.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:02.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:02.752 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:59:02.752 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:59:02.752 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:59:02.752 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:59:02.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:02.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:02.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:02.757 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:59:03.235 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:59:03.279 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:59:03.281 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:59:03.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:59:03.283 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:59:03.712 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:59:03.756 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:03.756 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:03.756 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:03.756 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:04.183 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:59:04.654 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:59:04.757 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:04.758 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:04.758 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:04.758 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:05.128 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:59:05.601 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:59:05.759 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:05.759 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:05.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:05.759 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:06.072 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:59:06.543 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:59:06.760 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:06.760 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:06.760 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:06.761 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:07.014 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:59:07.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:59:07.489 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 01:59:07.762 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:07.763 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:07.763 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:07.763 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:07.961 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 01:59:08.436 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 01:59:08.908 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 01:59:09.383 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 01:59:09.855 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 01:59:10.330 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 01:59:10.800 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 01:59:11.273 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 01:59:11.308 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:11.308 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:11.308 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:11.308 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:11.308 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:59:11.308 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:59:11.308 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:59:11.308 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:59:11.308 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:59:11.309 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:59:11.309 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:59:16.319 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:59:16.319 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:59:16.320 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:59:16.320 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:59:16.320 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:59:16.320 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:59:16.328 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:59:16.329 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:59:16.329 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:16.329 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:59:16.329 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:59:16.331 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:59:16.331 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:59:16.331 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:59:16.332 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:16.332 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:59:16.332 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:59:16.332 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:59:16.332 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:59:16.333 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:16.334 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:59:16.334 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:59:16.334 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:59:16.334 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:16.334 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:59:16.334 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:59:16.334 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:59:16.334 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:59:16.334 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:16.336 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:59:16.336 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:59:16.337 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:59:16.337 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:16.337 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:59:16.337 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:59:16.337 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:59:16.337 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:59:16.337 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:16.340 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:59:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:59:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:59:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:59:16.340 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:59:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:59:16.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:59:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:59:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:59:16.340 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:59:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:16.340 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:16.341 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:59:16.341 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:59:16.341 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:59:16.341 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:59:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:16.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:59:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:16.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:16.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:16.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:16.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:16.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:16.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:16.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:16.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:16.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:16.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:16.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:16.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:16.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:16.345 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:59:16.821 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:59:16.867 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:59:16.869 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:59:16.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:59:16.871 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:59:17.293 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:59:17.343 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:17.344 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:17.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:17.344 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:17.767 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:59:18.239 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:59:18.344 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:18.345 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:18.345 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:18.345 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:18.711 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:59:19.186 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:59:19.345 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:19.346 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:19.346 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:19.346 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:19.658 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:59:20.132 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:59:20.347 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:20.347 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:20.347 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:20.347 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:20.604 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:59:20.887 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:20.887 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:20.887 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:20.887 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:20.888 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:59:20.888 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:59:20.888 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:59:20.888 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:59:20.888 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:59:20.888 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:59:20.888 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:59:25.895 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:59:25.895 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:59:25.895 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:59:25.895 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:59:25.895 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:59:25.895 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:59:25.902 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:59:25.902 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:59:25.902 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:25.903 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:59:25.903 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:59:25.904 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:59:25.905 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:59:25.905 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:59:25.905 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:25.906 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:59:25.906 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:59:25.906 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:59:25.906 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:59:25.907 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:25.909 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:59:25.909 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:59:25.909 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:59:25.909 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:25.910 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:59:25.910 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:59:25.910 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:59:25.910 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:59:25.910 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:25.913 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:59:25.913 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:59:25.913 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:59:25.913 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:25.913 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:59:25.913 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:59:25.913 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:59:25.913 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:59:25.914 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:25.919 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:59:25.919 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:59:25.919 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:59:25.919 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:59:25.919 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:59:25.919 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:59:25.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:59:25.919 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:25.919 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:59:25.919 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:59:25.920 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:59:25.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:25.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:25.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:25.920 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:25.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:25.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:25.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:25.920 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:59:25.920 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:59:25.920 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:59:25.920 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:59:25.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:25.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:25.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:25.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:59:25.921 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:25.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:25.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:25.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:25.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:25.921 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:25.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:25.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:25.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:25.921 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:25.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:25.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:25.921 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:25.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:25.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:25.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:25.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:25.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:25.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:25.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:25.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:25.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:25.925 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:59:26.403 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:59:26.458 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:59:26.460 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:59:26.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:59:26.465 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:59:26.481 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:26.482 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:26.482 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:26.482 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:26.484 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:59:26.484 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:59:26.484 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:59:26.485 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:59:26.485 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:59:26.485 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:59:26.485 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:59:31.489 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:59:31.490 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:59:31.490 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:59:31.490 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:59:31.490 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:59:31.490 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:59:31.498 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:59:31.498 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:59:31.499 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:31.499 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:59:31.499 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:59:31.502 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:59:31.502 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:59:31.502 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:59:31.502 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:31.503 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:59:31.503 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:59:31.503 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:59:31.503 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:59:31.503 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:31.504 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:59:31.504 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:59:31.505 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:59:31.505 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:31.505 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:59:31.505 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:59:31.505 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:59:31.505 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:59:31.505 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:31.507 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:59:31.507 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:59:31.507 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:59:31.507 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:31.507 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:59:31.507 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:59:31.507 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:59:31.507 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:59:31.507 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:31.509 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:59:31.510 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:59:31.510 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:59:31.510 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:31.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:31.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:31.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:31.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:31.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:31.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:31.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:31.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:31.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:31.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:31.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:31.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:31.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:31.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:31.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:31.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:31.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:31.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:31.515 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:59:31.992 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:59:32.041 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:59:32.044 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:59:32.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:59:32.046 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:59:32.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:59:32.062 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:32.062 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:32.062 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:32.062 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:32.065 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:59:32.065 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:59:32.065 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:59:32.065 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:59:32.065 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:59:32.065 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:59:32.065 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:59:32.066 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=119 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:59:32.066 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=119 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:59:32.066 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=119 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:59:32.066 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=119 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:59:37.069 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:59:37.069 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:59:37.069 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:59:37.069 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:59:37.069 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:59:37.069 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:59:37.078 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:59:37.079 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:59:37.080 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:37.080 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:59:37.080 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:59:37.085 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:59:37.085 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:59:37.086 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:59:37.086 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:37.086 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:59:37.087 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:59:37.087 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:59:37.087 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:59:37.088 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:37.090 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:59:37.090 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:59:37.091 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:59:37.091 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:37.091 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:59:37.092 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:59:37.092 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:59:37.092 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:59:37.093 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:37.094 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:59:37.095 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:59:37.095 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:59:37.095 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:37.095 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:59:37.096 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:59:37.096 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:59:37.096 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:59:37.096 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:37.100 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:59:37.100 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:59:37.100 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:59:37.101 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:59:37.101 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:59:37.101 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:59:37.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:59:37.101 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:37.101 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:59:37.101 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:59:37.101 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:59:37.101 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:37.101 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:37.101 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:37.101 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:37.101 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:37.101 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:37.101 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:37.101 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:59:37.101 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:59:37.102 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:59:37.102 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:59:37.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:37.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:37.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:37.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:59:37.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:37.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:37.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:37.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:37.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:37.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:37.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:37.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:37.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:37.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:37.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:37.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:37.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:37.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:37.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:37.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:37.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:37.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:37.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:37.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:37.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:37.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:37.107 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:59:37.583 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:59:37.637 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:59:37.640 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:59:37.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:59:37.642 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:59:37.658 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:37.659 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:37.659 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:37.659 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:37.662 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:59:37.663 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:59:37.663 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:59:37.663 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:59:37.663 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:59:37.663 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:59:37.663 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:59:37.663 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:59:37.663 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:59:37.663 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:59:37.663 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:59:37.663 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:59:37.663 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:59:42.666 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:59:42.667 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:59:42.667 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:59:42.667 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:59:42.667 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:59:42.667 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:59:42.676 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:59:42.678 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:59:42.678 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:42.679 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:59:42.679 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:59:42.685 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:59:42.685 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:59:42.685 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:59:42.685 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:42.686 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:59:42.686 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:59:42.686 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:59:42.686 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:59:42.686 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:42.690 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:59:42.690 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:59:42.691 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:59:42.691 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:42.691 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:59:42.691 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:59:42.691 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:59:42.691 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:59:42.692 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:42.695 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:59:42.695 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:59:42.695 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:59:42.695 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:42.695 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:59:42.696 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:59:42.696 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:59:42.696 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:59:42.696 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:42.701 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:59:42.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:59:42.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:59:42.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:59:42.701 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:59:42.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:59:42.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:59:42.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:59:42.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:59:42.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:42.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:42.702 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:59:42.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:42.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:42.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:42.702 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:42.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:42.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:42.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:42.702 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:59:42.702 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:59:42.702 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:59:42.702 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:59:42.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:42.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:42.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:42.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:59:42.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:42.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:42.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:42.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:42.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:42.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:42.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:42.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:42.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:42.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:42.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:42.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:42.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:42.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:42.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:42.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:42.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:42.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:42.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:42.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:42.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:42.707 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:59:43.187 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:59:43.231 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:59:43.233 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:59:43.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:59:43.235 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:59:43.242 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:59:43.242 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:59:43.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:59:43.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:59:43.244 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:59:43.244 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:59:43.244 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:59:43.245 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:59:43.658 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:59:43.705 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:43.706 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:43.706 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:43.708 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:44.130 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:59:44.601 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:59:44.706 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:44.707 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:44.707 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:44.709 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:45.072 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:59:45.545 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:59:45.707 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:45.708 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:45.708 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:45.710 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:46.018 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:59:46.303 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:59:46.303 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:59:46.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:59:46.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:59:46.349 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:59:46.349 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:59:46.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:59:46.354 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:46.354 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:46.355 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:46.355 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:46.355 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:59:46.356 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:59:46.356 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:59:46.356 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:59:46.356 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:59:46.356 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:59:46.356 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 01:59:46.356 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=789 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:59:46.356 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=789 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:59:46.356 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=789 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:59:46.356 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=789 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:59:46.356 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=789 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:59:46.356 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=789 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 01:59:51.359 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:59:51.359 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:59:51.359 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:59:51.360 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:59:51.360 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:59:51.360 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:59:51.369 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:59:51.371 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:59:51.371 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:51.372 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 01:59:51.372 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 01:59:51.378 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 01:59:51.378 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 01:59:51.379 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:59:51.379 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:51.379 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:59:51.380 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 01:59:51.380 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 01:59:51.381 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 01:59:51.381 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:51.383 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 01:59:51.384 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 01:59:51.384 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:59:51.384 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:51.384 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:59:51.385 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 01:59:51.385 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 01:59:51.385 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 01:59:51.385 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:51.387 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 01:59:51.388 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 01:59:51.388 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:59:51.388 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 01:59:51.388 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:59:51.388 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 01:59:51.389 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 01:59:51.389 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 01:59:51.389 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:51.392 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 01:59:51.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 01:59:51.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 01:59:51.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 01:59:51.392 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 01:59:51.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 01:59:51.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 01:59:51.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:51.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 01:59:51.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 01:59:51.393 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 01:59:51.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:51.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:51.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:51.393 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:51.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:51.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:51.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:51.393 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 01:59:51.393 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 01:59:51.393 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 01:59:51.393 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 01:59:51.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:51.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:51.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:51.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 01:59:51.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:51.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:51.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:51.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:51.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:51.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:51.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:51.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:51.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:51.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:51.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:51.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:51.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:51.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 01:59:51.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:51.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:51.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:51.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:51.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 01:59:51.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 01:59:51.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:51.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 01:59:51.398 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 01:59:51.877 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 01:59:51.924 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 01:59:51.926 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 01:59:51.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:59:51.928 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 01:59:51.935 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:59:51.935 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:59:51.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 01:59:51.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:59:51.936 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:59:51.936 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:59:51.937 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 01:59:51.937 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 01:59:52.349 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 01:59:52.395 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:52.396 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:52.396 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:52.397 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:52.820 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 01:59:53.294 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 01:59:53.396 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:53.397 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:53.397 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:53.397 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:53.766 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 01:59:54.238 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 01:59:54.398 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:54.398 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:54.398 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:54.398 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:54.709 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 01:59:54.992 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 01:59:54.993 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 01:59:54.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:59:54.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 01:59:55.182 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 01:59:55.399 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:55.400 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:55.400 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:55.400 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:55.655 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 01:59:55.667 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 01:59:55.668 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 01:59:55.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 01:59:55.675 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 01:59:55.675 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 01:59:55.675 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 01:59:55.675 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 01:59:55.676 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 01:59:55.676 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 01:59:55.676 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 01:59:55.676 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 01:59:55.676 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 01:59:55.676 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 01:59:55.676 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:00:00.682 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:00:00.682 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:00:00.682 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:00:00.682 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:00:00.682 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:00:00.682 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:00:00.690 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:00:00.692 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:00:00.692 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:00:00.692 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:00:00.692 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:00:00.697 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:00:00.698 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:00:00.698 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:00:00.698 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:00:00.698 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:00:00.699 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:00:00.699 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:00:00.699 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:00:00.700 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:00.701 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:00:00.701 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:00:00.701 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:00:00.701 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:00:00.702 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:00:00.702 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:00:00.702 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:00:00.702 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:00:00.702 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:00.704 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:00:00.704 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:00:00.705 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:00:00.705 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:00:00.705 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:00:00.705 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:00:00.705 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:00:00.705 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:00:00.705 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:00.708 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:00:00.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:00:00.708 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:00:00.708 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:00:00.708 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:00:00.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:00:00.709 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:00:00.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:00:00.709 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:00.709 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:00:00.709 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:00:00.709 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:00.709 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:00.709 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:00.709 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:00.709 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:00.709 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:00.709 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:00:00.709 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:00:00.709 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:00:00.709 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:00:00.709 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:00.709 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:00.709 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:00.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:00:00.710 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:00.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:00.710 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:00.710 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:00.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:00.710 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:00.710 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:00.710 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:00.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:00.710 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:00.710 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:00.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:00.710 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:00.710 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:00.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:00.710 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:00.710 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:00.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:00.710 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:00.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:00.710 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:00.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:00.710 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:00.714 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:00:01.191 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:00:01.232 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:00:01.233 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:00:01.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:00:01.235 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:00:01.241 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:00:01.241 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:00:01.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:00:01.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:00:01.242 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:00:01.242 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:00:01.242 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:00:01.242 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:00:01.663 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:00:01.712 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:01.712 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:01.712 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:01.712 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:02.135 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:00:02.608 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:00:02.713 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:02.713 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:02.713 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:02.713 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:03.078 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:00:03.551 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:00:03.713 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:03.714 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:03.714 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:03.714 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:04.023 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:00:04.306 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:00:04.306 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:00:04.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:00:04.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:00:04.494 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:00:04.715 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:04.715 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:04.715 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:04.715 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:04.967 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:00:05.440 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:00:05.716 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:05.716 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:05.716 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:05.716 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:05.912 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:00:06.383 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:00:06.856 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:00:07.328 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:00:07.800 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:00:08.271 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:00:08.742 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:00:09.213 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:00:09.309 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:00:09.309 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:00:09.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:00:09.328 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:09.328 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:09.328 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:09.328 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:09.330 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:00:09.330 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:00:09.330 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:00:09.330 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:00:09.330 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:00:09.330 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:00:09.330 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:00:14.335 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:00:14.335 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:00:14.335 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:00:14.335 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:00:14.335 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:00:14.335 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:00:14.344 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:00:14.345 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:00:14.345 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:00:14.346 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:00:14.346 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:00:14.349 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:00:14.350 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:00:14.350 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:00:14.350 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:00:14.351 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:00:14.351 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:00:14.351 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:00:14.352 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:00:14.352 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:14.353 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:00:14.353 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:00:14.354 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:00:14.354 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:00:14.354 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:00:14.354 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:00:14.354 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:00:14.354 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:00:14.354 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:14.356 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:00:14.356 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:00:14.357 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:00:14.357 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:00:14.357 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:00:14.357 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:00:14.357 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:00:14.357 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:00:14.357 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:14.360 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:00:14.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:00:14.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:00:14.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:00:14.360 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:00:14.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:00:14.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:00:14.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:14.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:00:14.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:00:14.360 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:00:14.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:14.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:14.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:14.360 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:14.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:14.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:14.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:14.361 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:00:14.361 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:00:14.361 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:00:14.361 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:00:14.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:14.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:14.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:14.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:00:14.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:14.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:14.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:14.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:14.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:14.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:14.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:14.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:14.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:14.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:14.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:14.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:14.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:14.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:14.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:14.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:14.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:14.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:14.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:14.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:14.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:14.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:14.365 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:00:14.845 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:00:14.886 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:00:14.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:00:14.889 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:00:14.891 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:00:14.901 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:00:14.901 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:00:14.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:00:14.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:00:14.903 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:00:14.903 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:00:14.903 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:00:14.903 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:00:15.317 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:00:15.363 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:15.363 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:15.364 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:15.364 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:15.788 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:00:16.262 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:00:16.364 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:16.364 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:16.365 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:16.365 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:16.734 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:00:17.206 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:00:17.366 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:17.366 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:17.366 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:17.366 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:17.677 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:00:17.960 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:00:17.960 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:00:17.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:00:17.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:00:18.150 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:00:18.366 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:18.366 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:18.367 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:18.367 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:18.623 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:00:19.095 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:00:19.367 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:19.367 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:19.367 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:19.368 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:19.566 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:00:20.036 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:00:20.510 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:00:20.982 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:00:21.454 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:00:21.925 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:00:22.399 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:00:22.871 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:00:22.963 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:00:22.963 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:00:22.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:00:22.970 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:22.970 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:22.970 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:22.970 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:22.970 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:00:22.970 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:00:22.970 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:00:22.970 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:00:22.970 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:00:22.970 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:00:22.971 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:00:27.978 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:00:27.978 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:00:27.978 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:00:27.978 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:00:27.978 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:00:27.978 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:00:27.986 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:00:27.987 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:00:27.987 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:00:27.987 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:00:27.987 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:00:27.989 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:00:27.989 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:00:27.990 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:00:27.990 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:00:27.990 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:00:27.990 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:00:27.991 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:00:27.991 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:00:27.991 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:27.992 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:00:27.992 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:00:27.992 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:00:27.992 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:00:27.992 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:00:27.992 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:00:27.992 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:00:27.992 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:00:27.992 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:27.994 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:00:27.994 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:00:27.994 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:00:27.994 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:00:27.994 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:00:27.994 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:00:27.994 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:00:27.994 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:00:27.994 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:27.996 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:00:27.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:00:27.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:00:27.997 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:00:27.997 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:00:27.997 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:27.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:27.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:27.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:27.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:27.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:27.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:27.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:27.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:27.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:27.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:27.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:27.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:27.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:27.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:27.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:27.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:27.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:28.002 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:00:28.479 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:00:28.523 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:00:28.525 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:00:28.527 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:00:28.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:00:28.536 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:00:28.536 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:00:28.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:00:28.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:00:28.537 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:00:28.537 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:00:28.537 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:00:28.537 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:00:28.950 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:00:29.000 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:29.000 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:29.000 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:29.000 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:29.422 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:00:29.895 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:00:30.001 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:30.002 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:30.002 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:30.002 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:30.368 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:00:30.840 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:00:31.003 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:31.003 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:31.003 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:31.003 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:31.311 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:00:31.594 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:00:31.594 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:00:31.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:00:31.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:00:31.781 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:00:32.004 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:32.005 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:32.005 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:32.005 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:32.255 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:00:32.727 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:00:33.005 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:33.006 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:33.006 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:33.006 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:33.200 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:00:33.673 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:00:34.145 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:00:34.617 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:00:35.088 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:00:35.562 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:00:36.035 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:00:36.507 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:00:36.597 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:00:36.597 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:00:36.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:00:36.615 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:36.616 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:36.616 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:36.616 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:36.618 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:00:36.618 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:00:36.619 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:00:36.619 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:00:36.619 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:00:36.619 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:00:36.619 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:00:36.619 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1862 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:00:36.619 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1862 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:00:36.619 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1862 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:00:36.619 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1862 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:00:36.619 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1862 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:00:36.619 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1862 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:00:41.624 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:00:41.624 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:00:41.624 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:00:41.624 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:00:41.624 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:00:41.624 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:00:41.631 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:00:41.632 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:00:41.632 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:00:41.632 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:00:41.632 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:00:41.635 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:00:41.635 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:00:41.635 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:00:41.636 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:00:41.636 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:00:41.636 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:00:41.636 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:00:41.636 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:00:41.636 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:41.638 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:00:41.639 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:00:41.639 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:00:41.639 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:00:41.639 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:00:41.639 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:00:41.640 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:00:41.640 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:00:41.640 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:41.643 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:00:41.643 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:00:41.644 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:00:41.644 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:00:41.644 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:00:41.644 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:00:41.645 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:00:41.645 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:00:41.645 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:41.648 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:00:41.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:00:41.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:00:41.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:00:41.649 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:00:41.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:00:41.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:00:41.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:00:41.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:41.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:00:41.649 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:00:41.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:41.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:41.649 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:41.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:41.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:41.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:41.650 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:00:41.650 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:00:41.650 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:00:41.650 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:00:41.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:41.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:41.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:41.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:00:41.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:41.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:41.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:41.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:41.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:41.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:41.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:41.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:41.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:41.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:41.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:41.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:41.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:41.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:41.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:41.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:41.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:41.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:41.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:41.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:41.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:41.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:41.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:41.655 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:00:42.131 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:00:42.179 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:00:42.179 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:00:42.179 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:00:42.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:00:42.186 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:00:42.186 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:00:42.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:00:42.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:00:42.188 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:00:42.188 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:00:42.188 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:00:42.188 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:00:42.222 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:00:42.222 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:00:42.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:00:42.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:00:42.603 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:00:42.653 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:42.654 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:42.654 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:42.655 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:43.075 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:00:43.548 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:00:43.654 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:43.655 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:43.655 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:43.656 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:44.021 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:00:44.493 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:00:44.655 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:44.656 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:44.657 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:44.657 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:44.964 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:00:45.437 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:00:45.656 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:45.658 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:45.658 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:45.658 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:45.909 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:00:46.381 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:00:46.656 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:46.658 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:46.659 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:46.659 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:46.852 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:00:47.223 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:00:47.223 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:00:47.235 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:47.235 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:47.235 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:47.235 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:47.237 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:00:47.237 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:00:47.237 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:00:47.237 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:00:47.237 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:00:47.237 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:00:47.237 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:00:52.240 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:00:52.240 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:00:52.240 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:00:52.240 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:00:52.240 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:00:52.240 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:00:52.247 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:00:52.247 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:00:52.247 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:00:52.247 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:00:52.247 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:00:52.249 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:00:52.249 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:00:52.249 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:00:52.249 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:00:52.249 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:00:52.250 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:00:52.250 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:00:52.250 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:00:52.250 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:52.253 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:00:52.253 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:00:52.253 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:00:52.254 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:00:52.254 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:00:52.254 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:00:52.254 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:00:52.254 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:00:52.254 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:52.257 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:00:52.257 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:00:52.257 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:00:52.257 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:00:52.257 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:00:52.257 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:00:52.257 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:00:52.257 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:00:52.257 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:52.261 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:00:52.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:00:52.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:00:52.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:00:52.261 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:00:52.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:00:52.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:00:52.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:52.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:00:52.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:00:52.261 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:00:52.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:52.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:52.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:52.261 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:52.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:52.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:52.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:52.261 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:00:52.261 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:00:52.261 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:00:52.261 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:52.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:00:52.266 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:00:52.744 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:00:52.791 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:00:52.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:00:52.794 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:00:52.796 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:00:52.802 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:00:52.803 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:00:52.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:00:52.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:00:52.803 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:00:52.803 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:00:52.804 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:00:52.804 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:00:53.217 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:00:53.264 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:53.265 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:53.265 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:53.265 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:53.688 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:00:54.161 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:00:54.266 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:54.266 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:54.266 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:54.266 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:54.633 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:00:55.106 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:00:55.267 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:55.267 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:55.267 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:55.268 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:55.577 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:00:55.860 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:00:55.860 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:00:55.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:00:55.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:00:56.050 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:00:56.268 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:56.268 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:56.269 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:56.269 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:56.523 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:00:56.995 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:00:57.270 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:57.270 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:57.270 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:57.270 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:57.466 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:00:57.936 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:00:58.409 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:00:58.455 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:00:58.455 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:00:58.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:00:58.462 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:00:58.463 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:00:58.463 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:00:58.463 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:00:58.465 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:00:58.465 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:00:58.465 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:00:58.465 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:00:58.465 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:00:58.465 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:00:58.465 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:01:03.470 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:01:03.470 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:01:03.471 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:01:03.471 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:01:03.471 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:01:03.471 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:01:03.479 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:01:03.481 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:01:03.481 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:01:03.482 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:01:03.482 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:01:03.488 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:01:03.488 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:01:03.488 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:01:03.488 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:01:03.488 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:01:03.488 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:01:03.488 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:01:03.489 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:01:03.489 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:03.493 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:01:03.493 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:01:03.493 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:01:03.493 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:01:03.493 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:01:03.493 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:01:03.493 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:01:03.493 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:01:03.494 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:03.497 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:01:03.497 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:01:03.497 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:01:03.497 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:01:03.497 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:01:03.498 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:01:03.498 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:01:03.498 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:01:03.498 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:03.503 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:01:03.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:01:03.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:01:03.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:01:03.503 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:01:03.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:01:03.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:01:03.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:03.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:01:03.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:01:03.503 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:01:03.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:03.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:03.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:03.503 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:03.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:03.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:03.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:03.504 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:01:03.504 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:01:03.504 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:01:03.504 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:01:03.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:03.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:03.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:03.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:01:03.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:03.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:03.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:03.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:03.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:03.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:03.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:03.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:03.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:03.505 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:03.505 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:03.505 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:03.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:03.505 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:03.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:03.505 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:03.505 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:03.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:03.505 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:03.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:03.505 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:03.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:03.509 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:01:03.987 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:01:04.036 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:01:04.038 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:01:04.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:01:04.042 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:01:04.046 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:01:04.046 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:01:04.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:01:04.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:01:04.047 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:01:04.047 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:01:04.047 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:01:04.047 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:01:04.459 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:01:04.506 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:04.507 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:04.507 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:04.509 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:04.931 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:01:05.404 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:01:05.507 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:05.508 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:05.508 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:05.509 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:05.876 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:01:06.348 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:01:06.509 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:06.509 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:06.509 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:06.510 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:06.819 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:01:07.134 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:01:07.134 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:01:07.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:01:07.139 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:07.139 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:07.139 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:07.139 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:07.140 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:01:07.140 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:01:07.140 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:01:07.140 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:01:07.140 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:01:07.140 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:01:07.140 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:01:12.146 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:01:12.146 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:01:12.146 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:01:12.146 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:01:12.146 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:01:12.146 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:01:12.151 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:01:12.151 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:01:12.151 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:01:12.151 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:01:12.151 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:01:12.153 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:01:12.154 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:01:12.154 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:01:12.154 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:01:12.154 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:01:12.154 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:01:12.154 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:01:12.154 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:01:12.154 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:12.157 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:01:12.157 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:01:12.157 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:01:12.157 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:01:12.157 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:01:12.157 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:01:12.157 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:01:12.157 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:01:12.158 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:12.160 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:01:12.160 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:01:12.160 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:01:12.160 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:01:12.160 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:01:12.160 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:01:12.161 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:01:12.161 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:01:12.161 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:12.164 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:01:12.164 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:01:12.164 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:01:12.164 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:01:12.164 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:01:12.164 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:01:12.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:01:12.164 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:12.164 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:01:12.164 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:01:12.164 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:01:12.164 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:12.164 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:12.164 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:12.164 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:12.164 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:12.164 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:12.164 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:12.165 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:01:12.165 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:01:12.165 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:01:12.165 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:01:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:12.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:01:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:12.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:12.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:12.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:12.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:12.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:12.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:12.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:12.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:12.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:12.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:12.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:12.169 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:01:12.645 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:01:12.691 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:01:12.694 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:01:12.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:01:12.696 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:01:12.703 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:01:12.703 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:01:12.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:01:12.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:01:12.705 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:01:12.705 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:01:12.705 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:01:12.705 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:01:13.117 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:01:13.167 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:13.168 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:13.168 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:13.168 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:13.589 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:01:14.062 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:01:14.169 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:14.169 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:14.169 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:14.169 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:14.534 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:01:15.006 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:01:15.170 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:15.171 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:15.171 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:15.171 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:15.477 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:01:15.792 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:01:15.792 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:01:15.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:01:15.797 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:15.798 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:15.798 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:15.798 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:15.799 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:01:15.799 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:01:15.799 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:01:15.799 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:01:15.799 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:01:15.799 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:01:15.799 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:01:15.799 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=786 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:01:15.799 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=786 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:01:15.799 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=786 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:01:15.799 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=786 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:01:15.799 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=786 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:01:15.799 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=786 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:01:20.805 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:01:20.805 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:01:20.805 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:01:20.805 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:01:20.805 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:01:20.805 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:01:20.813 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:01:20.814 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:01:20.814 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:01:20.814 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:01:20.815 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:01:20.817 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:01:20.817 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:01:20.818 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:01:20.818 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:01:20.818 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:01:20.819 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:01:20.819 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:01:20.819 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:01:20.819 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:20.820 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:01:20.820 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:01:20.821 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:01:20.821 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:01:20.821 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:01:20.821 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:01:20.821 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:01:20.821 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:01:20.821 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:20.823 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:01:20.823 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:01:20.823 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:01:20.823 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:01:20.823 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:01:20.823 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:01:20.823 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:01:20.823 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:01:20.823 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:20.825 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:01:20.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:01:20.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:01:20.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:01:20.825 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:01:20.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:01:20.826 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:01:20.826 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:01:20.826 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:20.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:20.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:20.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:20.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:20.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:20.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:20.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:20.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:20.831 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:01:21.309 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:01:21.350 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:01:21.353 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:01:21.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:01:21.356 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:01:21.363 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:01:21.363 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:01:21.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:01:21.364 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:01:21.364 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:01:21.364 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:01:21.365 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:01:21.365 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:01:21.625 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:01:21.625 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:01:21.632 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:21.632 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:21.632 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:21.632 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:21.634 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:01:21.634 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:01:21.634 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:01:21.634 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:01:21.634 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:01:21.634 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:01:21.634 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:01:21.634 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=174 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:01:21.634 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=174 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:01:21.634 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=174 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:01:21.634 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=174 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:01:21.634 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=174 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:01:21.634 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=174 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:01:26.640 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:01:26.640 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:01:26.640 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:01:26.640 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:01:26.640 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:01:26.640 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:01:26.647 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:01:26.648 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:01:26.648 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:01:26.649 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:01:26.649 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:01:26.651 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:01:26.651 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:01:26.652 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:01:26.652 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:01:26.652 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:01:26.652 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:01:26.653 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:01:26.653 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:01:26.653 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:26.654 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:01:26.654 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:01:26.654 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:01:26.654 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:01:26.654 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:01:26.654 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:01:26.654 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:01:26.654 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:01:26.654 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:26.656 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:01:26.656 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:01:26.656 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:01:26.656 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:01:26.656 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:01:26.656 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:01:26.656 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:01:26.656 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:01:26.657 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:26.659 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:01:26.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:01:26.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:01:26.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:01:26.659 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:01:26.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:01:26.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:01:26.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:26.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:01:26.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:01:26.659 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:01:26.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:26.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:26.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:26.659 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:26.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:26.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:26.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:26.659 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:01:26.659 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:01:26.659 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:01:26.659 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:01:26.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:26.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:26.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:26.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:01:26.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:26.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:26.660 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:26.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:26.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:26.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:26.660 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:26.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:26.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:26.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:26.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:26.660 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:26.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:26.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:26.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:26.660 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:26.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:26.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:26.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:26.660 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:26.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:26.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:26.664 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:01:27.142 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:01:27.182 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:01:27.185 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:01:27.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:01:27.187 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:01:27.196 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:01:27.196 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:01:27.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:01:27.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:01:27.198 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:01:27.198 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:01:27.198 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:01:27.198 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:01:27.412 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:01:27.413 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:01:27.418 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:27.418 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:27.418 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:27.419 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:27.421 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:01:27.421 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:01:27.421 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:01:27.421 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:01:27.421 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:01:27.421 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:01:27.421 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:01:27.421 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=164 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:01:27.421 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=164 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:01:27.421 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=164 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:01:27.421 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=164 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:01:27.421 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=164 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:01:27.421 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=164 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:01:32.426 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:01:32.426 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:01:32.426 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:01:32.426 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:01:32.426 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:01:32.426 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:01:32.434 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:01:32.436 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:01:32.436 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:01:32.436 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:01:32.436 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:01:32.440 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:01:32.440 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:01:32.440 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:01:32.440 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:01:32.441 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:01:32.441 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:01:32.442 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:01:32.442 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:01:32.442 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:32.443 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:01:32.443 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:01:32.443 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:01:32.443 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:01:32.443 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:01:32.443 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:01:32.444 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:01:32.444 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:01:32.444 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:32.446 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:01:32.446 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:01:32.446 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:01:32.446 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:01:32.446 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:01:32.446 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:01:32.446 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:01:32.446 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:01:32.446 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:32.449 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:01:32.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:01:32.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:01:32.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:01:32.449 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:01:32.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:01:32.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:01:32.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:32.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:01:32.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:01:32.449 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:01:32.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:32.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:32.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:32.449 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:32.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:32.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:32.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:32.449 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:01:32.449 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:01:32.449 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:01:32.449 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:32.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:32.454 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:01:32.933 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:01:32.976 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:01:32.978 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:01:32.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:01:32.980 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:01:32.987 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:01:32.987 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:01:32.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:01:32.989 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:01:32.989 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:01:32.989 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:01:32.989 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:01:32.989 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:01:33.405 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:01:33.451 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:33.452 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:33.452 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:33.452 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:33.876 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:01:34.349 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:01:34.452 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:34.453 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:34.453 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:34.453 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:34.822 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:01:35.294 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:01:35.453 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:35.454 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:35.454 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:35.454 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:35.765 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:01:36.238 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:01:36.455 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:36.455 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:36.455 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:36.455 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:36.711 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:01:37.183 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:01:37.455 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:37.456 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:37.456 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:37.456 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:37.654 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:01:38.127 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:01:38.599 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:01:39.071 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:01:39.542 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:01:40.013 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:01:40.483 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:01:40.954 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:01:41.427 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:01:41.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:01:41.801 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:01:41.808 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:41.808 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:41.808 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:41.808 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:41.810 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:01:41.810 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:01:41.810 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:01:41.810 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:01:41.810 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:01:41.810 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:01:41.811 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:01:46.815 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:01:46.815 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:01:46.815 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:01:46.816 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:01:46.816 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:01:46.816 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:01:46.823 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:01:46.824 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:01:46.824 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:01:46.824 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:01:46.825 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:01:46.829 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:01:46.829 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:01:46.829 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:01:46.829 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:01:46.830 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:01:46.830 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:01:46.830 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:01:46.830 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:01:46.830 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:46.833 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:01:46.833 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:01:46.833 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:01:46.833 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:01:46.834 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:01:46.834 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:01:46.834 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:01:46.834 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:01:46.834 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:46.837 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:01:46.837 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:01:46.837 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:01:46.837 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:01:46.837 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:01:46.837 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:01:46.837 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:01:46.837 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:01:46.837 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:46.840 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:01:46.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:01:46.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:01:46.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:01:46.841 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:01:46.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:01:46.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:01:46.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:46.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:01:46.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:01:46.841 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:01:46.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:46.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:46.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:46.841 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:46.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:46.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:46.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:46.841 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:01:46.841 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:01:46.841 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:01:46.841 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:01:46.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:46.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:46.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:46.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:01:46.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:46.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:46.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:46.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:46.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:46.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:46.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:46.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:46.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:46.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:46.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:46.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:46.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:01:46.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:46.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:46.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:46.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:46.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:01:46.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:46.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:01:46.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:46.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:01:46.846 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:01:47.324 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:01:47.370 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:01:47.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:01:47.374 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:01:47.377 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:01:47.384 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:01:47.384 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:01:47.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:01:47.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:01:47.385 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:01:47.386 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:01:47.386 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:01:47.386 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:01:47.796 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:01:47.844 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:47.844 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:47.844 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:47.844 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:48.267 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:01:48.741 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:01:48.846 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:48.846 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:48.846 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:48.846 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:49.213 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:01:49.685 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:01:49.846 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:49.847 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:49.847 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:49.847 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:50.156 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:01:50.629 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:01:50.847 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:50.848 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:50.848 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:50.848 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:51.102 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:01:51.574 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:01:51.849 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:51.849 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:51.849 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:51.849 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:52.045 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:01:52.519 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:01:52.990 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:01:53.462 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:01:53.933 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:01:54.407 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:01:54.879 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:01:55.351 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:01:55.822 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:01:56.170 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:01:56.170 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:01:56.176 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:01:56.176 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:01:56.177 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:01:56.177 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:01:56.178 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:01:56.178 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:01:56.178 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:01:56.178 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:01:56.178 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:01:56.178 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:01:56.178 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:02:01.187 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:02:01.188 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:02:01.188 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:02:01.188 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:02:01.188 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:02:01.188 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:02:01.195 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:02:01.195 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:02:01.195 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:01.195 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:02:01.195 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:02:01.196 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:02:01.196 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:02:01.196 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:02:01.196 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:01.197 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:02:01.197 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:02:01.197 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:02:01.197 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:02:01.197 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:01.197 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:02:01.197 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:02:01.197 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:02:01.197 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:01.197 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:02:01.197 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:02:01.197 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:02:01.197 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:02:01.198 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:01.198 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:02:01.198 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:02:01.199 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:02:01.199 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:01.199 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:02:01.199 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:02:01.199 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:02:01.199 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:02:01.199 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:01.201 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:02:01.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:02:01.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:02:01.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:02:01.201 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:02:01.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:02:01.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:02:01.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:01.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:02:01.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:02:01.201 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:02:01.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:01.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:01.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:01.201 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:01.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:01.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:01.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:01.201 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:02:01.201 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:02:01.201 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:02:01.201 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:02:01.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:01.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:01.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:01.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:02:01.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:01.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:01.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:01.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:01.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:01.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:01.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:01.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:01.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:01.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:01.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:01.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:01.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:01.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:01.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:01.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:01.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:01.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:01.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:01.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:01.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:01.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:01.206 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:02:01.683 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:02:01.727 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:02:01.729 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:02:01.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:02:01.731 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:02:01.740 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:02:01.740 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:02:01.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:02:01.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:02:01.741 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:02:01.741 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:02:01.741 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:02:01.741 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:02:02.156 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:02:02.204 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:02.204 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:02.204 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:02.204 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:02.625 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:02:03.091 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:02:03.204 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:03.204 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:03.205 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:03.205 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:03.555 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:02:04.021 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:02:04.205 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:04.205 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:04.205 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:04.205 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:04.484 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:02:04.781 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:02:04.782 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:02:04.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:02:04.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:02:04.782 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:02:04.828 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:02:04.869 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:02:04.911 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:02:04.947 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:02:04.947 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:02:04.985 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:02:05.026 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:02:05.063 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:02:05.105 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:02:05.146 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:02:05.183 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:02:05.205 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:05.205 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:05.206 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:05.206 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:05.224 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:02:05.266 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:02:05.303 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:02:05.303 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:02:05.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:02:05.305 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:05.305 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:05.305 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:05.305 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:05.306 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:02:05.306 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:02:05.306 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:02:05.306 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:02:05.306 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:02:05.306 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:02:05.306 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:02:10.311 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:02:10.312 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:02:10.312 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:02:10.312 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:02:10.312 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:02:10.312 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:02:10.319 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:02:10.320 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:02:10.321 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:10.321 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:02:10.321 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:02:10.324 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:02:10.324 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:02:10.324 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:02:10.324 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:10.325 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:02:10.325 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:02:10.325 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:02:10.325 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:02:10.325 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:10.326 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:02:10.326 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:02:10.327 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:02:10.327 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:10.327 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:02:10.327 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:02:10.327 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:02:10.327 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:02:10.327 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:10.329 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:02:10.329 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:02:10.329 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:02:10.329 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:10.329 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:02:10.329 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:02:10.329 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:02:10.329 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:02:10.329 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:10.331 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:02:10.331 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:02:10.331 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:02:10.331 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:02:10.331 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:02:10.332 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:02:10.332 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:02:10.332 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:10.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:10.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:10.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:10.333 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:10.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:10.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:10.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:10.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:10.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:10.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:10.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:10.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:10.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:10.337 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:02:10.803 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:02:10.854 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:02:10.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:02:10.857 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:02:10.859 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:02:10.898 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:10.898 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:10.898 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:10.898 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:10.900 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:02:10.900 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:02:10.900 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:02:10.900 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:02:10.901 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:02:10.901 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:02:10.901 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:02:10.901 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:02:10.901 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:02:10.901 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:02:10.901 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:02:10.901 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:02:10.901 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:02:15.900 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:02:15.900 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:02:15.900 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:02:15.900 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:02:15.900 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:02:15.900 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:02:15.903 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:02:15.904 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:02:15.904 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:15.904 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:02:15.904 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:02:15.905 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:02:15.905 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:02:15.905 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:02:15.905 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:15.905 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:02:15.905 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:02:15.905 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:02:15.905 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:02:15.905 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:15.906 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:02:15.906 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:02:15.906 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:02:15.906 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:15.906 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:02:15.906 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:02:15.906 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:02:15.906 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:02:15.906 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:15.907 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:02:15.907 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:02:15.908 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:02:15.908 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:15.908 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:02:15.908 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:02:15.908 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:02:15.908 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:02:15.908 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:15.909 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:02:15.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:02:15.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:02:15.910 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:02:15.910 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:02:15.910 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:15.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:15.911 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:15.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:15.911 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:15.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:15.911 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:15.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:15.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:15.915 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:02:16.378 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:02:16.422 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:02:16.424 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:02:16.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:02:16.425 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:02:16.841 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:02:16.911 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:16.912 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:16.913 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:16.913 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:17.304 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:02:17.768 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:02:17.912 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:17.912 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:17.913 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:17.913 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:18.232 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:02:18.698 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:02:18.913 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:18.913 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:18.914 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:18.914 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:19.164 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:02:19.631 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:02:19.914 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:19.914 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:19.915 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:19.915 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:20.097 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:02:20.562 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:02:20.914 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:20.914 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:20.915 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:20.916 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:21.028 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:02:21.495 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:02:21.962 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:02:22.428 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:02:22.895 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:02:23.357 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:02:23.823 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:02:24.288 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:02:24.750 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:02:25.212 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:02:25.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:02:25.446 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:25.446 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:25.446 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:25.446 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:25.446 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:02:25.446 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:02:25.447 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:02:25.447 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:02:25.447 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:02:25.447 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:02:25.447 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:02:30.448 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:02:30.448 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:02:30.448 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:02:30.448 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:02:30.448 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:02:30.448 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:02:30.452 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:02:30.452 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:02:30.452 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:30.452 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:02:30.452 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:02:30.453 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:02:30.453 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:02:30.453 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:02:30.453 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:30.453 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:02:30.453 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:02:30.453 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:02:30.453 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:02:30.453 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:30.454 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:02:30.454 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:02:30.454 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:02:30.454 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:30.454 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:02:30.454 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:02:30.454 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:02:30.454 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:02:30.454 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:30.455 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:02:30.455 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:02:30.455 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:02:30.455 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:30.456 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:02:30.456 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:02:30.456 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:02:30.456 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:02:30.456 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:30.457 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:02:30.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:02:30.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:02:30.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:02:30.457 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:02:30.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:02:30.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:02:30.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:30.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:02:30.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:02:30.457 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:02:30.458 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:02:30.458 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:02:30.458 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:30.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:30.462 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:02:30.929 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:02:30.971 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:02:30.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:02:30.972 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:02:30.972 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:02:31.395 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:02:31.460 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:31.460 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:31.460 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:31.461 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:31.864 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:02:32.330 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:02:32.461 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:32.461 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:32.461 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:32.461 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:32.795 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:02:33.260 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:02:33.461 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:33.462 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:33.462 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:33.462 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:33.727 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:02:34.192 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:02:34.462 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:34.462 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:34.462 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:34.462 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:34.657 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:02:35.121 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:02:35.462 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:35.463 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:35.463 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:35.463 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:35.586 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:02:36.053 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:02:36.519 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:02:36.984 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:02:37.449 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:02:37.916 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:02:38.381 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:02:38.850 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:02:39.317 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:02:39.781 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:02:39.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:02:39.990 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:39.991 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:39.991 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:39.991 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:39.991 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:02:39.991 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:02:39.991 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:02:39.991 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:02:39.991 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:02:39.991 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:02:39.991 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:02:44.999 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:02:44.999 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:02:44.999 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:02:44.999 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:02:44.999 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:02:44.999 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:02:45.004 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:02:45.005 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:02:45.005 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:45.006 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:02:45.006 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:02:45.009 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:02:45.009 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:02:45.010 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:02:45.010 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:45.010 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:02:45.010 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:02:45.010 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:02:45.010 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:02:45.010 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:45.013 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:02:45.013 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:02:45.013 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:02:45.013 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:45.013 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:02:45.013 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:02:45.014 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:02:45.014 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:02:45.014 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:45.016 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:02:45.016 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:02:45.016 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:02:45.016 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:45.016 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:02:45.017 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:02:45.017 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:02:45.017 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:02:45.017 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:45.020 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:02:45.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:02:45.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:02:45.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:02:45.020 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:02:45.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:02:45.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:02:45.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:45.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:02:45.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:02:45.020 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:02:45.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:45.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:45.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:45.020 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:45.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:45.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:45.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:45.021 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:02:45.021 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:02:45.021 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:02:45.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:45.021 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:02:45.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:45.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:45.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:02:45.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:45.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:45.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:45.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:45.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:45.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:45.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:45.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:45.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:45.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:45.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:45.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:45.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:45.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:45.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:45.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:45.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:45.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:45.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:45.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:45.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:45.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:45.026 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:02:45.505 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:02:45.543 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:02:45.544 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:02:45.546 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:02:45.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:02:45.977 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:02:46.023 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:46.023 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:46.023 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:46.024 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:46.451 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:02:46.923 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:02:47.024 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:47.024 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:47.025 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:47.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:47.395 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:02:47.866 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:02:48.026 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:48.026 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:48.027 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:48.027 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:48.341 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:02:48.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:02:48.571 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:48.571 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:48.571 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:48.571 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:48.572 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:02:48.572 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:02:48.572 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:02:48.572 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:02:48.572 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:02:48.572 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:02:48.572 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:02:48.572 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=766 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:02:48.572 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=766 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:02:48.572 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=766 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:02:48.572 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=766 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:02:48.572 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=766 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:02:48.572 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=766 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:02:53.583 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:02:53.589 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:02:53.589 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:02:53.590 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:02:53.590 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:02:53.590 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:02:53.596 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:02:53.597 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:02:53.597 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:53.598 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:02:53.598 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:02:53.600 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:02:53.600 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:02:53.601 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:02:53.601 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:53.601 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:02:53.601 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:02:53.602 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:02:53.602 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:02:53.602 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:53.603 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:02:53.603 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:02:53.603 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:02:53.603 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:53.603 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:02:53.603 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:02:53.603 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:02:53.603 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:02:53.603 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:53.605 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:02:53.605 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:02:53.605 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:02:53.605 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:53.605 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:02:53.605 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:02:53.605 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:02:53.605 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:02:53.605 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:53.607 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:02:53.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:02:53.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:02:53.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:02:53.607 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:02:53.608 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:02:53.608 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:53.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:53.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:53.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:53.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:53.613 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:02:54.091 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:02:54.131 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:02:54.133 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:02:54.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:02:54.135 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:02:54.153 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:02:54.153 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:02:54.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:02:54.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:02:54.163 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:02:54.163 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:02:54.163 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:02:54.163 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:02:54.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:02:54.193 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:02:54.194 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:02:54.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:02:54.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:02:54.564 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:02:54.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:02:54.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:02:54.576 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:02:54.576 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:02:54.583 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:54.583 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:54.583 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:54.583 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:54.584 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:02:54.584 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:02:54.584 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:02:54.584 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:02:54.584 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:02:54.584 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:02:54.584 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:02:54.584 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=210 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:02:54.584 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=210 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:02:54.584 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=210 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:02:54.584 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=210 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:02:59.591 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:02:59.591 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:02:59.591 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:02:59.591 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:02:59.591 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:02:59.591 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:02:59.599 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:02:59.601 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:02:59.601 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:59.601 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:02:59.601 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:02:59.606 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:02:59.606 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:02:59.606 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:02:59.606 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:59.607 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:02:59.607 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:02:59.607 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:02:59.607 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:02:59.607 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:02:59.611 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:02:59.611 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:02:59.612 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:02:59.612 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:59.612 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:02:59.612 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:02:59.612 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:02:59.612 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:02:59.612 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:02:59.616 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:02:59.616 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:02:59.616 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:02:59.616 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:02:59.616 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:02:59.617 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:02:59.617 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:02:59.617 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:02:59.617 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:02:59.622 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:02:59.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:02:59.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:02:59.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:02:59.622 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:02:59.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:02:59.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:02:59.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:02:59.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:59.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:02:59.623 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:02:59.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:59.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:59.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:59.623 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:02:59.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:59.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:59.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:59.623 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:02:59.623 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:02:59.623 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:02:59.623 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:02:59.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:59.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:59.624 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:59.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:02:59.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:59.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:59.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:59.624 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:59.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:59.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:59.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:59.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:59.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:59.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:59.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:59.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:02:59.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:59.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:59.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:59.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:59.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:59.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:02:59.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:02:59.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:59.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:59.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:02:59.628 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:03:00.107 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:03:00.155 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:03:00.157 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:03:00.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:03:00.160 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:03:00.171 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:00.171 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:00.171 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:00.171 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:00.174 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:03:00.175 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:03:00.175 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:03:00.175 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:03:00.175 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:03:00.176 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:03:00.176 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:03:00.176 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:00.176 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:00.176 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:00.176 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:00.176 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:00.176 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:05.177 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:03:05.177 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:03:05.177 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:03:05.177 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:03:05.177 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:03:05.177 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:03:05.184 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:03:05.184 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:03:05.184 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:05.185 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:03:05.185 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:03:05.188 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:03:05.189 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:03:05.189 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:03:05.189 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:05.189 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:03:05.189 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:03:05.190 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:03:05.190 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:03:05.190 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:05.193 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:03:05.193 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:03:05.194 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:03:05.194 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:05.194 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:03:05.195 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:03:05.195 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:03:05.195 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:03:05.195 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:05.196 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:03:05.197 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:03:05.197 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:03:05.197 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:05.197 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:03:05.197 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:03:05.197 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:03:05.197 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:03:05.197 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:05.201 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:03:05.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:03:05.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:03:05.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:03:05.201 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:03:05.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:03:05.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:03:05.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:05.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:03:05.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:03:05.202 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:03:05.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:05.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:05.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:05.202 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:05.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:05.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:05.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:05.202 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:03:05.202 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:03:05.202 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:03:05.203 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:03:05.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:05.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:05.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:05.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:03:05.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:05.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:05.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:05.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:05.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:05.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:05.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:05.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:05.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:05.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:05.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:05.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:05.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:05.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:05.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:05.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:05.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:05.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:05.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:05.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:05.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:05.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:05.207 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:03:05.686 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:03:05.734 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:03:05.737 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:03:05.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:03:05.740 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:03:06.158 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:03:06.206 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:06.206 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:06.207 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:06.207 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:06.633 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:03:07.105 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:03:07.208 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:07.208 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:07.208 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:07.208 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:07.576 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:03:07.758 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:07.758 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:07.758 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:07.759 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:07.760 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:03:07.760 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:03:07.760 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:03:07.760 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:03:07.760 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:03:07.760 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:03:07.760 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:03:07.760 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=552 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:07.760 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=552 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:07.760 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=552 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:07.760 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=552 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:07.760 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=552 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:07.760 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=552 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:12.764 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:03:12.764 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:03:12.764 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:03:12.764 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:03:12.764 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:03:12.764 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:03:12.768 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:03:12.768 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:03:12.768 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:12.768 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:03:12.768 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:03:12.769 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:03:12.769 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:03:12.769 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:03:12.769 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:12.770 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:03:12.770 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:03:12.770 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:03:12.770 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:03:12.770 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:12.770 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:03:12.770 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:03:12.770 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:03:12.770 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:12.771 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:03:12.771 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:03:12.771 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:03:12.771 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:03:12.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:12.772 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:03:12.772 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:03:12.772 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:03:12.772 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:12.772 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:03:12.772 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:03:12.772 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:03:12.772 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:03:12.773 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:12.775 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:03:12.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:03:12.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:03:12.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:03:12.775 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:03:12.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:03:12.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:03:12.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:12.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:03:12.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:03:12.775 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:03:12.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:12.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:12.775 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:12.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:12.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:12.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:12.775 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:03:12.775 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:03:12.775 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:03:12.775 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:12.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:12.780 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:03:13.258 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:03:13.301 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:03:13.303 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:03:13.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:03:13.305 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:03:13.308 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:03:13.308 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:03:13.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:03:13.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:03:13.308 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:03:13.308 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:03:13.308 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:03:13.308 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:03:13.730 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:03:13.779 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:13.779 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:13.779 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:13.779 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:14.202 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:03:14.675 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:03:14.780 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:14.780 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:14.780 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:14.781 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:15.148 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:03:15.620 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:03:15.781 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:15.782 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:15.782 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:15.782 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:16.091 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:03:16.108 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:03:16.109 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:03:16.113 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:16.113 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:16.114 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:16.114 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:16.116 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:03:16.116 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:03:16.116 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:03:16.116 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:03:16.116 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:03:16.116 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:03:16.116 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:03:21.121 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:03:21.121 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:03:21.121 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:03:21.121 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:03:21.121 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:03:21.121 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:03:21.128 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:03:21.130 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:03:21.130 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:21.130 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:03:21.130 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:03:21.136 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:03:21.136 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:03:21.136 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:03:21.136 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:21.136 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:03:21.136 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:03:21.137 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:03:21.137 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:03:21.137 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:21.140 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:03:21.140 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:03:21.140 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:03:21.140 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:21.140 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:03:21.140 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:03:21.141 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:03:21.141 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:03:21.141 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:21.143 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:03:21.144 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:03:21.144 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:03:21.144 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:21.144 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:03:21.144 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:03:21.144 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:03:21.144 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:03:21.144 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:21.148 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:03:21.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:03:21.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:03:21.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:03:21.148 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:03:21.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:03:21.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:03:21.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:03:21.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:03:21.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:21.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:21.148 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:03:21.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:21.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:21.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:21.148 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:21.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:21.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:21.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:21.148 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:03:21.148 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:03:21.149 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:03:21.149 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:03:21.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:21.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:21.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:21.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:03:21.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:21.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:21.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:21.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:21.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:21.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:21.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:21.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:21.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:21.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:21.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:21.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:21.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:21.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:21.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:21.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:21.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:21.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:21.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:21.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:21.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:21.153 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:03:21.631 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:03:21.675 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:03:21.677 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:03:21.679 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:03:21.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:03:21.682 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:03:21.683 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:03:21.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:03:21.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:03:21.683 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:03:21.683 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:03:21.683 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:03:21.683 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:03:22.104 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:03:22.151 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:22.152 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:22.152 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:22.152 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:22.575 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:03:23.048 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:03:23.153 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:23.153 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:23.153 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:23.153 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:23.520 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:03:23.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:03:23.776 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:03:23.781 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:23.781 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:23.781 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:23.782 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:23.785 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:03:23.786 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:03:23.786 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:03:23.786 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:03:23.786 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:03:23.786 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:03:23.786 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:03:23.787 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=569 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:23.787 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=569 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:23.787 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=569 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:23.787 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=569 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:23.787 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=569 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:23.787 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=569 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:28.788 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:03:28.788 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:03:28.788 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:03:28.788 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:03:28.788 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:03:28.788 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:03:28.797 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:03:28.799 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:03:28.799 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:28.799 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:03:28.800 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:03:28.805 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:03:28.806 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:03:28.806 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:03:28.806 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:28.807 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:03:28.807 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:03:28.807 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:03:28.808 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:03:28.808 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:28.811 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:03:28.811 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:03:28.812 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:03:28.812 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:28.812 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:03:28.813 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:03:28.813 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:03:28.813 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:03:28.813 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:28.815 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:03:28.815 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:03:28.815 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:03:28.816 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:28.816 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:03:28.816 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:03:28.816 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:03:28.816 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:03:28.816 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:28.820 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:03:28.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:03:28.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:03:28.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:03:28.820 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:03:28.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:03:28.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:03:28.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:28.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:03:28.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:03:28.820 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:03:28.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:28.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:28.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:28.821 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:28.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:28.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:28.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:28.821 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:03:28.821 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:03:28.821 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:03:28.821 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:03:28.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:28.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:28.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:28.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:03:28.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:28.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:28.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:28.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:28.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:28.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:28.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:28.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:28.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:28.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:28.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:28.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:28.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:28.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:28.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:28.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:28.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:28.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:28.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:28.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:28.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:28.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:28.826 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:03:29.304 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:03:29.350 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:03:29.352 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:03:29.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:03:29.354 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:03:29.362 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:03:29.363 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:03:29.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:03:29.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:03:29.363 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:03:29.363 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:03:29.364 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:03:29.364 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:03:29.775 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:03:29.824 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:29.824 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:29.824 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:29.824 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:30.247 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:03:30.718 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:03:30.825 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:30.826 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:30.826 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:30.826 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:31.191 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:03:31.663 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:03:31.826 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:31.826 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:31.826 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:31.827 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:32.135 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:03:32.152 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:03:32.153 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:03:32.156 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:32.156 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:32.156 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:32.156 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:32.156 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:03:32.156 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:03:32.157 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:03:32.157 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:03:32.157 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:03:32.157 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:03:32.157 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:03:37.164 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:03:37.164 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:03:37.164 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:03:37.164 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:03:37.164 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:03:37.164 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:03:37.171 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:03:37.172 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:03:37.172 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:37.173 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:03:37.173 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:03:37.177 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:03:37.177 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:03:37.177 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:03:37.178 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:37.178 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:03:37.178 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:03:37.179 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:03:37.179 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:03:37.179 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:37.181 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:03:37.181 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:03:37.181 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:03:37.181 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:37.182 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:03:37.182 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:03:37.182 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:03:37.182 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:03:37.182 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:37.183 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:03:37.184 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:03:37.184 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:03:37.184 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:37.184 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:03:37.184 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:03:37.184 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:03:37.184 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:03:37.184 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:37.186 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:03:37.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:03:37.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:03:37.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:03:37.186 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:03:37.187 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:03:37.187 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:03:37.187 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:37.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:37.188 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:37.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:37.188 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:37.188 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:37.188 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:37.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:37.188 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:37.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:37.188 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:37.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:37.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:37.192 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:03:37.670 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:03:37.709 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:03:37.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:03:37.711 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:03:37.713 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:03:37.722 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:03:37.722 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:03:37.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:03:37.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:03:37.723 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:03:37.723 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:03:37.723 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:03:37.723 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:03:38.142 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:03:38.189 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:38.189 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:38.190 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:38.190 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:38.614 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:03:39.085 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:03:39.190 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:39.190 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:39.190 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:39.191 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:39.558 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:03:39.809 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:03:39.809 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:03:39.816 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:39.816 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:39.816 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:39.816 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:39.819 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:03:39.819 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:03:39.819 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:03:39.819 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:03:39.819 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:03:39.819 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:03:39.819 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:03:39.819 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=569 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:39.819 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=569 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:39.819 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=569 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:39.819 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=569 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:39.819 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=569 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:39.819 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=569 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:44.823 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:03:44.823 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:03:44.823 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:03:44.823 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:03:44.823 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:03:44.823 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:03:44.832 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:03:44.834 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:03:44.834 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:44.835 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:03:44.835 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:03:44.840 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:03:44.840 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:03:44.840 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:03:44.840 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:44.841 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:03:44.841 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:03:44.841 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:03:44.841 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:03:44.841 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:44.845 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:03:44.845 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:03:44.845 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:03:44.845 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:44.845 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:03:44.845 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:03:44.845 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:03:44.845 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:03:44.845 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:44.848 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:03:44.848 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:03:44.849 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:03:44.849 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:44.849 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:03:44.849 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:03:44.849 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:03:44.849 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:03:44.849 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:44.853 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:03:44.853 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:03:44.853 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:03:44.853 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:03:44.854 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:03:44.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:03:44.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:03:44.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:44.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:03:44.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:03:44.854 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:03:44.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:44.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:44.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:44.854 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:44.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:44.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:44.854 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:03:44.854 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:03:44.854 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:03:44.855 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:03:44.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:44.855 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:44.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:44.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:03:44.855 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:44.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:44.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:44.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:44.855 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:44.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:44.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:44.856 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:44.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:44.856 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:44.856 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:44.856 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:44.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:44.856 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:44.856 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:44.856 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:44.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:44.856 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:44.856 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:44.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:44.856 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:44.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:44.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:44.859 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:03:45.337 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:03:45.379 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:03:45.381 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:03:45.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:03:45.383 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:03:45.390 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:03:45.390 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:03:45.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:03:45.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:03:45.392 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:03:45.392 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:03:45.392 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:03:45.392 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:03:45.809 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:03:45.858 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:45.859 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:45.859 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:45.860 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:46.280 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:03:46.751 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:03:46.860 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:46.860 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:46.860 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:46.860 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:47.225 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:03:47.697 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:03:47.862 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:47.862 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:47.862 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:47.862 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:48.169 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:03:48.640 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:03:48.863 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:48.863 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:48.864 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:48.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:49.113 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:03:49.129 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:03:49.129 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:03:49.137 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:49.137 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:49.137 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:49.137 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:49.140 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:03:49.140 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:03:49.140 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:03:49.140 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:03:49.140 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:03:49.140 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:03:49.140 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:03:49.140 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=926 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:49.140 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=926 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:49.140 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=926 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:49.140 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=926 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:49.140 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=926 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:49.140 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=926 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:03:54.145 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:03:54.145 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:03:54.145 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:03:54.145 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:03:54.145 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:03:54.145 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:03:54.153 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:03:54.154 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:03:54.154 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:54.155 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:03:54.155 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:03:54.158 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:03:54.159 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:03:54.159 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:03:54.159 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:54.159 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:03:54.160 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:03:54.160 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:03:54.161 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:03:54.161 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:54.162 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:03:54.163 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:03:54.163 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:03:54.163 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:54.163 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:03:54.164 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:03:54.164 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:03:54.164 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:03:54.164 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:54.165 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:03:54.166 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:03:54.166 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:03:54.166 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:03:54.166 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:03:54.166 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:03:54.166 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:03:54.166 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:03:54.166 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:54.169 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:03:54.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:03:54.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:03:54.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:03:54.169 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:03:54.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:03:54.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:03:54.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:54.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:03:54.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:03:54.170 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:03:54.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:54.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:54.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:54.170 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:54.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:54.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:54.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:54.170 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:03:54.170 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:03:54.170 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:03:54.170 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:03:54.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:54.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:54.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:54.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:03:54.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:54.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:54.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:54.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:54.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:54.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:54.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:54.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:54.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:54.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:54.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:54.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:54.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:03:54.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:54.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:54.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:54.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:54.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:54.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:03:54.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:54.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:03:54.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:03:54.175 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:03:54.653 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:03:54.691 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:03:54.693 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:03:54.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:03:54.694 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:03:54.702 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:03:54.702 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:03:54.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:03:54.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:03:54.702 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:03:54.703 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:03:54.703 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:03:54.703 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:03:55.124 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:03:55.173 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:55.173 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:55.173 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:55.173 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:55.596 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:03:56.067 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:03:56.174 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:56.174 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:56.175 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:56.175 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:56.540 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:03:57.012 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:03:57.175 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:57.175 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:57.176 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:57.176 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:57.484 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:03:57.955 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:03:58.176 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:58.176 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:58.176 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:58.177 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:58.426 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:03:58.680 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:03:58.680 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:03:58.686 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:03:58.686 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:03:58.686 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:03:58.686 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:03:58.687 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:03:58.687 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:03:58.687 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:03:58.687 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:03:58.687 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:03:58.687 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:03:58.687 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:03.694 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:04:03.694 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:04:03.694 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:03.694 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:03.694 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:03.694 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:03.704 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:03.706 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:04:03.706 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:03.707 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:04:03.707 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:04:03.713 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:04:03.713 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:04:03.714 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:04:03.714 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:03.714 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:03.715 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:04:03.715 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:04:03.715 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:04:03.716 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:03.718 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:04:03.718 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:04:03.719 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:04:03.719 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:03.719 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:03.719 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:04:03.719 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:04:03.719 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:04:03.719 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:03.722 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:04:03.723 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:04:03.723 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:04:03.723 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:03.723 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:03.723 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:04:03.723 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:04:03.723 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:04:03.723 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:03.727 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:04:03.727 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:04:03.727 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:04:03.727 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:04:03.727 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:04:03.727 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:04:03.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:04:03.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:03.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:04:03.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:04:03.728 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:04:03.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:03.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:03.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:03.728 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:03.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:03.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:03.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:03.728 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:04:03.728 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:04:03.728 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:04:03.728 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:04:03.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:03.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:03.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:03.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:04:03.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:03.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:03.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:03.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:03.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:03.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:03.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:03.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:03.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:03.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:03.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:03.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:03.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:03.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:03.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:03.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:03.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:03.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:03.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:03.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:03.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:03.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:03.733 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:04:04.210 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:04:04.260 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:04:04.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:04:04.263 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:04:04.266 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:04:04.682 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:04:04.731 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:04.731 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:04.731 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:04.732 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:05.156 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:04:05.629 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:04:05.733 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:05.733 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:05.733 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:05.733 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:06.100 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:04:06.281 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:06.281 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:06.281 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:06.281 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:06.284 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:06.284 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:06.284 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:06.284 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:06.284 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:04:06.284 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:04:06.284 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:04:11.292 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:04:11.293 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:04:11.293 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:11.293 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:11.293 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:11.293 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:11.301 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:11.302 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:04:11.302 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:11.302 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:04:11.302 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:04:11.305 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:04:11.305 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:04:11.305 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:04:11.305 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:11.306 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:11.306 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:04:11.306 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:04:11.306 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:04:11.306 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:11.307 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:04:11.307 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:04:11.307 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:04:11.307 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:11.307 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:11.308 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:04:11.308 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:04:11.308 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:04:11.308 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:11.309 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:04:11.309 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:04:11.309 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:04:11.309 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:11.309 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:11.309 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:04:11.309 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:04:11.309 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:04:11.310 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:04:11.312 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:04:11.312 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:04:11.312 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:11.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:11.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:11.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:11.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:11.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:11.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:11.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:11.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:11.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:11.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:11.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:11.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:11.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:11.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:11.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:11.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:11.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:11.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:11.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:11.317 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:04:11.795 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:04:11.831 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:04:11.832 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:04:11.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:04:11.834 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:04:11.850 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:04:11.850 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:04:11.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:04:11.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:11.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:04:12.267 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:04:12.315 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:12.315 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:12.315 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:12.315 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:12.740 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:04:13.213 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:04:13.316 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:13.316 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:13.316 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:13.317 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:13.685 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:04:14.161 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:04:14.318 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:14.318 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:14.318 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:14.318 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:14.632 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:04:14.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:04:14.887 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:14.888 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:14.888 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:14.888 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:14.891 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:14.891 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:14.891 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:14.891 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:14.891 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:04:14.891 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:04:14.891 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:04:14.891 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=772 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:14.891 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=772 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:14.891 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=772 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:14.891 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=772 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:14.891 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=772 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:14.892 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=772 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:19.895 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:04:19.895 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:04:19.895 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:19.895 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:19.895 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:19.895 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:19.903 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:19.904 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:04:19.904 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:19.905 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:04:19.905 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:04:19.908 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:04:19.909 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:04:19.909 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:04:19.909 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:19.909 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:19.909 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:04:19.910 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:04:19.910 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:04:19.910 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:19.913 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:04:19.914 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:04:19.914 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:04:19.914 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:19.914 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:19.914 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:04:19.914 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:04:19.914 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:04:19.915 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:19.918 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:04:19.918 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:04:19.918 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:04:19.918 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:19.918 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:19.919 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:04:19.919 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:04:19.919 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:04:19.919 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:19.924 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:04:19.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:04:19.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:04:19.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:04:19.924 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:04:19.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:04:19.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:04:19.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:19.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:04:19.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:04:19.924 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:04:19.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:19.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:19.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:19.925 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:19.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:19.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:19.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:19.925 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:04:19.925 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:04:19.925 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:04:19.925 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:04:19.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:19.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:19.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:19.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:04:19.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:19.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:19.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:19.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:19.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:19.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:19.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:19.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:19.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:19.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:19.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:19.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:19.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:19.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:19.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:19.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:19.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:19.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:19.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:19.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:19.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:19.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:19.930 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:04:20.406 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:04:20.457 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:04:20.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:04:20.460 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:04:20.462 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:04:20.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:04:20.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:04:20.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:04:20.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:20.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:04:20.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:04:20.501 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:20.501 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:20.501 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:20.501 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:20.503 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:20.503 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:20.503 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:04:20.503 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:04:20.503 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:04:20.504 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:20.504 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:25.513 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:04:25.513 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:04:25.514 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:25.514 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:25.514 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:25.514 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:25.522 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:25.524 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:04:25.524 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:25.524 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:04:25.524 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:04:25.528 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:04:25.528 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:04:25.529 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:04:25.529 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:25.530 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:25.530 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:04:25.530 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:04:25.530 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:04:25.531 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:25.532 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:04:25.532 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:04:25.532 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:04:25.532 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:25.533 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:25.533 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:04:25.533 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:04:25.533 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:04:25.533 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:25.534 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:04:25.535 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:04:25.535 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:04:25.535 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:25.535 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:25.535 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:04:25.535 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:04:25.535 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:04:25.535 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:25.537 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:04:25.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:04:25.538 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:04:25.538 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:04:25.538 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:25.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:25.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:25.539 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:25.539 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:25.539 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:25.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:25.539 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:25.539 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:25.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:25.539 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:25.539 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:25.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:25.539 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:25.539 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:25.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:25.539 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:25.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:25.539 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:25.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:25.543 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:04:26.021 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:04:26.061 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:04:26.063 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:04:26.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:04:26.065 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:04:26.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:04:26.080 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:04:26.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:04:26.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:26.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:04:26.493 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:04:26.540 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:26.540 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:26.541 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:26.541 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:26.968 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:04:27.440 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:04:27.542 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:27.542 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:27.542 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:27.542 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:27.916 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:04:28.388 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:04:28.543 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:28.544 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:28.544 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:28.544 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:28.862 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:04:29.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:04:29.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:29.103 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:29.103 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:29.103 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:29.103 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:29.103 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:29.103 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:29.103 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:29.104 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:04:29.104 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:04:29.104 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:04:29.104 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:34.114 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:04:34.114 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:04:34.115 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:34.115 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:34.115 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:34.115 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:34.123 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:34.125 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:04:34.125 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:34.125 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:04:34.126 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:04:34.130 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:04:34.130 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:04:34.131 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:04:34.131 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:34.131 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:04:34.131 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:34.131 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:04:34.131 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:04:34.131 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:34.135 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:04:34.135 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:04:34.135 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:04:34.135 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:34.135 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:34.135 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:04:34.135 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:04:34.136 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:04:34.136 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:34.138 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:04:34.138 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:04:34.138 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:04:34.138 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:34.139 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:34.139 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:04:34.139 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:04:34.139 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:04:34.139 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:34.142 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:04:34.142 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:04:34.142 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:04:34.142 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:04:34.142 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:04:34.142 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:04:34.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:04:34.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:34.143 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:04:34.143 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:04:34.143 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:04:34.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:34.143 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:34.143 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:34.143 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:34.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:34.143 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:34.143 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:34.143 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:04:34.143 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:04:34.143 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:04:34.143 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:04:34.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:34.143 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:34.143 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:34.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:04:34.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:34.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:34.143 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:34.143 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:34.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:34.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:34.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:34.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:34.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:34.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:34.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:34.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:34.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:34.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:34.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:34.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:34.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:34.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:34.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:34.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:34.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:34.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:34.148 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:04:34.625 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:04:34.665 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:04:34.667 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:04:34.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:04:34.669 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:04:34.689 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:04:34.689 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:04:34.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:04:34.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:34.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:04:34.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:04:34.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:34.707 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:34.707 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:34.707 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:34.707 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:34.709 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:34.709 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:34.709 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:34.709 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:34.709 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:04:34.709 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:04:34.709 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:04:34.710 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:34.710 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:34.710 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:34.710 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:34.710 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:34.710 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:39.715 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:04:39.715 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:04:39.715 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:39.715 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:39.715 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:39.715 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:39.723 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:39.725 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:04:39.725 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:39.726 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:04:39.726 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:04:39.731 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:04:39.732 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:04:39.732 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:04:39.733 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:39.733 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:39.734 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:04:39.734 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:04:39.734 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:04:39.735 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:39.737 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:04:39.737 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:04:39.737 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:04:39.737 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:39.738 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:39.738 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:04:39.739 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:04:39.739 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:04:39.739 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:39.741 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:04:39.741 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:04:39.741 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:04:39.742 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:39.742 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:39.742 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:04:39.742 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:04:39.742 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:04:39.742 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:39.746 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:04:39.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:04:39.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:04:39.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:04:39.746 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:04:39.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:04:39.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:04:39.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:39.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:04:39.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:04:39.747 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:04:39.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:39.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:39.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:39.747 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:39.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:39.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:39.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:39.747 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:04:39.747 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:04:39.747 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:04:39.747 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:04:39.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:39.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:39.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:39.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:04:39.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:39.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:39.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:39.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:39.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:39.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:39.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:39.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:39.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:39.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:39.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:39.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:39.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:39.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:39.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:39.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:39.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:39.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:39.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:39.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:39.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:39.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:39.752 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:04:40.229 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:04:40.274 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:04:40.276 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:04:40.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:04:40.278 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:04:40.287 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:40.287 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:40.287 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:40.287 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:40.291 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:40.291 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:40.291 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:04:40.291 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:04:40.291 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:04:40.291 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:40.291 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:40.291 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:40.291 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:40.291 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:40.291 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:40.291 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:40.291 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:40.291 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:45.294 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:04:45.294 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:04:45.294 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:45.294 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:45.294 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:45.294 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:45.297 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:45.297 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:04:45.297 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:45.297 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:04:45.297 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:04:45.298 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:04:45.298 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:04:45.298 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:04:45.298 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:45.298 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:45.299 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:04:45.299 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:04:45.299 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:04:45.299 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:45.299 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:04:45.299 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:04:45.299 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:04:45.299 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:45.299 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:45.300 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:04:45.300 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:04:45.300 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:04:45.300 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:45.301 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:04:45.301 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:04:45.301 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:04:45.301 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:45.301 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:45.301 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:04:45.301 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:04:45.301 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:04:45.301 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:04:45.303 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:04:45.303 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:04:45.303 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:45.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:45.304 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:45.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:45.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:45.304 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:45.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:45.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:45.304 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:45.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:45.308 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:04:45.785 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:04:45.828 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:04:45.830 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:04:45.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:04:45.833 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:04:45.848 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:45.848 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:45.848 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:45.848 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:45.853 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:45.853 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:45.853 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:45.853 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:45.853 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:04:45.853 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:04:45.853 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:04:45.854 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:45.854 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:45.854 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:45.854 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:45.854 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:45.854 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:50.855 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:04:50.855 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:04:50.855 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:50.855 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:50.855 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:50.855 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:50.858 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:50.858 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:04:50.858 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:50.858 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:04:50.858 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:04:50.859 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:04:50.859 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:04:50.859 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:04:50.859 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:50.860 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:50.860 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:04:50.860 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:04:50.860 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:04:50.860 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:50.860 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:04:50.860 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:04:50.860 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:04:50.861 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:50.861 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:50.861 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:04:50.861 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:04:50.861 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:04:50.861 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:50.862 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:04:50.862 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:04:50.862 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:04:50.862 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:50.862 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:50.862 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:04:50.862 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:04:50.862 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:04:50.862 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:04:50.864 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:04:50.864 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:04:50.864 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:50.864 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:50.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:50.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:50.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:50.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:50.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:50.865 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:50.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:50.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:50.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:50.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:50.865 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:50.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:50.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:50.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:50.865 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:50.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:50.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:50.865 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:50.869 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:04:51.345 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:04:51.390 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:04:51.392 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:04:51.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:04:51.394 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:04:51.408 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:51.408 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:51.408 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:51.408 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:51.413 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:51.413 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:04:51.413 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:04:51.413 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:04:51.414 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:51.414 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:51.414 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:51.414 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:51.414 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:51.414 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:51.414 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:51.415 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:51.415 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:51.415 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:51.415 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:51.415 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:56.415 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:04:56.415 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:04:56.416 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:56.416 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:56.416 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:56.416 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:56.431 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:56.432 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:04:56.432 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:56.432 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:04:56.432 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:04:56.434 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:04:56.435 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:04:56.435 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:04:56.435 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:56.435 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:56.435 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:04:56.436 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:04:56.436 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:04:56.436 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:56.437 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:04:56.437 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:04:56.437 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:04:56.437 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:56.437 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:56.437 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:04:56.437 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:04:56.437 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:04:56.437 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:56.438 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:04:56.438 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:04:56.439 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:04:56.439 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:04:56.439 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:56.439 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:04:56.439 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:04:56.439 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:04:56.439 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:04:56.441 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:04:56.441 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:04:56.441 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:56.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:04:56.446 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:04:56.924 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:04:56.966 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:04:56.969 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:04:56.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:04:56.971 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:04:56.984 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:04:56.984 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:04:56.984 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:04:56.984 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:04:56.988 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:04:56.988 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:04:56.988 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:04:56.988 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:04:56.989 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:04:56.989 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:04:56.989 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:04:56.989 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:56.989 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:56.989 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:56.989 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:56.989 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:56.989 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:56.989 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:04:56.989 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:01.995 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:05:01.996 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:05:01.996 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:01.996 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:01.996 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:01.996 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:02.004 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:02.005 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:05:02.005 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:02.005 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:05:02.005 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:05:02.007 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:05:02.008 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:05:02.008 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:05:02.008 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:02.008 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:02.008 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:05:02.009 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:05:02.009 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:05:02.009 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:02.010 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:05:02.010 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:05:02.010 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:05:02.010 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:02.010 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:02.010 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:05:02.010 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:05:02.010 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:05:02.010 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:02.012 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:05:02.012 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:05:02.012 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:05:02.012 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:02.012 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:02.012 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:05:02.012 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:05:02.012 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:05:02.012 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:02.014 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:05:02.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:05:02.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:05:02.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:05:02.014 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:05:02.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:05:02.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:05:02.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:02.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:05:02.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:05:02.014 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:05:02.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:05:02.015 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:05:02.015 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:05:02.015 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:02.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:02.019 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:05:02.497 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:05:02.537 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:05:02.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:02.540 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:05:02.542 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:05:02.969 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:05:03.017 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:03.018 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:03.018 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:03.018 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:03.440 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:05:03.915 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:05:04.019 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:04.019 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:04.020 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:04.020 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:04.387 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:05:04.861 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:05:05.021 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:05.021 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:05.021 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:05.021 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:05.333 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:05:05.559 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:05:05.559 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:05:05.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:05:05.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:05:05.560 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:05:05.561 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:05:05.561 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:05:05.562 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:05:05.806 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:05:06.022 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:06.022 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:06.022 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:06.023 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:06.276 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:05:06.750 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:05:07.023 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:07.023 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:07.024 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:07.024 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:07.222 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:05:07.694 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:05:07.813 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:05:07.813 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:05:07.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:07.819 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:07.819 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:07.819 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:07.819 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:07.822 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:07.822 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:07.822 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:07.822 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:07.822 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:05:07.822 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:05:07.822 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:05:12.824 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:05:12.824 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:05:12.824 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:12.824 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:12.824 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:12.824 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:12.831 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:12.832 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:05:12.832 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:12.833 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:05:12.833 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:05:12.836 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:05:12.837 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:05:12.837 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:05:12.837 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:12.838 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:12.838 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:05:12.839 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:05:12.839 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:05:12.839 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:12.841 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:05:12.841 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:05:12.842 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:05:12.842 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:12.842 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:12.842 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:05:12.843 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:05:12.843 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:05:12.843 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:12.844 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:05:12.845 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:05:12.845 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:05:12.845 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:12.845 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:12.845 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:05:12.845 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:05:12.845 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:05:12.846 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:12.849 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:05:12.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:05:12.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:05:12.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:05:12.849 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:05:12.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:05:12.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:05:12.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:12.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:05:12.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:05:12.849 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:05:12.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:12.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:12.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:12.849 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:12.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:12.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:12.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:12.850 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:05:12.850 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:05:12.850 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:05:12.850 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:05:12.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:12.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:12.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:12.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:05:12.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:12.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:12.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:12.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:12.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:12.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:12.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:12.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:12.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:12.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:12.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:12.851 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:12.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:12.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:12.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:12.851 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:12.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:12.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:12.851 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:12.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:12.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:12.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:12.855 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:05:13.332 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:05:13.375 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:05:13.377 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:05:13.379 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:05:13.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:13.397 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:05:13.397 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:05:13.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:05:13.414 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:13.414 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:13.414 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:13.414 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:13.417 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:13.418 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:05:13.418 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:05:13.418 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:05:13.418 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:13.419 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:13.419 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:13.419 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:13.419 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:13.419 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:13.419 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:13.419 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:13.419 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:13.419 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:18.421 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:05:18.421 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:05:18.421 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:18.421 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:18.421 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:18.421 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:18.427 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:18.429 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:05:18.429 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:18.430 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:05:18.430 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:05:18.434 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:05:18.434 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:05:18.435 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:05:18.435 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:18.435 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:18.435 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:05:18.435 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:05:18.435 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:05:18.435 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:18.439 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:05:18.439 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:05:18.439 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:05:18.439 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:18.439 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:18.439 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:05:18.439 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:05:18.439 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:05:18.440 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:18.442 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:05:18.442 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:05:18.442 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:05:18.442 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:18.443 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:18.443 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:05:18.443 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:05:18.443 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:05:18.443 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:18.446 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:05:18.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:05:18.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:05:18.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:05:18.446 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:05:18.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:05:18.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:05:18.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:18.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:05:18.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:05:18.447 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:05:18.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:18.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:18.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:18.447 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:18.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:18.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:18.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:18.447 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:05:18.447 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:05:18.447 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:05:18.447 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:05:18.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:18.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:18.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:18.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:05:18.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:18.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:18.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:18.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:18.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:18.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:18.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:18.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:18.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:18.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:18.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:18.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:18.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:18.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:18.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:18.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:18.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:18.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:18.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:18.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:18.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:18.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:18.452 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:05:18.930 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:05:18.977 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:05:18.980 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:05:18.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:18.983 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:05:19.005 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:05:19.006 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:05:19.006 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:05:19.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:19.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:19.023 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:19.023 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:19.023 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:19.024 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:19.026 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:19.027 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:19.027 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:19.027 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:19.027 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:05:19.027 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:05:19.027 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:05:19.027 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=125 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:19.027 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:19.028 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:19.028 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:19.028 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:24.032 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:05:24.032 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:05:24.032 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:24.032 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:24.032 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:24.032 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:24.037 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:24.038 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:05:24.038 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:24.038 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:05:24.039 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:05:24.042 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:05:24.043 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:05:24.043 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:05:24.043 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:24.043 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:24.044 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:05:24.044 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:05:24.044 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:05:24.044 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:24.046 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:05:24.046 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:05:24.046 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:05:24.046 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:24.046 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:24.046 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:05:24.046 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:05:24.046 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:05:24.046 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:24.048 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:05:24.049 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:05:24.049 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:05:24.049 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:24.049 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:24.049 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:05:24.049 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:05:24.049 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:05:24.049 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:24.052 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:05:24.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:05:24.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:05:24.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:05:24.052 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:05:24.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:05:24.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:05:24.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:24.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:05:24.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:05:24.052 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:05:24.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:24.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:24.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:24.052 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:24.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:24.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:24.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:24.053 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:05:24.053 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:05:24.053 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:05:24.053 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:05:24.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:24.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:24.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:24.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:05:24.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:24.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:24.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:24.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:24.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:24.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:24.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:24.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:24.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:24.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:24.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:24.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:24.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:24.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:24.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:24.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:24.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:24.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:24.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:24.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:24.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:24.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:24.057 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:05:24.533 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:05:24.579 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:05:24.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:24.582 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:05:24.585 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:05:24.605 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:05:24.605 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:05:24.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:05:24.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:24.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:24.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:24.625 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:24.626 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:24.626 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:24.626 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:24.629 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:24.629 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:24.629 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:24.629 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:24.629 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:05:24.629 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:05:24.629 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:05:24.629 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:24.629 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:24.629 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:24.629 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:24.629 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:24.629 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:29.634 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:05:29.634 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:05:29.634 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:29.634 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:29.634 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:29.634 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:29.641 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:29.642 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:05:29.642 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:29.642 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:05:29.643 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:05:29.645 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:05:29.645 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:05:29.645 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:05:29.645 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:29.645 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:29.646 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:05:29.646 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:05:29.646 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:05:29.646 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:29.647 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:05:29.647 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:05:29.647 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:05:29.647 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:29.647 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:29.647 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:05:29.648 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:05:29.648 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:05:29.648 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:29.649 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:05:29.649 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:05:29.649 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:05:29.649 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:29.650 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:29.650 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:05:29.650 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:05:29.650 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:05:29.650 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:29.652 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:05:29.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:05:29.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:05:29.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:05:29.652 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:05:29.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:05:29.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:05:29.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:29.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:05:29.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:05:29.652 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:05:29.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:29.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:29.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:29.652 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:05:29.653 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:05:29.653 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:05:29.653 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:29.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:29.657 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:05:30.136 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:05:30.179 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:05:30.181 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:05:30.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:30.183 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:05:30.209 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:05:30.210 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:05:30.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:05:30.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:30.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:30.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:30.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:30.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:30.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:30.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:30.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:30.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:30.256 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:30.256 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:30.256 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:30.257 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:30.260 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:30.260 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:30.260 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:30.260 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:30.260 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:05:30.260 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:05:30.260 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:05:35.264 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:05:35.264 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:05:35.264 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:35.264 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:35.264 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:35.264 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:35.272 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:35.273 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:05:35.274 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:35.274 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:05:35.274 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:05:35.277 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:05:35.277 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:05:35.277 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:05:35.277 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:35.278 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:35.278 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:05:35.278 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:05:35.278 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:05:35.278 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:35.279 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:05:35.279 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:05:35.279 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:05:35.280 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:35.280 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:35.280 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:05:35.280 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:05:35.280 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:05:35.280 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:35.282 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:05:35.282 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:05:35.282 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:05:35.282 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:35.282 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:35.282 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:05:35.282 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:05:35.282 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:05:35.282 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:35.285 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:05:35.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:05:35.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:05:35.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:05:35.285 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:05:35.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:05:35.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:05:35.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:05:35.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:35.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:05:35.285 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:05:35.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:35.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:35.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:35.285 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:35.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:05:35.286 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:05:35.286 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:05:35.286 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:35.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:35.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:35.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:35.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:35.290 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:05:35.768 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:05:35.814 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:05:35.816 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:05:35.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:35.819 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:05:35.821 [DEBUG] fake_trx.py:382 (BTS@172.18.59.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-06 02:05:35.821 [INFO] fake_trx.py:385 (BTS@172.18.59.20:5700) Artificial TRXC delay set to 200
2026-03-06 02:05:35.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-06 02:05:36.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:36.244 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:05:36.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:36.451 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:36.451 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:36.451 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:36.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:36.652 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:36.718 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:05:37.191 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:05:37.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:37.459 [DEBUG] fake_trx.py:382 (BTS@172.18.59.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-06 02:05:37.459 [INFO] fake_trx.py:385 (BTS@172.18.59.20:5700) Artificial TRXC delay set to 0
2026-03-06 02:05:37.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-06 02:05:37.459 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:37.459 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:37.459 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:37.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:37.468 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:37.468 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:37.468 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:37.468 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:37.469 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:37.469 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:05:37.469 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:05:37.469 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:05:37.469 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:37.469 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:37.469 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:37.469 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=470 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:37.469 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=470 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:37.469 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=470 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:37.469 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=470 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:37.469 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=470 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:37.469 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=470 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:42.476 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:05:42.476 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:05:42.476 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:42.476 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:42.476 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:42.476 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:42.484 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:42.485 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:05:42.485 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:42.485 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:05:42.486 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:05:42.488 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:05:42.488 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:05:42.489 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:05:42.489 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:42.489 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:42.489 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:05:42.490 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:05:42.490 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:05:42.490 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:42.491 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:05:42.491 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:05:42.491 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:05:42.491 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:42.491 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:42.491 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:05:42.491 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:05:42.491 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:05:42.491 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:42.493 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:05:42.493 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:05:42.493 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:05:42.493 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:42.493 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:42.493 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:05:42.493 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:05:42.493 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:05:42.493 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:42.496 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:05:42.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:05:42.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:05:42.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:05:42.496 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:05:42.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:05:42.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:05:42.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:42.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:05:42.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:05:42.496 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:05:42.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:42.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:42.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:42.496 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:42.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:42.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:42.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:42.496 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:05:42.496 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:05:42.496 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:05:42.497 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:42.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:42.501 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:05:42.979 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:05:43.023 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:05:43.026 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:05:43.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:43.028 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:05:43.030 [DEBUG] fake_trx.py:382 (BTS@172.18.59.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-06 02:05:43.031 [INFO] fake_trx.py:385 (BTS@172.18.59.20:5700) Artificial TRXC delay set to 200
2026-03-06 02:05:43.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-06 02:05:43.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:43.452 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:05:43.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:43.663 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:43.663 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:43.663 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:43.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:43.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:43.928 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:05:44.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:44.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:44.402 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:05:44.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:44.666 [DEBUG] fake_trx.py:382 (BTS@172.18.59.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-06 02:05:44.667 [INFO] fake_trx.py:385 (BTS@172.18.59.20:5700) Artificial TRXC delay set to 0
2026-03-06 02:05:44.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-06 02:05:44.667 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:44.667 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:44.667 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:44.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:44.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:44.668 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:44.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:44.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:44.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:44.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:44.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:44.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:44.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:44.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:44.675 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:44.675 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:44.675 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:44.675 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:44.676 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:44.676 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:05:44.676 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:05:44.676 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:05:44.676 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:44.676 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:44.676 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:44.676 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=470 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:44.676 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=470 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:44.676 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=470 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:44.676 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=470 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:44.676 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=470 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:44.676 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=470 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:49.683 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:05:49.683 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:05:49.683 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:49.683 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:49.683 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:49.683 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:49.691 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:49.694 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:05:49.694 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:49.694 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:05:49.694 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:05:49.699 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:05:49.700 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:05:49.700 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:05:49.700 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:49.701 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:49.701 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:05:49.702 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:05:49.702 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:05:49.702 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:49.704 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:05:49.705 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:05:49.705 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:05:49.705 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:49.706 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:49.706 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:05:49.706 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:05:49.706 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:05:49.706 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:49.709 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:05:49.709 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:05:49.709 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:05:49.709 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:49.709 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:49.709 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:05:49.709 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:05:49.709 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:05:49.709 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:49.713 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:05:49.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:05:49.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:05:49.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:05:49.714 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:05:49.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:05:49.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:05:49.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:49.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:05:49.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:05:49.714 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:05:49.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:49.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:49.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:49.714 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:49.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:49.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:49.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:49.714 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:05:49.714 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:05:49.714 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:05:49.714 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:05:49.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:49.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:49.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:49.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:05:49.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:49.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:49.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:49.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:49.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:49.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:49.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:49.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:49.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:49.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:49.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:49.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:49.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:49.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:49.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:49.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:49.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:49.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:49.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:49.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:49.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:49.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:49.719 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:05:50.198 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:05:50.247 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:05:50.249 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:05:50.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:50.251 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:05:50.271 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:05:50.272 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:05:50.272 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:05:50.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:50.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:50.289 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:50.289 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:50.289 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:50.289 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:50.293 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:50.293 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:50.293 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:50.293 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:50.293 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:05:50.294 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:05:50.294 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:05:50.294 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:50.294 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:50.294 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:50.294 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:50.294 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:50.294 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:55.297 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:05:55.297 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:05:55.297 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:55.297 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:55.297 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:55.297 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:55.305 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:55.306 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:05:55.306 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:55.306 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:05:55.306 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:05:55.309 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:05:55.310 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:05:55.310 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:05:55.310 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:55.310 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:55.311 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:05:55.311 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:05:55.311 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:05:55.311 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:55.312 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:05:55.313 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:05:55.313 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:05:55.313 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:55.313 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:55.313 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:05:55.313 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:05:55.313 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:05:55.314 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:55.315 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:05:55.315 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:05:55.315 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:05:55.315 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:05:55.315 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:55.315 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:05:55.316 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:05:55.316 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:05:55.316 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:55.318 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:05:55.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:05:55.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:05:55.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:05:55.318 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:05:55.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:05:55.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:05:55.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:05:55.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:55.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:05:55.318 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:05:55.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:55.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:55.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:55.318 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:55.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:55.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:55.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:55.318 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:05:55.318 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:05:55.318 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:05:55.319 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:05:55.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:05:55.323 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:05:55.801 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:05:55.842 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:05:55.844 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:05:55.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:55.846 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:05:55.867 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:05:55.867 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:05:55.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:05:55.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:55.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:05:55.881 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:05:55.881 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:05:55.882 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:05:55.882 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:05:55.884 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:05:55.884 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:05:55.884 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:05:55.884 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:05:55.885 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:05:55.885 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:05:55.885 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:05:55.885 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:55.885 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:55.885 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:55.885 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:55.885 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:05:55.885 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:06:00.889 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:06:00.889 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:06:00.889 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:06:00.889 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:06:00.889 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:06:00.889 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:06:00.896 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:06:00.898 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:06:00.898 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:06:00.899 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:06:00.899 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:06:00.903 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:06:00.904 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:06:00.904 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:06:00.905 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:06:00.905 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:06:00.906 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:06:00.906 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:06:00.906 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:06:00.907 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:06:00.908 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:06:00.909 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:06:00.909 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:06:00.909 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:06:00.909 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:06:00.910 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:06:00.910 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:06:00.910 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:06:00.910 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:06:00.912 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:06:00.912 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:06:00.912 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:06:00.912 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:06:00.912 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:06:00.912 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:06:00.912 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:06:00.913 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:06:00.913 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:06:00.916 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:06:00.916 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:06:00.916 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:06:00.916 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:06:00.916 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:06:00.916 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:06:00.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:06:00.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:06:00.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:06:00.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:06:00.917 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:06:00.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:06:00.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:06:00.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:06:00.917 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:06:00.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:06:00.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:06:00.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:06:00.917 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:06:00.917 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:06:00.917 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:06:00.917 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:06:00.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:06:00.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:06:00.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:06:00.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:06:00.918 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:06:00.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:06:00.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:06:00.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:06:00.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:06:00.918 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:06:00.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:06:00.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:06:00.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:06:00.918 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:06:00.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:06:00.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:06:00.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:06:00.918 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:06:00.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:06:00.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:06:00.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:06:00.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:06:00.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:06:00.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:06:00.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:06:00.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:06:00.922 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:06:01.399 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:06:01.448 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:06:01.449 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:06:01.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:01.452 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:06:01.474 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:01.474 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:01.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:01.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:01.480 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:01.480 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:01.480 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:01.480 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:01.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:01.501 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:01.502 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:01.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:01.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:01.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:01.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:01.562 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:01.562 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:01.578 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:01.578 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:01.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:01.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:01.580 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:01.580 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:01.580 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:01.580 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:01.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:01.643 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:01.644 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:01.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:01.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:01.871 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:06:01.920 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:06:01.920 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:06:01.920 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:06:01.920 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:06:02.342 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:06:02.816 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:06:02.922 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:06:02.922 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:06:02.922 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:06:02.922 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:06:03.288 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:06:03.761 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:06:03.922 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:06:03.922 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:06:03.923 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:06:03.923 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:06:04.231 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:06:04.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:04.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:04.650 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:04.651 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:04.676 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:04.676 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:04.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:04.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:04.678 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:04.678 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:04.678 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:04.678 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:04.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:04.704 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:06:04.705 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:04.706 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:04.706 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:04.706 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:04.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:04.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:04.747 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:04.747 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:04.763 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:04.763 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:04.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:04.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:04.765 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:04.765 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:04.765 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:04.765 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:04.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:04.802 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:04.802 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:04.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:04.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:04.923 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:06:04.924 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:06:04.924 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:06:04.924 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:06:05.175 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:06:05.648 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:06:05.925 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:06:05.925 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:06:05.925 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:06:05.925 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:06:06.121 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:06:06.594 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:06:07.067 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:06:07.539 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:06:07.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:07.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:07.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:07.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:07.828 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:07.828 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:07.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:07.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:07.829 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:07.829 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:07.829 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:07.829 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:07.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:07.874 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:07.874 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:07.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:07.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:08.010 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:06:08.483 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:06:08.956 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:06:09.428 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:06:09.902 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:06:10.375 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:06:10.847 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:06:10.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:10.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:10.880 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:10.880 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:10.904 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:10.904 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:10.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:10.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:10.905 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:10.906 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:10.906 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:10.906 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:10.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:10.946 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:10.947 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:10.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:10.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:10.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:10.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:10.993 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:10.993 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:11.010 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:11.010 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:11.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:11.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:11.011 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:11.011 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:11.012 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:11.012 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:11.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:11.036 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:11.036 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:11.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:11.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:11.318 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:06:11.789 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:06:11.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:11.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:11.998 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:11.998 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:12.014 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:12.014 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:12.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:12.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:12.015 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:12.015 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:12.015 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:12.015 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:12.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:12.021 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:12.021 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:12.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:12.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:12.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:12.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:12.092 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:12.092 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:12.100 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:12.100 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:12.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:12.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:12.101 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:12.101 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:12.101 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:12.101 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:12.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:12.117 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:12.117 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:12.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:12.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:12.261 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:06:12.734 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:06:13.206 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:06:13.677 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:06:14.148 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:06:14.622 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:06:15.094 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:06:15.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:15.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:15.123 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:15.124 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:15.145 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:15.145 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:15.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:15.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:15.146 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:15.146 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:15.147 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:15.147 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:15.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:15.195 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:15.196 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:15.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:15.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:15.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:15.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:15.265 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:15.266 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:15.283 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:15.283 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:15.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:15.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:15.285 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:15.285 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:15.285 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:15.285 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:15.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:15.334 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:15.335 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:15.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:15.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:15.566 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:06:16.037 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:06:16.511 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:06:16.983 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:06:17.455 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:06:17.926 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:06:18.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:18.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:18.343 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:18.343 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:18.360 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:18.360 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:18.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:18.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:18.361 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:18.361 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:18.361 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:18.361 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:18.397 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:06:18.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:18.405 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:18.406 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:18.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:18.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:18.870 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:06:19.343 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:06:19.815 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:06:20.286 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:06:20.758 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:06:21.231 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:06:21.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:21.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:21.412 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:21.412 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:21.432 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:21.432 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:21.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:21.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:21.433 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:21.433 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:21.433 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:21.433 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:21.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:21.475 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:21.476 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:21.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:21.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:21.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:21.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:21.559 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:21.560 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:21.577 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:21.577 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:21.577 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:21.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:21.579 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:21.579 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:21.579 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:21.579 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:21.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:21.615 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:21.616 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:21.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:21.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:21.703 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 02:06:22.174 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 02:06:22.648 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 02:06:22.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:22.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:22.825 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:22.826 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:22.844 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:22.844 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:22.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:22.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:22.845 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:22.846 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:22.846 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:22.846 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:22.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:22.889 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:22.890 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:22.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:22.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:23.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:23.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:23.112 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:23.112 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:23.120 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 02:06:23.124 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:23.124 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:23.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:23.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:23.125 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:23.125 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:23.126 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:23.126 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:23.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:23.172 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:23.172 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:23.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:23.173 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:23.592 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 02:06:24.063 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 02:06:24.533 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 02:06:25.004 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 02:06:25.478 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 02:06:25.950 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 02:06:26.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:26.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:26.176 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:26.177 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:26.189 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:26.189 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:26.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:26.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:26.192 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:26.192 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:26.192 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:26.192 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:26.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:26.242 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:26.243 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:26.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:26.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:26.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:26.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:26.417 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:26.417 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:26.422 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 02:06:26.434 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:26.434 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:26.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:26.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:26.436 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:26.436 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:26.436 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:26.436 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:26.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:26.479 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:26.480 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:26.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:26.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:26.893 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 02:06:27.367 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 02:06:27.839 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 02:06:28.311 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 02:06:28.782 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 02:06:29.253 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 02:06:29.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:29.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:29.486 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:29.487 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:29.505 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:29.505 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:29.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:29.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:29.506 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:29.507 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:29.507 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:29.507 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:29.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:29.542 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:29.543 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:29.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:29.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:29.723 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 02:06:30.194 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 02:06:30.665 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 02:06:31.139 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 02:06:31.611 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 02:06:32.083 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 02:06:32.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:32.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:32.550 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:32.550 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:32.554 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 02:06:32.568 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:32.568 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:32.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:32.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:32.569 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:32.569 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:32.570 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:32.570 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:32.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:32.609 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:32.609 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:32.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:32.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:32.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:32.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:32.783 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:32.783 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:32.799 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:32.799 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:32.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:32.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:32.800 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:32.800 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:32.800 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:32.800 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:32.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:32.842 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:32.842 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:32.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:32.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:33.024 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 02:06:33.495 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 02:06:33.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:33.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:33.536 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:33.536 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:33.553 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:33.554 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:33.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:33.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:33.555 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:33.555 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:33.555 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:33.555 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:33.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:33.596 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:33.597 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:33.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:33.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:33.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:33.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:33.653 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:33.653 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:33.670 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:33.670 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:33.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:33.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:33.672 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:33.672 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:33.672 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:33.672 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:33.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:33.677 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:33.677 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:33.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:33.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:33.966 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 02:06:34.437 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 02:06:34.910 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 02:06:35.383 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 02:06:35.855 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-06 02:06:36.326 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-06 02:06:36.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:36.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:36.684 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:36.684 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:36.700 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:36.701 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:36.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:36.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:36.702 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:36.702 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:36.702 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:36.702 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:36.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:36.755 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:36.756 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:36.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:36.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:36.799 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-06 02:06:36.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:36.950 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:36.951 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:36.951 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:36.967 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:36.967 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:36.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:36.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:36.968 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:36.969 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:36.969 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:36.969 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:36.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:36.978 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:36.978 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:36.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:36.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:37.272 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-06 02:06:37.744 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-06 02:06:38.217 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-06 02:06:38.689 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-06 02:06:39.161 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-06 02:06:39.632 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-06 02:06:39.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:39.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:39.985 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:39.985 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:40.004 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:40.004 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:40.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:40.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:40.005 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:40.005 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:40.005 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:40.005 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:40.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:40.062 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:40.062 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:40.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:40.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:40.106 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-06 02:06:40.578 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-06 02:06:41.050 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-06 02:06:41.521 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-06 02:06:41.995 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-06 02:06:42.467 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-06 02:06:42.939 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-06 02:06:43.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:43.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:43.070 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:43.070 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:43.090 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:43.090 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:43.090 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:43.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:43.092 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:43.092 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:43.092 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:43.092 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:43.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:43.133 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:43.134 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:43.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:43.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:43.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:43.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:43.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:43.330 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:43.344 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:43.344 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:43.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:43.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:43.345 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:43.345 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:43.345 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:43.345 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:43.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:43.356 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:43.356 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:43.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:43.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:43.409 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-06 02:06:43.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:43.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:43.876 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:43.877 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:43.881 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-06 02:06:43.883 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:06:43.883 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:06:43.883 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:06:43.883 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:06:43.884 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:06:43.884 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:06:43.884 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:06:43.884 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:06:43.884 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:06:43.884 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:06:43.884 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:06:48.889 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:06:48.889 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:06:48.889 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:06:48.889 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:06:48.889 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:06:48.889 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:06:48.899 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:06:48.901 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:06:48.901 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:06:48.901 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:06:48.902 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:06:48.905 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:06:48.905 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:06:48.905 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:06:48.906 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:06:48.906 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:06:48.906 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:06:48.907 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:06:48.907 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:06:48.907 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:06:48.907 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:06:48.907 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:06:48.907 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:06:48.908 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:06:48.908 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:06:48.908 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:06:48.908 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:06:48.908 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:06:48.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:06:48.910 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:06:48.910 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:06:48.910 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:06:48.911 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:06:48.911 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:06:48.911 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:06:48.911 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:06:48.911 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:06:48.911 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:06:48.915 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:06:48.915 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:06:48.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:06:48.915 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:06:48.915 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:06:48.915 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:06:48.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:06:48.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:06:48.915 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:06:48.916 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:06:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:06:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:06:48.916 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:06:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:06:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:06:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:06:48.916 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:06:48.916 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:06:48.916 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:06:48.916 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:06:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:06:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:06:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:06:48.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:06:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:06:48.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:06:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:06:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:06:48.916 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:06:48.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:06:48.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:06:48.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:06:48.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:06:48.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:06:48.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:06:48.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:06:48.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:06:48.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:06:48.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:06:48.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:06:48.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:06:48.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:06:48.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:06:48.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:06:48.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:06:48.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:06:48.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:06:48.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:06:48.921 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:06:49.397 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:06:49.446 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:06:49.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:49.449 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:06:49.450 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:06:49.474 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:49.475 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:49.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:49.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:49.479 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:49.479 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:49.479 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:49.479 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:49.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:49.497 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:49.497 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:49.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:49.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:49.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:49.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:49.558 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:49.558 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:49.574 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:49.575 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:49.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:49.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:49.576 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:49.576 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:49.576 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:49.576 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:49.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:49.580 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:49.580 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:49.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:49.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:49.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:49.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:49.677 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:49.677 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:49.699 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:49.699 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:49.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:49.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:49.701 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:49.701 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:49.701 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:49.701 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:49.727 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:49.732 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:49.733 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:49.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:49.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:49.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:49.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:49.794 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:49.794 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:49.812 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:49.812 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:49.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:49.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:49.814 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:49.814 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:49.814 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:49.814 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:49.864 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:06:49.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:49.874 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:49.874 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:49.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:49.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:49.920 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:06:49.920 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:06:49.920 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:06:49.921 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:06:49.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:49.950 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:49.951 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:49.951 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:49.961 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:06:49.961 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:06:49.962 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:06:49.962 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:06:49.965 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:06:49.966 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:06:49.966 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:06:49.966 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:06:49.966 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:06:49.966 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:06:49.966 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:06:49.967 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=228 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:06:49.967 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=228 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:06:49.967 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=228 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:06:49.967 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=228 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:06:49.967 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=228 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:06:49.967 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=228 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:06:54.970 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:06:54.970 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:06:54.970 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:06:54.970 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:06:54.970 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:06:54.970 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:06:54.975 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:06:54.977 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:06:54.977 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:06:54.977 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:06:54.977 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:06:54.981 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:06:54.981 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:06:54.982 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:06:54.982 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:06:54.982 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:06:54.982 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:06:54.983 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:06:54.983 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:06:54.983 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:06:54.984 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:06:54.984 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:06:54.984 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:06:54.984 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:06:54.985 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:06:54.985 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:06:54.985 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:06:54.985 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:06:54.985 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:06:54.987 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:06:54.987 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:06:54.987 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:06:54.987 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:06:54.987 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:06:54.987 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:06:54.987 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:06:54.987 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:06:54.988 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:06:54.991 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:06:54.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:06:54.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:06:54.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:06:54.991 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:06:54.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:06:54.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:06:54.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:06:54.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:06:54.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:06:54.992 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:06:54.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:06:54.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:06:54.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:06:54.992 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:06:54.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:06:54.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:06:54.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:06:54.992 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:06:54.992 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:06:54.992 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:06:54.992 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:06:54.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:06:54.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:06:54.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:06:54.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:06:54.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:06:54.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:06:54.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:06:54.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:06:54.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:06:54.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:06:54.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:06:54.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:06:54.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:06:54.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:06:54.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:06:54.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:06:54.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:06:54.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:06:54.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:06:54.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:06:54.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:06:54.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:06:54.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:06:54.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:06:54.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:06:54.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:06:54.997 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:06:55.475 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:06:55.518 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:06:55.521 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:06:55.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:55.523 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:06:55.540 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:55.541 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:55.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:55.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:55.547 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:55.547 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:55.547 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:55.547 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:55.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:55.579 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:55.579 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:55.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:55.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:55.948 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:06:55.994 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:06:55.995 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:06:55.995 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:06:55.995 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:06:56.419 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:06:56.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:56.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:56.439 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:56.440 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:56.457 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:56.457 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:56.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:56.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:56.458 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:56.458 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:56.458 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:56.458 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:56.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:56.462 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:56.462 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:56.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:56.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:56.890 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:06:56.995 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:06:56.996 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:06:56.996 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:06:56.996 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:06:57.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:57.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:57.160 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:57.160 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:57.173 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:57.174 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:57.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:57.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:57.175 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:57.175 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:57.175 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:57.175 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:57.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:57.225 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:57.226 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:57.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:57.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:57.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:57.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:57.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:57.330 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:57.349 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:57.349 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:57.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:06:57.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:57.351 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:57.351 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:57.351 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:06:57.351 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:06:57.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:57.357 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:06:57.357 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:06:57.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:57.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:57.362 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:06:57.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:06:57.754 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:06:57.755 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:06:57.755 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:06:57.766 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:06:57.766 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:06:57.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:06:57.767 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:06:57.768 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:06:57.768 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:06:57.768 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:06:57.768 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:06:57.768 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:06:57.768 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:06:57.768 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:07:02.773 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:07:02.773 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:07:02.773 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:07:02.773 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:07:02.773 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:07:02.773 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:07:02.780 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:07:02.780 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:07:02.780 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:07:02.781 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:07:02.781 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:07:02.785 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:07:02.785 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:07:02.786 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:07:02.786 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:07:02.786 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:07:02.786 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:07:02.787 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:07:02.787 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:07:02.788 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:02.790 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:07:02.790 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:07:02.791 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:07:02.791 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:07:02.791 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:07:02.791 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:07:02.792 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:07:02.792 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:07:02.792 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:02.794 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:07:02.794 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:07:02.794 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:07:02.794 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:07:02.794 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:07:02.794 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:07:02.794 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:07:02.794 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:07:02.795 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:02.798 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:07:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:07:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:07:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:07:02.798 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:07:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:07:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:07:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:07:02.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:07:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:02.798 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:07:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:02.798 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:02.798 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:07:02.798 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:07:02.798 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:07:02.799 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:02.803 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:07:03.281 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:07:03.321 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:07:03.323 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:07:03.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:03.325 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:07:03.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:03.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:03.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:03.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:03.355 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:03.355 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:03.355 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:03.355 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:03.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:03.381 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:03.381 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:03.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:03.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:03.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:03.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:03.553 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:03.553 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:03.570 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:03.570 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:03.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:03.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:03.572 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:03.572 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:03.572 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:03.572 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:03.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:03.619 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:03.620 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:03.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:03.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:03.749 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:07:03.802 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:03.802 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:03.802 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:03.802 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:03.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:03.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:03.896 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:03.896 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:03.916 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:03.916 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:03.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:03.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:03.918 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:03.918 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:03.918 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:03.918 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:03.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:03.935 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:03.935 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:03.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:03.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:04.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:04.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:04.214 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:04.214 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:04.220 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:07:04.230 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:04.230 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:04.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:04.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:04.232 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:04.232 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:04.232 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:04.232 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:04.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:04.274 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:04.274 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:04.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:04.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:04.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:04.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:04.612 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:04.612 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:04.622 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:04.623 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:04.623 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:04.623 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:04.625 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:07:04.625 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:07:04.625 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:07:04.625 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:07:04.625 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:07:04.625 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:07:04.625 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:07:04.625 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=396 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:07:04.625 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=396 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:07:04.625 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=396 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:07:04.625 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=396 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:07:04.625 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=396 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:07:04.625 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=396 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:07:04.625 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=396 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:07:04.625 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=396 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:07:09.629 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:07:09.630 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:07:09.630 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:07:09.630 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:07:09.630 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:07:09.630 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:07:09.637 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:07:09.638 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:07:09.638 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:07:09.638 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:07:09.639 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:07:09.641 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:07:09.641 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:07:09.641 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:07:09.641 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:07:09.641 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:07:09.641 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:07:09.642 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:07:09.642 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:07:09.642 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:09.644 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:07:09.644 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:07:09.645 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:07:09.645 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:07:09.645 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:07:09.645 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:07:09.645 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:07:09.645 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:07:09.645 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:09.648 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:07:09.648 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:07:09.649 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:07:09.649 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:07:09.649 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:07:09.649 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:07:09.649 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:07:09.649 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:07:09.649 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:09.653 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:07:09.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:07:09.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:07:09.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:07:09.653 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:07:09.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:07:09.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:07:09.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:09.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:07:09.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:07:09.654 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:07:09.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:09.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:09.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:09.654 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:09.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:09.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:09.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:09.654 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:07:09.654 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:07:09.654 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:07:09.654 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:07:09.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:09.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:09.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:09.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:07:09.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:09.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:09.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:09.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:09.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:09.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:09.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:09.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:09.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:09.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:09.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:09.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:09.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:09.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:09.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:09.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:09.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:09.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:09.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:09.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:09.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:09.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:09.659 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:07:10.137 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:07:10.183 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:07:10.186 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:07:10.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:10.188 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:07:10.213 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:10.213 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:10.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:10.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:10.217 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:10.218 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:10.218 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:10.218 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:10.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:10.238 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:10.239 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:10.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:10.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:10.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:10.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:10.408 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:10.409 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:10.426 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:10.426 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:10.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:10.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:10.427 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:10.427 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:10.427 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:10.427 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:10.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:10.476 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:10.476 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:10.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:10.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:10.610 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:07:10.658 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:10.658 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:10.658 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:10.659 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:10.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:10.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:10.755 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:10.755 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:10.772 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:10.773 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:10.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:10.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:10.774 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:10.774 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:10.775 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:10.775 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:10.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:10.798 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:10.798 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:10.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:10.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:11.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:11.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:11.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:11.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:11.082 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:07:11.094 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:11.094 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:11.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:11.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:11.095 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:11.096 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:11.096 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:11.096 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:11.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:11.136 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:11.136 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:11.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:11.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:11.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:11.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:11.472 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:11.472 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:11.481 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:11.481 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:11.481 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:11.481 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:11.484 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:07:11.484 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:07:11.484 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:07:11.484 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:07:11.484 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:07:11.484 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:07:11.484 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:07:16.488 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:07:16.489 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:07:16.489 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:07:16.489 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:07:16.489 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:07:16.489 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:07:16.492 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:07:16.492 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:07:16.493 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:07:16.493 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:07:16.493 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:07:16.495 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:07:16.495 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:07:16.495 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:07:16.495 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:07:16.496 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:07:16.496 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:07:16.496 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:07:16.496 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:07:16.496 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:16.498 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:07:16.498 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:07:16.499 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:07:16.499 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:07:16.499 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:07:16.499 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:07:16.499 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:07:16.499 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:07:16.499 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:16.501 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:07:16.501 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:07:16.501 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:07:16.502 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:07:16.502 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:07:16.502 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:07:16.502 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:07:16.502 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:07:16.502 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:16.506 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:07:16.506 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:07:16.506 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:07:16.506 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:07:16.506 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:07:16.506 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:07:16.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:07:16.506 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:16.506 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:07:16.506 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:07:16.506 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:07:16.506 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:16.506 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:16.506 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:16.506 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:16.506 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:16.506 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:16.506 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:16.506 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:07:16.506 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:07:16.506 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:07:16.507 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:07:16.507 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:16.507 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:16.507 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:16.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:07:16.507 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:16.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:16.507 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:16.507 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:16.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:16.507 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:16.507 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:16.507 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:16.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:16.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:16.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:16.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:16.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:16.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:16.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:16.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:16.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:16.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:16.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:16.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:16.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:16.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:16.511 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:07:16.988 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:07:17.035 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:07:17.039 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:07:17.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:17.041 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:07:17.067 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:17.067 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:17.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:17.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:17.071 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:17.072 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:17.072 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:17.072 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:17.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:17.092 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:17.093 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:17.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:17.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:17.461 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:07:17.511 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:17.511 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:17.511 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:17.512 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:17.934 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:07:18.407 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:07:18.512 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:18.513 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:18.513 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:18.513 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:18.879 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:07:18.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:18.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:18.927 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:18.927 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:18.945 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:18.945 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:18.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:18.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:18.946 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:18.946 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:18.946 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:18.946 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:18.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:18.978 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:18.978 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:18.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:18.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:19.350 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:07:19.514 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:19.514 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:19.514 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:19.514 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:19.824 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:07:20.295 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:07:20.515 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:20.516 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:20.516 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:20.516 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:20.768 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:07:21.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:21.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:21.096 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:21.096 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:21.115 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:21.115 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:21.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:21.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:21.117 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:21.117 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:21.117 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:21.117 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:21.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:21.144 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:21.145 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:21.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:21.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:21.241 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:07:21.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:21.517 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:21.517 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:21.517 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:21.713 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:07:22.186 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:07:22.656 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:07:22.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:22.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:22.698 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:22.698 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:22.717 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:22.717 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:22.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:22.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:22.720 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:22.720 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:22.720 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:22.720 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:22.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:22.756 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:22.756 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:22.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:22.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:23.127 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:07:23.601 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:07:24.073 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:07:24.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:24.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:24.540 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:24.540 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:24.545 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:07:24.549 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:24.549 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:24.549 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:24.550 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:24.552 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:07:24.552 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:07:24.552 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:07:24.552 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:07:24.552 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:07:24.552 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:07:24.552 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:07:29.557 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:07:29.557 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:07:29.557 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:07:29.557 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:07:29.557 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:07:29.557 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:07:29.560 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:07:29.560 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:07:29.560 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:07:29.560 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:07:29.560 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:07:29.561 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:07:29.561 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:07:29.561 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:07:29.561 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:07:29.561 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:07:29.561 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:07:29.562 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:07:29.562 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:07:29.562 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:29.562 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:07:29.562 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:07:29.562 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:07:29.562 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:07:29.562 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:07:29.562 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:07:29.562 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:07:29.562 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:07:29.562 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:29.564 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:07:29.564 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:07:29.564 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:07:29.564 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:07:29.564 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:07:29.564 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:07:29.564 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:07:29.564 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:07:29.564 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:07:29.566 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:07:29.566 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:07:29.566 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:29.571 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:07:30.049 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:07:30.091 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:07:30.094 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:07:30.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:30.096 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:07:30.115 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:30.115 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:30.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:30.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:30.121 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:30.121 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:30.122 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:30.122 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:30.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:30.152 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:30.153 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:30.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:30.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:30.522 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:07:30.568 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:30.569 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:30.569 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:30.569 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:30.993 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:07:31.464 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:07:31.569 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:31.570 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:31.570 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:31.570 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:31.937 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:07:31.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:31.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:31.984 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:31.984 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:31.998 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:31.998 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:31.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:31.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:31.999 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:31.999 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:32.000 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:32.000 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:32.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:32.031 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:32.031 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:32.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:32.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:32.409 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:07:32.570 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:32.571 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:32.571 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:32.571 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:32.881 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:07:33.352 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:07:33.572 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:33.572 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:33.572 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:33.572 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:33.823 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:07:34.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:34.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:34.154 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:34.154 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:34.174 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:34.174 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:34.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:34.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:34.175 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:34.175 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:34.175 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:34.175 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:34.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:34.201 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:34.201 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:34.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:34.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:34.296 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:07:34.573 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:34.574 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:34.574 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:34.574 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:34.769 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:07:35.241 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:07:35.712 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:07:35.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:35.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:35.752 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:35.753 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:35.771 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:35.771 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:35.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:35.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:35.773 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:35.773 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:35.773 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:35.773 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:35.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:35.812 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:35.812 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:35.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:35.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:36.183 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:07:36.656 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:07:37.128 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:07:37.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:37.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:37.596 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:37.596 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:37.600 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:07:37.601 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:37.601 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:37.601 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:37.601 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:37.602 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:07:37.602 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:07:37.602 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:07:37.602 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:07:37.602 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:07:37.602 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:07:37.602 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:07:42.609 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:07:42.609 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:07:42.609 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:07:42.610 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:07:42.610 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:07:42.610 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:07:42.620 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:07:42.621 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:07:42.621 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:07:42.621 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:07:42.622 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:07:42.625 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:07:42.625 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:07:42.625 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:07:42.625 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:07:42.626 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:07:42.626 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:07:42.627 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:07:42.627 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:07:42.627 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:42.629 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:07:42.629 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:07:42.629 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:07:42.629 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:07:42.629 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:07:42.629 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:07:42.629 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:07:42.629 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:07:42.629 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:42.632 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:07:42.632 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:07:42.632 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:07:42.632 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:07:42.633 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:07:42.633 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:07:42.633 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:07:42.633 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:07:42.633 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:42.637 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:07:42.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:07:42.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:07:42.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:07:42.637 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:07:42.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:07:42.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:07:42.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:42.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:07:42.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:07:42.638 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:07:42.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:42.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:42.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:42.638 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:42.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:42.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:42.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:42.638 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:07:42.638 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:07:42.638 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:07:42.638 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:07:42.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:42.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:42.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:42.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:07:42.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:42.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:42.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:42.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:42.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:42.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:42.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:42.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:42.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:42.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:42.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:42.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:42.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:42.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:42.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:07:42.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:42.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:42.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:42.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:07:42.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:42.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:07:42.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:07:42.643 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:07:43.121 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:07:43.162 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:07:43.165 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:07:43.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:43.167 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:07:43.187 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:43.187 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:43.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:43.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:43.190 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:43.190 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:43.190 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:43.190 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:43.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:43.224 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:43.225 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:43.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:43.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:43.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:43.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:43.401 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:43.401 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:43.421 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:43.421 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:43.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:43.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:43.422 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:43.422 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:43.422 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:43.422 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:43.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:43.460 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:43.460 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:43.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:43.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:43.591 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:07:43.641 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:43.641 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:43.642 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:43.642 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:44.064 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:07:44.536 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:07:44.642 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:44.643 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:44.643 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:44.643 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:45.007 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:07:45.481 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:07:45.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:45.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:45.531 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:45.531 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:45.548 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:45.548 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:45.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:45.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:45.549 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:45.550 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:45.550 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:45.550 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:45.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:45.581 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:45.582 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:45.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:45.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:45.644 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:45.644 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:45.644 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:45.644 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:45.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:45.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:45.748 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:45.748 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:45.762 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:45.762 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:45.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:45.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:45.763 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:45.763 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:45.763 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:45.763 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:45.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:45.819 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:45.820 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:45.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:45.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:45.953 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:07:46.424 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:07:46.645 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:46.646 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:46.646 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:46.646 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:46.895 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:07:47.366 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:07:47.647 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:07:47.647 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:07:47.647 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:07:47.647 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:07:47.839 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:07:47.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:47.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:47.931 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:47.931 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:47.948 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:47.948 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:47.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:47.950 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:47.950 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:47.950 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:47.950 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:47.950 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:47.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:47.975 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:47.975 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:47.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:47.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:48.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:48.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:48.250 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:48.250 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:48.267 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:48.267 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:48.267 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:48.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:48.268 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:48.268 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:48.268 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:48.268 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:48.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:48.312 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:07:48.316 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:48.316 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:48.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:48.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:48.783 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:07:49.255 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:07:49.725 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:07:50.199 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:07:50.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:50.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:50.576 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:50.576 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:50.593 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:50.593 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:50.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:50.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:50.594 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:50.594 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:50.594 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:50.594 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:50.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:50.616 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:50.616 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:50.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:50.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:50.671 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:07:50.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:50.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:50.900 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:50.901 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:50.917 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:50.917 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:50.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:50.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:50.919 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:50.919 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:50.919 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:50.919 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:50.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:50.961 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:50.961 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:50.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:50.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:51.143 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:07:51.614 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:07:52.086 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:07:52.559 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:07:52.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:52.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:52.981 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:52.981 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:52.987 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:52.987 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:52.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:52.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:52.988 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:52.988 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:52.988 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:52.988 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:53.031 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:07:53.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:53.041 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:53.041 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:53.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:53.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:53.502 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:07:53.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:53.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:53.661 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:53.662 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:53.679 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:53.679 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:53.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:53.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:53.681 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:53.681 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:53.681 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:53.681 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:53.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:53.747 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:53.748 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:53.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:53.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:53.973 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:07:54.444 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:07:54.917 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:07:55.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:55.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:55.355 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:55.355 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:55.363 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:55.363 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:55.364 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:55.364 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:55.364 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:55.364 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:55.364 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:55.365 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:55.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:55.389 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:55.389 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:55.389 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:07:55.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:55.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:55.861 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:07:56.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:56.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:56.020 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:56.020 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:56.036 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:56.036 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:56.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:56.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:56.037 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:56.037 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:56.037 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:56.037 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:56.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:56.043 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:56.043 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:56.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:56.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:56.332 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:07:56.803 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:07:57.276 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:07:57.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:57.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:57.714 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:57.714 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:57.734 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:57.734 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:57.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:57.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:57.736 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:57.736 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:57.736 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:57.736 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:57.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:57.741 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:57.742 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:57.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:57.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:57.749 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:07:58.220 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:07:58.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:58.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:58.307 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:58.307 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:58.325 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:07:58.325 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:07:58.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:07:58.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:58.326 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:58.327 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:58.327 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:07:58.327 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:07:58.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:07:58.368 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:07:58.368 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:07:58.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:58.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:07:58.692 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:07:59.165 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:07:59.638 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:08:00.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:00.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:00.034 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:00.035 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:00.054 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:00.054 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:00.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:00.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:00.056 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:00.057 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:00.057 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:00.057 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:00.109 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:08:00.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:00.118 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:00.119 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:00.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:00.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:00.580 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:08:00.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:00.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:00.667 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:00.668 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:00.685 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:00.685 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:00.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:00.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:00.687 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:00.687 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:00.687 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:00.687 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:00.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:00.727 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:00.728 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:00.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:00.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:01.051 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:08:01.525 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:08:01.997 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:08:02.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:02.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:02.393 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:02.393 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:02.405 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:02.405 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:02.405 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:02.405 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:02.407 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:08:02.407 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:08:02.407 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:08:02.407 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:08:02.407 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:08:02.407 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:08:02.407 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:08:07.412 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:08:07.412 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:08:07.412 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:08:07.413 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:08:07.413 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:08:07.413 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:08:07.415 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:08:07.416 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:08:07.416 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:07.416 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:08:07.416 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:08:07.417 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:08:07.417 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:08:07.417 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:08:07.417 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:07.417 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:08:07.417 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:08:07.417 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:08:07.417 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:08:07.417 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:07.418 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:08:07.418 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:08:07.418 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:08:07.418 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:07.418 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:08:07.418 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:08:07.418 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:08:07.418 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:08:07.418 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:07.419 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:08:07.419 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:08:07.419 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:08:07.419 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:07.419 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:08:07.419 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:08:07.419 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:08:07.419 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:08:07.420 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:07.421 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:08:07.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:08:07.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:08:07.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:08:07.421 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:08:07.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:08:07.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:08:07.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:07.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:08:07.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:08:07.421 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:08:07.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:08:07.422 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:08:07.422 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:08:07.422 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:07.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:07.426 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:08:07.904 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:08:07.939 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:08:07.940 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:08:07.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:07.942 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:08:07.957 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:07.957 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:07.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:07.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:07.960 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:07.960 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:07.960 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:07.960 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:08.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:08.008 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:08.008 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:08.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:08.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:08.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:08.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:08.065 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:08.065 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:08.078 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:08.078 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:08.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:08.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:08.079 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:08.079 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:08.079 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:08.079 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:08.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:08.087 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:08.087 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:08.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:08.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:08.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:08.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:08.144 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:08.144 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:08.157 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:08.158 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:08.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:08.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:08.159 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:08.159 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:08.159 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:08.159 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:08.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:08.195 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:08.195 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:08.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:08.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:08.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:08.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:08.305 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:08.305 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:08.322 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:08.322 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:08.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:08.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:08.323 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:08.323 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:08.323 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:08.323 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:08.375 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:08:08.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:08.380 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:08.381 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:08.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:08.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:08.424 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:08.424 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:08.424 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:08.425 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:08.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:08.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:08.467 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:08.467 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:08.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:08.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:08.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:08.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:08.487 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:08.487 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:08.487 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:08.487 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:08.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:08.521 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:08.522 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:08.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:08.523 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:08.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:08.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:08.772 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:08.772 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:08.790 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:08.790 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:08.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:08.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:08.792 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:08.792 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:08.792 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:08.792 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:08.847 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:08:08.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:08.857 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:08.857 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:08.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:08.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:09.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:09.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:09.007 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:09.007 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:09.023 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:09.023 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:09.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:09.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:09.024 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:09.024 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:09.024 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:09.024 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:09.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:09.038 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:09.038 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:09.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:09.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:09.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:09.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:09.169 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:09.169 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:09.187 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:09.187 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:09.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:09.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:09.189 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:09.189 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:09.189 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:09.189 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:09.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:09.230 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:09.230 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:09.230 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:09.230 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:09.318 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:08:09.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:09.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:09.405 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:09.405 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:09.414 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:09.414 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:09.414 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:09.415 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:09.418 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:08:09.419 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:08:09.419 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:08:09.419 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:08:09.419 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:08:09.419 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:08:09.419 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:08:09.420 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=432 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:09.420 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=432 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:09.420 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=432 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:09.420 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=432 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:09.420 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=432 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:09.420 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=432 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:09.420 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=432 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:14.420 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:08:14.420 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:08:14.420 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:08:14.420 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:08:14.420 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:08:14.421 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:08:14.429 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:08:14.430 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:08:14.430 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:14.430 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:08:14.431 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:08:14.434 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:08:14.434 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:08:14.434 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:08:14.435 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:14.435 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:08:14.436 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:08:14.436 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:08:14.436 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:08:14.437 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:14.439 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:08:14.439 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:08:14.439 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:08:14.439 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:14.440 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:08:14.440 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:08:14.441 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:08:14.441 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:08:14.441 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:14.443 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:08:14.443 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:08:14.444 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:08:14.444 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:14.444 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:08:14.444 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:08:14.444 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:08:14.444 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:08:14.444 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:14.449 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:08:14.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:08:14.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:08:14.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:08:14.449 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:08:14.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:08:14.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:08:14.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:14.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:08:14.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:08:14.450 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:08:14.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:14.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:14.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:14.450 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:14.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:14.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:14.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:14.450 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:08:14.450 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:08:14.451 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:08:14.451 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:08:14.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:14.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:14.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:14.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:08:14.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:14.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:14.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:14.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:14.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:14.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:14.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:14.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:14.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:14.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:14.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:14.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:14.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:14.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:14.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:14.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:14.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:14.453 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:14.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:14.453 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:14.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:14.453 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:14.455 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:08:14.933 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:08:14.986 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:08:14.987 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:08:14.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:14.989 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:08:15.010 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:15.010 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:15.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:15.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:15.014 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:15.014 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:15.015 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:15.015 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:15.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:15.034 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:15.034 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:15.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:15.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:15.406 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:08:15.455 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:15.456 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:15.457 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:15.457 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:15.877 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:08:15.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:15.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:15.897 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:15.898 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:15.917 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:15.917 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:15.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:15.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:15.919 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:15.919 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:15.919 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:15.919 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:15.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:15.970 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:15.970 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:15.970 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:15.970 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:16.350 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:08:16.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:16.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:16.376 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:16.376 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:16.393 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:16.393 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:16.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:16.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:16.395 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:16.395 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:16.395 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:16.395 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:16.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:16.450 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:16.451 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:16.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:16.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:16.456 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:16.457 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:16.457 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:16.458 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:16.822 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:08:17.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:17.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:17.102 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:17.103 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:17.119 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:17.119 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:17.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:17.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:17.120 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:17.120 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:17.120 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:17.120 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:17.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:17.158 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:17.158 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:17.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:17.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:17.292 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:08:17.457 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:17.458 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:17.458 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:17.458 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:17.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:17.577 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:17.579 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:17.579 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:17.596 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:17.596 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:17.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:17.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:17.597 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:17.597 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:17.597 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:17.597 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:17.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:17.620 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:17.621 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:17.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:17.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:17.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:17.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:17.730 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:17.731 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:17.748 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:17.748 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:17.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:17.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:17.749 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:17.749 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:17.749 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:17.749 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:17.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:17.758 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:17.758 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:17.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:17.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:17.764 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:08:18.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:18.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:18.206 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:18.206 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:18.221 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:18.221 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:18.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:18.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:18.223 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:18.223 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:18.223 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:18.223 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:18.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:18.235 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:18.235 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:18.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:18.236 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:08:18.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:18.458 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:18.458 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:18.459 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:18.459 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:18.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:18.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:18.631 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:18.631 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:18.647 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:18.647 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:18.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:18.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:18.648 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:18.648 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:18.648 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:18.648 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:18.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:18.653 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:18.653 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:18.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:18.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:18.706 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:08:19.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:19.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:19.102 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:19.103 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:19.111 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:19.111 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:19.111 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:19.111 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:19.115 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:08:19.116 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:08:19.116 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:08:19.116 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:08:19.116 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:08:19.116 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:08:19.117 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:08:19.117 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1008 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:19.117 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1008 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:19.117 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1008 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:19.117 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1008 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:19.117 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1008 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:19.117 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1008 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:19.117 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1008 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:24.117 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:08:24.117 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:08:24.117 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:08:24.117 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:08:24.117 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:08:24.117 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:08:24.127 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:08:24.128 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:08:24.129 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:24.129 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:08:24.129 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:08:24.132 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:08:24.132 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:08:24.132 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:08:24.132 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:24.133 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:08:24.133 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:08:24.133 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:08:24.133 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:08:24.133 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:24.135 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:08:24.135 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:08:24.135 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:08:24.135 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:24.135 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:08:24.135 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:08:24.135 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:08:24.135 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:08:24.135 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:24.138 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:08:24.138 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:08:24.138 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:08:24.138 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:24.138 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:08:24.138 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:08:24.138 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:08:24.138 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:08:24.138 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:24.140 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:08:24.140 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:08:24.140 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:08:24.140 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:08:24.140 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:08:24.140 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:08:24.141 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:08:24.141 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:08:24.141 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:24.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:24.146 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:08:24.621 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:08:24.673 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:08:24.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:24.676 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:08:24.679 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:08:24.702 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:24.702 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:24.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:24.706 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:24.706 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:24.706 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:24.706 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:24.706 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:24.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:24.719 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:24.719 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:24.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:24.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:24.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:24.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:24.784 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:24.784 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:24.802 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:24.802 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:24.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:24.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:24.803 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:24.803 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:24.803 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:24.803 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:24.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:24.868 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:24.869 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:24.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:24.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:24.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:24.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:24.922 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:24.922 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:24.940 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:24.940 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:24.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:24.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:24.941 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:24.941 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:24.941 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:24.941 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:24.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:24.948 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:24.948 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:24.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:24.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:25.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:25.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:25.044 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:25.044 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:25.062 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:25.062 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:25.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:25.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:25.063 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:25.063 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:25.063 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:25.063 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:25.090 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:08:25.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:25.103 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:25.103 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:25.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:25.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:25.144 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:25.144 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:25.144 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:25.145 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:25.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:25.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:25.199 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:25.199 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:25.217 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:25.217 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:25.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:25.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:25.219 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:25.219 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:25.219 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:25.219 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:25.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:25.224 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:25.224 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:25.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:25.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:25.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:25.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:25.319 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:25.319 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:25.337 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:25.337 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:25.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:25.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:25.338 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:25.339 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:25.339 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:25.339 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:25.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:25.378 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:25.379 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:25.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:25.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:25.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:25.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:25.555 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:25.555 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:25.560 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:08:25.571 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:25.571 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:25.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:25.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:25.572 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:25.572 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:25.572 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:25.572 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:25.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:25.613 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:25.613 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:25.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:25.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:25.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:25.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:25.717 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:25.717 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:25.736 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:25.736 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:25.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:25.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:25.738 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:25.738 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:25.738 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:25.738 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:25.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:25.741 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:25.741 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:25.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:25.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:25.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:25.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:25.955 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:25.955 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:25.965 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:25.965 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:25.965 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:25.965 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:25.968 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:08:25.968 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:08:25.968 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:08:25.968 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:08:25.968 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:08:25.968 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:08:25.968 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:08:30.972 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:08:30.972 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:08:30.972 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:08:30.972 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:08:30.972 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:08:30.972 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:08:30.980 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:08:30.981 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:08:30.981 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:30.982 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:08:30.982 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:08:30.986 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:08:30.986 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:08:30.986 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:08:30.986 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:30.986 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:08:30.987 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:08:30.987 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:08:30.987 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:08:30.987 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:30.991 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:08:30.991 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:08:30.991 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:08:30.991 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:30.991 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:08:30.992 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:08:30.992 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:08:30.992 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:08:30.992 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:30.996 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:08:30.997 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:08:30.997 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:08:30.997 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:30.997 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:08:30.997 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:08:30.997 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:08:30.997 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:08:30.997 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:31.004 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:08:31.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:08:31.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:08:31.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:08:31.004 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:08:31.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:08:31.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:08:31.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:31.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:08:31.005 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:08:31.005 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:08:31.005 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:31.005 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:31.005 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:31.005 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:31.005 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:31.005 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:31.005 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:31.005 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:08:31.005 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:08:31.005 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:08:31.005 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:08:31.005 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:31.005 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:31.005 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:31.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:08:31.006 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:31.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:31.006 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:31.006 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:31.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:31.006 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:31.006 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:31.006 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:31.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:31.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:31.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:31.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:31.007 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:31.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:31.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:31.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:31.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:31.007 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:31.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:31.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:31.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:31.007 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:31.010 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:08:31.481 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:08:31.542 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:08:31.544 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:08:31.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:31.547 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:08:31.571 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:31.571 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:31.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:31.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:31.575 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:31.575 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:31.575 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:31.575 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:31.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:31.631 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:31.631 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:31.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:31.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:31.953 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:08:32.011 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:32.011 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:32.011 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:32.013 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:32.425 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:08:32.898 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:08:32.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:32.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:32.929 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:32.929 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:32.946 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:32.946 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:32.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:32.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:32.947 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:32.947 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:32.947 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:32.947 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:32.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:32.996 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:32.996 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:32.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:32.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:33.012 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:33.012 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:33.012 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:33.014 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:33.371 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:08:33.843 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:08:33.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:33.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:33.895 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:33.895 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:33.912 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:33.912 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:33.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:33.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:33.914 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:33.914 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:33.914 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:33.914 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:33.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:33.936 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:33.937 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:33.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:33.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:34.013 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:34.013 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:34.013 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:34.015 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:34.314 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:08:34.787 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:08:35.014 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:35.015 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:35.015 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:35.015 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:35.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:35.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:35.094 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:35.094 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:35.111 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:35.111 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:35.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:35.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:35.113 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:35.113 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:35.113 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:35.113 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:35.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:35.163 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:35.163 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:35.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:35.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:35.260 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:08:35.732 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:08:36.016 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:36.016 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:36.016 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:36.016 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:36.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:36.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:36.061 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:36.061 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:36.078 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:36.078 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:36.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:36.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:36.079 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:36.079 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:36.080 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:36.080 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:36.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:36.113 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:36.113 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:36.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:36.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:36.203 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:08:36.677 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:08:36.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:36.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:36.721 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:36.721 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:36.736 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:36.736 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:36.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:36.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:36.737 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:36.737 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:36.737 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:36.737 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:36.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:36.778 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:36.778 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:36.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:36.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:37.149 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:08:37.620 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:08:37.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:37.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:37.662 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:37.663 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:37.683 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:37.683 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:37.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:37.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:37.684 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:37.684 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:37.685 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:37.685 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:37.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:37.717 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:37.718 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:37.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:37.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:38.091 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:08:38.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:38.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:38.560 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:38.560 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:38.565 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:08:38.583 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:38.583 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:38.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:38.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:38.587 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:38.587 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:38.587 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:38.587 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:38.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:38.616 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:38.616 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:38.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:38.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:39.037 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:08:39.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:39.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:39.506 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:39.506 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:39.509 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:08:39.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:39.517 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:39.517 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:39.517 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:39.520 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:08:39.520 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:08:39.520 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:08:39.520 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:08:39.520 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:08:39.520 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:08:39.520 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:08:39.520 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1840 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:39.520 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1840 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:39.520 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1840 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:39.520 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1840 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:44.528 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:08:44.529 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:08:44.529 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:08:44.529 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:08:44.529 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:08:44.529 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:08:44.543 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:08:44.544 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:08:44.544 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:44.544 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:08:44.544 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:08:44.546 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:08:44.547 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:08:44.547 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:08:44.547 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:44.547 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:08:44.547 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:08:44.548 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:08:44.548 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:08:44.548 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:44.549 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:08:44.549 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:08:44.549 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:08:44.549 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:44.549 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:08:44.549 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:08:44.549 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:08:44.549 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:08:44.549 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:44.551 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:08:44.551 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:08:44.551 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:08:44.551 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:44.551 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:08:44.551 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:08:44.551 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:08:44.551 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:08:44.551 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:44.553 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:08:44.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:08:44.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:08:44.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:08:44.553 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:08:44.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:08:44.554 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:08:44.554 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:08:44.554 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:44.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:44.558 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:08:45.036 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:08:45.075 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:08:45.076 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:08:45.077 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:08:45.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:45.095 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:45.095 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:45.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:45.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:45.099 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:45.099 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:45.099 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:45.099 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:45.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:45.140 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:45.140 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:45.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:45.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:45.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:45.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:45.259 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:45.259 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:45.276 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:45.276 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:45.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:45.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:45.278 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:45.278 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:45.278 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:45.278 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:45.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:45.329 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:45.329 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:45.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:45.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:45.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:45.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:45.498 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:45.499 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:45.507 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:08:45.514 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:45.514 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:45.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:45.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:45.516 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:45.516 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:45.516 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:45.516 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:45.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:45.556 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:45.556 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:45.556 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:45.556 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:45.558 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:45.558 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:45.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:45.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:45.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:45.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:45.734 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:45.734 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:45.751 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:45.751 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:45.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:45.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:45.753 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:45.753 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:45.753 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:45.753 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:45.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:45.794 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:45.794 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:45.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:45.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:45.978 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:08:46.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:46.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:46.138 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:46.138 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:46.147 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:46.147 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:46.147 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:46.147 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:46.152 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:08:46.152 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:08:46.153 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:08:46.153 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:08:46.153 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:08:46.153 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:08:46.153 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:08:46.153 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=345 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:46.154 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=345 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:46.154 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=345 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:46.154 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=345 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:46.154 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=345 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:46.154 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=345 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:46.154 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=345 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:46.154 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=345 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:51.155 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:08:51.155 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:08:51.155 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:08:51.155 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:08:51.155 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:08:51.155 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:08:51.160 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:08:51.161 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:08:51.161 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:51.162 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:08:51.162 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:08:51.165 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:08:51.165 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:08:51.165 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:08:51.165 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:51.165 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:08:51.165 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:08:51.166 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:08:51.166 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:08:51.166 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:51.169 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:08:51.169 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:08:51.169 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:08:51.169 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:51.170 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:08:51.170 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:08:51.170 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:08:51.170 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:08:51.170 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:51.172 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:08:51.172 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:08:51.173 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:08:51.173 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:51.173 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:08:51.173 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:08:51.173 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:08:51.173 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:08:51.173 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:51.177 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:08:51.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:08:51.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:08:51.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:08:51.178 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:08:51.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:08:51.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:08:51.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:51.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:08:51.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:08:51.178 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:08:51.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:51.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:51.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:51.178 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:51.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:51.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:51.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:51.178 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:08:51.178 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:08:51.178 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:08:51.179 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:08:51.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:51.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:51.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:51.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:08:51.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:51.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:51.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:51.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:51.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:51.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:51.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:51.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:51.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:51.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:51.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:51.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:51.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:51.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:51.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:51.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:51.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:51.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:51.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:51.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:51.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:51.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:51.183 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:08:51.662 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:08:51.710 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:08:51.713 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:08:51.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:51.715 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:08:51.736 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:51.736 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:51.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:51.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:51.741 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:51.741 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:51.742 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:51.742 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:51.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:51.766 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:51.766 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:51.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:51.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:51.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:51.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:51.866 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:51.867 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:51.884 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:51.884 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:51.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:51.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:51.885 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:51.885 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:51.886 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:51.886 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:51.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:51.898 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:51.898 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:51.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:51.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:52.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:52.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:52.048 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:52.048 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:52.069 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:52.069 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:52.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:52.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:52.071 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:52.072 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:52.072 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:52.072 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:52.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:52.083 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:52.084 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:52.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:52.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:52.134 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:08:52.182 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:52.182 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:52.182 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:52.184 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:52.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:52.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:52.363 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:52.364 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:52.382 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:52.382 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:52.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:52.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:52.384 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:52.384 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:52.384 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:52.384 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:52.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:52.425 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:52.426 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:52.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:52.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:52.605 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:08:52.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:52.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:52.762 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:52.762 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:52.771 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:52.771 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:52.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:52.772 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:52.773 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:08:52.773 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:08:52.773 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:08:52.773 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:08:52.773 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:08:52.773 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:08:52.773 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:08:57.778 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:08:57.779 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:08:57.779 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:08:57.779 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:08:57.779 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:08:57.779 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:08:57.789 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:08:57.790 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:08:57.790 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:57.790 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:08:57.790 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:08:57.792 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:08:57.792 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:08:57.792 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:08:57.792 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:57.793 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:08:57.793 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:08:57.793 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:08:57.793 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:08:57.793 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:57.794 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:08:57.794 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:08:57.794 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:08:57.794 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:57.794 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:08:57.794 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:08:57.794 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:08:57.794 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:08:57.794 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:57.796 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:08:57.796 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:08:57.796 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:08:57.796 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:08:57.796 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:08:57.796 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:08:57.796 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:08:57.796 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:08:57.796 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:57.798 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:08:57.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:08:57.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:08:57.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:08:57.798 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:08:57.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:08:57.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:08:57.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:57.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:08:57.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:08:57.798 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:08:57.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:57.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:57.798 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:57.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:57.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:57.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:57.798 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:08:57.798 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:08:57.798 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:08:57.798 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:08:57.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:57.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:57.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:57.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:08:57.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:57.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:57.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:57.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:57.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:57.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:57.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:57.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:57.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:57.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:57.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:57.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:57.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:08:57.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:57.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:57.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:57.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:57.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:57.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:08:57.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:57.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:57.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:08:57.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:08:57.803 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:08:58.282 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:08:58.324 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:08:58.326 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:08:58.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:58.328 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:08:58.354 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:58.354 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:58.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:58.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:58.359 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:58.359 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:58.360 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:58.360 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:58.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:58.386 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:58.386 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:58.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:58.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:58.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:58.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:58.486 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:58.486 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:58.506 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:58.506 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:58.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:58.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:58.508 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:58.508 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:58.508 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:58.508 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:58.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:58.516 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:58.516 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:58.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:58.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:58.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:58.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:58.665 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:58.665 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:58.682 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:58.682 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:58.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:58.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:58.683 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:58.683 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:58.683 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:58.683 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:58.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:58.706 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:58.707 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:58.707 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:58.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:58.749 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:08:58.800 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:58.801 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:58.801 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:58.801 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:58.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:58.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:58.978 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:58.978 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:58.997 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:58.997 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:58.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:08:58.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:58.999 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:58.999 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:58.999 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:08:58.999 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:08:59.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:59.032 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:08:59.032 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:08:59.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:59.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:59.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:08:59.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:08:59.142 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:08:59.142 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:08:59.151 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:08:59.151 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:08:59.152 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:08:59.152 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:08:59.155 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:08:59.156 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:08:59.156 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:08:59.156 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:08:59.156 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:08:59.157 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:08:59.157 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:08:59.157 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=294 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:59.157 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:59.157 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:59.157 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:59.157 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:59.157 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:08:59.157 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:04.159 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:09:04.159 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:09:04.159 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:09:04.179 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:09:04.179 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:09:04.180 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:09:04.184 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:09:04.186 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:09:04.187 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:04.187 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:09:04.188 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:09:04.195 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:09:04.195 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:09:04.196 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:09:04.196 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:04.197 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:09:04.197 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:09:04.198 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:09:04.198 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:09:04.199 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:04.201 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:09:04.202 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:09:04.202 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:09:04.202 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:04.203 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:09:04.203 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:09:04.204 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:09:04.204 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:09:04.205 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:04.206 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:09:04.207 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:09:04.207 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:09:04.207 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:04.207 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:09:04.208 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:09:04.208 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:09:04.208 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:09:04.208 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:04.212 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:09:04.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:09:04.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:09:04.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:09:04.212 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:09:04.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:09:04.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:09:04.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:04.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:09:04.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:09:04.212 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:09:04.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:04.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:04.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:04.212 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:04.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:04.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:04.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:04.213 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:09:04.213 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:09:04.213 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:09:04.213 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:09:04.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:04.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:04.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:04.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:09:04.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:04.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:04.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:04.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:04.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:04.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:04.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:04.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:04.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:04.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:04.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:04.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:04.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:04.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:04.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:04.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:04.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:04.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:04.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:04.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:04.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:04.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:04.217 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:09:04.694 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:09:04.746 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:09:04.748 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:09:04.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:04.750 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:09:04.770 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:04.770 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:04.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:09:04.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:04.776 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:04.777 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:04.777 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:09:04.777 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:09:04.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:04.796 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:04.797 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:04.797 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:04.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:04.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:04.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:04.898 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:04.899 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:04.919 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:04.919 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:04.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:09:04.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:04.922 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:04.923 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:04.923 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:09:04.923 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:09:04.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:04.929 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:04.930 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:04.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:04.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:05.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:05.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:05.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:05.080 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:05.092 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:05.092 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:05.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:09:05.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:05.093 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:05.093 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:05.093 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:09:05.093 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:09:05.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:05.118 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:05.118 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:05.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:05.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:05.166 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:09:05.216 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:05.217 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:05.217 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:05.218 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:05.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:05.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:05.397 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:05.397 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:05.419 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:05.419 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:05.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:09:05.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:05.421 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:05.422 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:05.422 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:09:05.422 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:09:05.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:05.456 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:05.456 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:05.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:05.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:05.637 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:09:05.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:05.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:05.794 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:05.794 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:05.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:05.799 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:05.799 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:05.799 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:05.800 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:09:05.800 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:09:05.800 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:09:05.800 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:09:05.800 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:09:05.800 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:09:05.800 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:09:10.806 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:09:10.807 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:09:10.807 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:09:10.807 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:09:10.807 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:09:10.807 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:09:10.814 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:09:10.814 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:09:10.814 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:10.814 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:09:10.814 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:09:10.817 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:09:10.817 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:09:10.817 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:09:10.817 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:10.817 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:09:10.817 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:09:10.817 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:09:10.817 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:09:10.817 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:10.820 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:09:10.820 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:09:10.821 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:09:10.821 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:10.821 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:09:10.821 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:09:10.821 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:09:10.821 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:09:10.821 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:10.824 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:09:10.824 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:09:10.824 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:09:10.824 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:10.825 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:09:10.825 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:09:10.825 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:09:10.825 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:09:10.825 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:10.830 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:09:10.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:09:10.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:09:10.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:09:10.830 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:09:10.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:09:10.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:09:10.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:10.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:09:10.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:09:10.830 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:09:10.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:10.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:10.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:10.830 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:10.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:10.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:10.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:10.831 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:09:10.831 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:09:10.831 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:09:10.831 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:09:10.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:10.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:10.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:10.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:09:10.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:10.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:10.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:10.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:10.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:10.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:10.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:10.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:10.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:10.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:10.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:10.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:10.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:10.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:10.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:10.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:10.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:10.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:10.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:10.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:10.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:10.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:10.836 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:09:11.313 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:09:11.367 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:09:11.370 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:09:11.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:11.372 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:09:11.394 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:11.394 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:11.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:09:11.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:11.402 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:11.402 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:11.402 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:09:11.403 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:09:11.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:11.463 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:11.464 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:11.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:11.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:11.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:11.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:11.774 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:11.774 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:11.785 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:09:11.792 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:11.792 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:11.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:09:11.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:11.794 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:11.794 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:11.794 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:09:11.794 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:09:11.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:11.835 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:11.836 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:11.836 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:11.837 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:11.840 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:11.840 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:11.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:11.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:12.256 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:09:12.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:12.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:12.356 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:12.356 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:12.375 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:12.375 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:12.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:09:12.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:12.378 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:12.378 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:12.378 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:09:12.378 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:09:12.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:12.397 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:12.397 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:12.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:12.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:12.727 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:09:12.836 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:12.837 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:12.837 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:12.837 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:13.200 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:09:13.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:13.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:13.356 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:13.356 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:13.374 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:13.374 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:13.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:09:13.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:13.377 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:13.377 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:13.377 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:09:13.377 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:09:13.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:13.437 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:13.438 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:13.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:13.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:13.673 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:09:13.837 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:13.838 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:13.838 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:13.838 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:14.145 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:09:14.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:14.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:14.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:14.465 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:14.470 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:14.470 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:14.470 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:14.470 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:14.471 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:09:14.471 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:09:14.471 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:09:14.471 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:09:14.471 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:09:14.471 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:09:14.471 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:09:14.471 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=787 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:14.471 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=787 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:14.471 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=787 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:14.471 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=787 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:14.471 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=787 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:14.471 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=787 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:14.471 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=787 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:14.471 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=787 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:19.479 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:09:19.479 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:09:19.479 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:09:19.479 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:09:19.479 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:09:19.479 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:09:19.484 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:09:19.486 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:09:19.486 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:19.486 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:09:19.486 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:09:19.489 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:09:19.490 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:09:19.490 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:09:19.490 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:19.491 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:09:19.491 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:09:19.491 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:09:19.491 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:09:19.492 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:19.493 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:09:19.494 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:09:19.494 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:09:19.494 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:19.494 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:09:19.494 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:09:19.494 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:09:19.495 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:09:19.495 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:19.496 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:09:19.496 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:09:19.496 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:09:19.496 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:19.497 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:09:19.497 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:09:19.497 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:09:19.497 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:09:19.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:19.500 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:09:19.500 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:09:19.500 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:09:19.500 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:09:19.500 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:09:19.500 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:09:19.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:09:19.500 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:19.500 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:09:19.500 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:09:19.500 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:09:19.500 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:19.500 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:19.500 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:19.500 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:19.500 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:19.500 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:19.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:19.501 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:09:19.501 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:09:19.501 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:09:19.501 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:09:19.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:19.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:19.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:19.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:09:19.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:19.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:19.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:19.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:19.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:19.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:19.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:19.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:19.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:19.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:19.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:19.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:19.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:19.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:19.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:19.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:19.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:19.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:19.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:19.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:19.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:19.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:19.505 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:09:19.985 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:09:20.031 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:09:20.034 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:09:20.035 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:09:20.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:20.059 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:20.059 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:20.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:09:20.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:20.065 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:20.065 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:20.066 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:09:20.066 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:09:20.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:20.086 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:20.086 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:20.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:20.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:20.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:20.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:20.404 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:20.404 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:20.421 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:20.421 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:20.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:09:20.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:20.423 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:20.423 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:20.423 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:09:20.423 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:09:20.457 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:09:20.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:20.462 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:20.462 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:20.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:20.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:20.504 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:20.504 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:20.504 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:20.504 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:20.928 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:09:20.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:20.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:20.944 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:20.944 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:20.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:20.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:20.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:09:20.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:20.967 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:20.967 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:20.967 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:09:20.967 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:09:20.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:20.971 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:20.971 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:20.971 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:20.971 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:21.402 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:09:21.504 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:21.505 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:21.505 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:21.505 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:21.874 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:09:22.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:22.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:22.036 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:22.036 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:22.051 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:22.051 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:22.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:09:22.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:22.052 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:22.052 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:22.053 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:09:22.053 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:09:22.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:22.057 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:22.057 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:22.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:22.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:22.346 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:09:22.506 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:22.506 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:22.506 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:22.506 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:22.817 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:09:23.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:23.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:23.138 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:23.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:23.148 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:23.149 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:23.149 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:23.149 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:23.153 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:09:23.153 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:09:23.153 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:09:23.153 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:09:23.153 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:09:23.153 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:09:23.154 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:09:23.154 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=789 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:23.154 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=789 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:23.154 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=789 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:23.154 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=789 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:23.154 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=789 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:23.154 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=789 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:28.156 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:09:28.156 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:09:28.156 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:09:28.156 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:09:28.156 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:09:28.156 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:09:28.163 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:09:28.164 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:09:28.164 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:28.165 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:09:28.165 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:09:28.167 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:09:28.167 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:09:28.168 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:09:28.168 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:28.168 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:09:28.169 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:09:28.169 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:09:28.169 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:09:28.169 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:28.171 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:09:28.172 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:09:28.172 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:09:28.172 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:28.172 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:09:28.172 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:09:28.173 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:09:28.173 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:09:28.173 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:28.176 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:09:28.176 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:09:28.176 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:09:28.176 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:28.176 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:09:28.176 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:09:28.176 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:09:28.176 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:09:28.177 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:28.182 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:09:28.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:09:28.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:09:28.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:09:28.182 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:09:28.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:09:28.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:09:28.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:28.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:09:28.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:09:28.182 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:09:28.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:28.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:28.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:28.182 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:28.183 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:28.183 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:28.183 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:28.183 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:09:28.183 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:09:28.183 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:09:28.183 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:09:28.183 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:28.183 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:28.183 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:28.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:09:28.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:28.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:28.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:28.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:28.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:28.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:28.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:28.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:28.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:28.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:28.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:28.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:28.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:28.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:28.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:28.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:28.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:28.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:28.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:28.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:28.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:28.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:28.188 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:09:28.665 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:09:28.718 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:09:28.719 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:09:28.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:28.721 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:09:28.738 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:28.738 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:28.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:09:28.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:28.745 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:28.745 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:28.745 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:09:28.745 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:09:28.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:28.769 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:28.769 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:28.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:28.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:29.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:29.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:29.084 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:29.084 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:29.100 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:29.100 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:29.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:09:29.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:29.102 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:29.102 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:29.102 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:09:29.102 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:09:29.136 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:09:29.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:29.146 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:29.146 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:29.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:29.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:29.188 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:29.188 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:29.188 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:29.189 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:29.609 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:09:29.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:29.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:29.628 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:29.628 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:29.647 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:29.647 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:29.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:09:29.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:29.649 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:29.649 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:29.649 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:09:29.649 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:09:29.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:29.653 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:29.653 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:29.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:29.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:30.081 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:09:30.189 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:30.190 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:30.190 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:30.190 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:30.552 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:09:30.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:30.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:30.710 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:30.710 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:30.726 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:30.726 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:30.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:09:30.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:30.728 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:30.728 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:30.728 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:09:30.728 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:09:30.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:30.733 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:30.733 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:30.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:30.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:31.025 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:09:31.191 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:31.191 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:31.191 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:31.192 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:31.497 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:09:31.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:31.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:31.821 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:31.821 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:31.830 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:31.830 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:31.830 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:31.830 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:31.834 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:09:31.834 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:09:31.834 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:09:31.834 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:09:31.835 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:09:31.835 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:09:31.835 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:09:31.835 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=789 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:31.835 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=789 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:31.835 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=789 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:31.835 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=789 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:31.836 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=789 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:31.836 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=789 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:31.836 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=789 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:31.836 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=789 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:36.836 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:09:36.836 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:09:36.837 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:09:36.837 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:09:36.837 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:09:36.837 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:09:36.842 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:09:36.844 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:09:36.844 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:36.844 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:09:36.844 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:09:36.847 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:09:36.848 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:09:36.848 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:09:36.848 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:36.849 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:09:36.849 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:09:36.849 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:09:36.849 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:09:36.849 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:36.851 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:09:36.851 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:09:36.851 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:09:36.851 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:36.852 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:09:36.852 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:09:36.852 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:09:36.852 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:09:36.852 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:36.854 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:09:36.854 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:09:36.854 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:09:36.854 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:36.854 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:09:36.854 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:09:36.854 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:09:36.854 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:09:36.854 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:36.857 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:09:36.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:09:36.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:09:36.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:09:36.857 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:09:36.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:09:36.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:09:36.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:36.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:09:36.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:09:36.858 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:09:36.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:36.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:36.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:36.858 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:36.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:36.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:36.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:36.858 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:09:36.858 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:09:36.858 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:09:36.858 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:09:36.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:36.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:36.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:36.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:09:36.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:36.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:36.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:36.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:36.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:36.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:36.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:36.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:36.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:36.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:36.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:36.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:36.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:36.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:36.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:36.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:36.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:36.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:36.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:36.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:36.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:36.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:36.863 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:09:37.339 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:09:37.390 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:09:37.393 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:09:37.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:37.396 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:09:37.418 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:37.418 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:37.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:09:37.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:37.425 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:37.425 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:37.425 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:09:37.425 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:09:37.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:37.436 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:37.436 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:37.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:37.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:37.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:37.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:37.739 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:37.739 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:37.758 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:37.758 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:37.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:09:37.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:37.761 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:37.761 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:37.761 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:09:37.761 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:09:37.810 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:09:37.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:37.820 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:37.820 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:37.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:37.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:37.861 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:37.862 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:37.863 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:37.866 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:38.282 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:09:38.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:38.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:38.298 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:38.299 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:38.316 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:38.316 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:38.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:09:38.318 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:38.318 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:38.318 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:38.318 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:09:38.318 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:09:38.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:38.325 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:38.325 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:38.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:38.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:38.755 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:09:38.862 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:38.863 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:38.863 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:38.867 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:39.228 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:09:39.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:39.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:39.388 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:39.388 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:39.402 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:39.402 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:39.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:09:39.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:39.405 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:39.405 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:39.405 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:09:39.405 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:09:39.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:39.412 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:09:39.412 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:09:39.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:39.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:39.699 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:09:39.863 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:39.864 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:39.864 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:39.868 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:40.171 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:09:40.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:40.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:09:40.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:40.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:40.500 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:40.501 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:40.501 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:40.501 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:40.504 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:09:40.505 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:09:40.505 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:09:40.505 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:09:40.505 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:09:40.506 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:09:40.506 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:09:40.506 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=788 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:40.506 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=788 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:40.506 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=788 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:40.506 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=788 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:40.506 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=788 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:40.506 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=788 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:45.507 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:09:45.508 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:09:45.508 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:09:45.508 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:09:45.508 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:09:45.508 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:09:45.515 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:09:45.516 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:09:45.517 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:45.517 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:09:45.517 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:09:45.520 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:09:45.520 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:09:45.520 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:09:45.520 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:45.521 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:09:45.521 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:09:45.521 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:09:45.521 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:09:45.521 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:45.522 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:09:45.523 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:09:45.523 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:09:45.523 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:45.523 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:09:45.523 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:09:45.523 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:09:45.523 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:09:45.523 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:45.525 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:09:45.525 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:09:45.525 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:09:45.525 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:45.525 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:09:45.525 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:09:45.525 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:09:45.525 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:09:45.525 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:45.528 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:09:45.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:09:45.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:09:45.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:09:45.528 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:09:45.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:09:45.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:09:45.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:45.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:09:45.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:09:45.528 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:09:45.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:45.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:45.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:45.528 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:45.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:45.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:09:45.529 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:09:45.529 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:09:45.529 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:45.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:45.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:45.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:45.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:45.533 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:09:46.012 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:09:46.055 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:09:46.057 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:09:46.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:46.059 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:09:46.072 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:46.072 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:46.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:09:46.088 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:46.089 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:46.089 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:46.089 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:46.091 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:09:46.091 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:09:46.091 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:09:46.092 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:09:46.092 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:09:46.092 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:09:46.092 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:09:46.092 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:46.092 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:46.092 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:46.092 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:46.092 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:46.092 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:51.101 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:09:51.102 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:09:51.102 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:09:51.102 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:09:51.102 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:09:51.102 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:09:51.110 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:09:51.111 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:09:51.111 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:51.111 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:09:51.111 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:09:51.113 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:09:51.113 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:09:51.114 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:09:51.114 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:51.114 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:09:51.114 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:09:51.115 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:09:51.115 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:09:51.115 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:51.116 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:09:51.116 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:09:51.116 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:09:51.116 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:51.116 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:09:51.116 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:09:51.116 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:09:51.116 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:09:51.116 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:51.118 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:09:51.118 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:09:51.118 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:09:51.118 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:51.118 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:09:51.118 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:09:51.118 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:09:51.118 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:09:51.118 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:51.120 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:09:51.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:09:51.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:09:51.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:09:51.120 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:09:51.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:09:51.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:09:51.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:51.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:09:51.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:09:51.120 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:09:51.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:51.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:51.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:51.120 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:51.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:09:51.121 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:09:51.121 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:09:51.121 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:51.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:51.125 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:09:51.602 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:09:51.643 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:09:51.645 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:09:51.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:51.647 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:09:51.680 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:51.681 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:51.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:09:51.699 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:51.699 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:51.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:09:51.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:51.705 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:51.705 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:51.705 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:51.705 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:51.705 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:09:51.705 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:09:51.705 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:09:51.705 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:09:51.706 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:09:51.706 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:09:51.706 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:09:56.713 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:09:56.713 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:09:56.713 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:09:56.713 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:09:56.713 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:09:56.713 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:09:56.720 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:09:56.721 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:09:56.721 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:56.721 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:09:56.721 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:09:56.723 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:09:56.724 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:09:56.724 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:09:56.724 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:56.724 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:09:56.724 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:09:56.725 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:09:56.725 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:09:56.725 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:56.726 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:09:56.726 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:09:56.726 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:09:56.726 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:56.726 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:09:56.726 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:09:56.726 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:09:56.726 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:09:56.727 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:56.728 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:09:56.728 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:09:56.728 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:09:56.728 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:09:56.728 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:09:56.728 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:09:56.728 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:09:56.728 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:09:56.729 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:56.731 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:09:56.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:09:56.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:09:56.731 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:09:56.731 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:09:56.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:09:56.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:09:56.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:56.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:09:56.731 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:09:56.731 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:09:56.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:56.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:56.731 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:56.731 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:56.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:56.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:56.731 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:09:56.731 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:09:56.731 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:09:56.731 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:09:56.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:56.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:56.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:56.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:09:56.732 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:56.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:56.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:56.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:56.732 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:56.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:56.732 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:56.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:56.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:56.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:56.732 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:09:56.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:56.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:56.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:56.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:56.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:56.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:56.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:56.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:09:56.733 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:56.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:56.733 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:09:56.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:09:56.736 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:09:57.212 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:09:57.260 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:09:57.262 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:09:57.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:09:57.265 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:09:57.282 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:09:57.282 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:09:57.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:09:57.293 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:09:57.293 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:09:57.293 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:09:57.293 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:09:57.296 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:09:57.296 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:09:57.296 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:09:57.296 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:09:57.297 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:09:57.297 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:09:57.297 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:09:57.297 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:57.297 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:57.297 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:57.297 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:57.297 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:57.297 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:09:57.297 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:10:02.299 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:10:02.299 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:10:02.299 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:10:02.299 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:10:02.299 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:10:02.299 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:10:02.302 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:10:02.302 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:10:02.302 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:10:02.302 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:10:02.302 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:10:02.303 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:10:02.303 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:10:02.304 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:10:02.304 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:10:02.304 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:10:02.304 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:10:02.304 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:10:02.304 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:10:02.304 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:10:02.305 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:10:02.305 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:10:02.305 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:10:02.305 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:10:02.305 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:10:02.305 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:10:02.305 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:10:02.305 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:10:02.305 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:10:02.306 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:10:02.306 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:10:02.306 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:10:02.306 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:10:02.306 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:10:02.306 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:10:02.306 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:10:02.306 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:10:02.306 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:10:02.308 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:10:02.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:10:02.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:10:02.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:10:02.308 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:10:02.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:10:02.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:10:02.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:02.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:10:02.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:10:02.308 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:10:02.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:02.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:10:02.309 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:10:02.309 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:10:02.309 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:02.309 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:02.310 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:10:02.310 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:10:02.310 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:10:02.310 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:10:02.310 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:10:02.310 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:10:02.310 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:10:07.322 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:10:07.322 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:10:07.323 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:10:07.323 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:10:07.323 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:10:07.323 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:10:07.330 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:10:07.331 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:10:07.331 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:10:07.332 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:10:07.332 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:10:07.334 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:10:07.334 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:10:07.334 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:10:07.334 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:10:07.334 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:10:07.334 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:10:07.335 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:10:07.335 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:10:07.335 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:10:07.336 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:10:07.336 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:10:07.336 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:10:07.336 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:10:07.337 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:10:07.337 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:10:07.337 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:10:07.337 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:10:07.337 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:10:07.338 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:10:07.338 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:10:07.338 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:10:07.338 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:10:07.338 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:10:07.338 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:10:07.338 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:10:07.338 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:10:07.339 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:10:07.341 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:10:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:10:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:10:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:10:07.341 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:10:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:10:07.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:10:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:10:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:10:07.341 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:10:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:07.341 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:10:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:07.341 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:10:07.341 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:10:07.341 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:10:07.341 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:10:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:07.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:10:07.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:07.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:07.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:07.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:07.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:07.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:07.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:07.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:07.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:07.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:07.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:07.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:07.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:07.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:07.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:07.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:07.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:07.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:07.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:07.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:07.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:07.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:07.346 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:10:07.824 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:10:07.862 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:10:07.863 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:10:07.864 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:10:07.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:07.874 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:07.875 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:07.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:10:07.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:07.878 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:07.878 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:07.878 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:10:07.878 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:10:07.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:07.928 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:07.929 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:07.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:07.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:08.295 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:10:08.344 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:10:08.344 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:10:08.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:10:08.344 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:10:08.767 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:10:08.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:08.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:08.879 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:08.879 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:08.888 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:08.888 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:08.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:10:08.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:08.889 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:08.889 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:08.889 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:10:08.889 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:10:08.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:08.908 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:08.908 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:08.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:08.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:09.238 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:10:09.345 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:10:09.346 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:10:09.346 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:10:09.346 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:10:09.711 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:10:09.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:09.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:09.839 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:09.839 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:09.855 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:09.855 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:09.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:10:09.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:09.856 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:09.856 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:09.856 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:10:09.856 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:10:09.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:09.900 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:09.901 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:09.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:09.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:10.184 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:10:10.346 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:10:10.347 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:10:10.347 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:10:10.347 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:10:10.656 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:10:10.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:10.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:10.813 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:10.814 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:10.831 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:10.831 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:10.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:10:10.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:10.833 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:10.833 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:10.833 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:10:10.833 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:10:10.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:10.838 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:10.838 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:10.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:10.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:11.127 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:10:11.348 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:10:11.348 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:10:11.348 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:10:11.348 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:10:11.600 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:10:11.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:11.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:11.775 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:11.775 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:11.790 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:11.790 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:11.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:10:11.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:11.791 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:11.791 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:11.791 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:10:11.791 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:10:11.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:11.834 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:11.835 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:11.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:11.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:12.073 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:10:12.349 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:10:12.349 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:10:12.349 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:10:12.349 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:10:12.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:12.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:12.393 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:12.393 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:12.393 [WARNING] transceiver.py:257 (MS@172.18.59.22:6700) RX TRXD message (fn=1091 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:10:12.401 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:12.401 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:12.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:10:12.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:12.402 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:12.402 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:12.402 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:10:12.402 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:10:12.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:12.450 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:12.450 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:12.450 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:12.450 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:12.545 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:10:12.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:12.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:12.993 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:12.993 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:13.001 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:13.001 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:13.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:10:13.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:13.002 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:13.002 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:13.002 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:10:13.002 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:10:13.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:13.015 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:13.015 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:13.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:13.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:13.015 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:10:13.486 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:10:13.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:13.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:13.575 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:13.575 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:13.583 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:13.583 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:13.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:10:13.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:13.585 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:13.585 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:13.585 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:10:13.585 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:10:13.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:13.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:13.634 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:13.634 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:13.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:13.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:13.957 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:10:14.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:14.230 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:14.230 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:14.231 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:14.248 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:14.248 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:14.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:10:14.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:14.250 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:14.250 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:14.250 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:10:14.250 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:10:14.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:14.294 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:14.294 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:14.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:14.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:14.430 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:10:14.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:14.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:14.876 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:14.877 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:14.894 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:14.894 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:14.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:10:14.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:14.895 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:14.895 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:14.895 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:10:14.895 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:10:14.902 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:10:14.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:14.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:14.959 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:14.959 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:14.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:14.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:15.375 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:10:15.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:15.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:15.500 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:15.500 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:15.517 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:15.517 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:15.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:10:15.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:15.519 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:15.519 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:15.519 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:10:15.519 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:10:15.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:15.569 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:15.569 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:15.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:15.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:15.848 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:10:16.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:16.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:16.156 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:16.156 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:16.174 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:16.174 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:16.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:10:16.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:16.177 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:16.177 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:16.177 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:10:16.177 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:10:16.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:16.227 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:16.227 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:16.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:16.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:16.320 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:10:16.792 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:10:16.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:16.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:16.844 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:16.844 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:16.862 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:16.862 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:16.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:10:16.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:16.864 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:16.864 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:16.864 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:10:16.864 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:10:16.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:16.889 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:16.889 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:16.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:16.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:17.263 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:10:17.737 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:10:17.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:17.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:17.745 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:17.745 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:17.762 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:17.762 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:17.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:10:17.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:17.764 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:17.764 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:17.764 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:10:17.764 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:10:17.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:17.780 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:17.780 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:17.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:17.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:18.209 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:10:18.680 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:10:18.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:18.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:18.710 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:18.710 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:18.718 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:18.718 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:18.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:10:18.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:18.719 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:18.720 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:18.720 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:10:18.720 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:10:18.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:18.724 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:18.724 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:18.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:18.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:19.151 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:10:19.622 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:10:19.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:19.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:19.669 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:19.670 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:19.684 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:19.685 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:19.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:10:19.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:19.686 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:19.686 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:19.686 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:10:19.686 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:10:19.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:19.719 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:19.719 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:19.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:19.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:20.095 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:10:20.568 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:10:20.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:20.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:20.635 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:20.636 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:20.644 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:20.644 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:20.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:10:20.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:20.645 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:20.645 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:20.646 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:10:20.646 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:10:20.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:20.663 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:20.663 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:20.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:20.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:21.040 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:10:21.511 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:10:21.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:21.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:21.596 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:21.596 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:21.614 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:21.614 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:21.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:10:21.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:21.616 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:21.616 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:21.616 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:10:21.616 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:10:21.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:21.660 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:21.660 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:21.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:21.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:21.984 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:10:22.457 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:10:22.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:22.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:22.561 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:22.561 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:22.580 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:22.580 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:22.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:10:22.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:22.582 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:22.582 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:22.582 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:10:22.582 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:10:22.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:22.598 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:22.598 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:22.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:22.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:22.929 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:10:23.400 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:10:23.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:23.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:23.521 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:23.522 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:23.539 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:23.539 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:23.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:10:23.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:23.541 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:23.541 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:23.541 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:10:23.541 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:10:23.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:23.587 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:23.587 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:23.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:23.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:23.871 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:10:24.344 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:10:24.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:24.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:24.481 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:24.481 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:24.488 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:10:24.488 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:10:24.488 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:10:24.488 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:10:24.489 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:10:24.489 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:10:24.489 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:10:24.489 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:10:24.489 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:10:24.489 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:10:24.489 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:10:29.496 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:10:29.496 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:10:29.496 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:10:29.496 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:10:29.496 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:10:29.496 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:10:29.508 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:10:29.510 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:10:29.510 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:10:29.510 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:10:29.510 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:10:29.516 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:10:29.516 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:10:29.516 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:10:29.516 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:10:29.517 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:10:29.517 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:10:29.517 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:10:29.517 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:10:29.517 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:10:29.521 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:10:29.521 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:10:29.521 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:10:29.521 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:10:29.521 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:10:29.521 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:10:29.522 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:10:29.522 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:10:29.522 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:10:29.524 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:10:29.525 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:10:29.525 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:10:29.525 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:10:29.525 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:10:29.525 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:10:29.525 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:10:29.525 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:10:29.525 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:10:29.529 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:10:29.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:10:29.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:10:29.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:10:29.529 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:10:29.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:10:29.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:10:29.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:29.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:10:29.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:10:29.529 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:10:29.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:29.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:29.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:29.529 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:10:29.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:29.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:29.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:29.529 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:10:29.529 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:10:29.529 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:10:29.529 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:10:29.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:29.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:29.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:29.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:10:29.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:29.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:29.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:29.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:29.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:29.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:29.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:29.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:29.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:29.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:29.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:29.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:29.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:29.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:29.531 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:29.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:29.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:29.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:29.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:29.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:29.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:29.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:29.534 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:10:30.013 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:10:30.061 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:10:30.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:30.064 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:10:30.065 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:10:30.081 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:30.081 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:30.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:10:30.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:30.087 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:30.087 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:30.088 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:10:30.088 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:10:30.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:30.117 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:30.117 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:30.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:30.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:30.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:30.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:30.361 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:30.361 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:30.370 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:30.370 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:30.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:10:30.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:30.371 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:30.371 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:30.371 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:10:30.371 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:10:30.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:30.389 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:30.389 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:30.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:30.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:30.484 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:10:30.533 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:10:30.533 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:10:30.533 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:10:30.534 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:10:30.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:30.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:30.616 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:30.616 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:30.624 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:30.624 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:30.624 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:10:30.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:30.625 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:30.625 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:30.625 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:10:30.625 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:10:30.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:30.677 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:30.677 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:30.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:30.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:30.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:30.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:30.878 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:30.878 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:30.896 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:30.896 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:30.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:10:30.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:30.898 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:30.898 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:30.898 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:10:30.898 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:10:30.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:30.902 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:10:30.902 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:10:30.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:30.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:30.956 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:10:31.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:10:31.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:10:31.133 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:10:31.133 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:10:31.140 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:10:31.140 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:10:31.140 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:10:31.140 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:10:31.142 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:10:31.142 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:10:31.142 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:10:31.142 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:10:31.142 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:10:31.142 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:10:31.142 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:10:31.142 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=348 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:10:31.142 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=348 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:10:31.142 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=348 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:10:31.142 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=348 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:10:36.148 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:10:36.148 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:10:36.148 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:10:36.148 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:10:36.148 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:10:36.148 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:10:36.156 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:10:36.156 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:10:36.157 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:10:36.157 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:10:36.157 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:10:36.160 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:10:36.160 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:10:36.160 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:10:36.160 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:10:36.160 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:10:36.161 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:10:36.161 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:10:36.161 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:10:36.161 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:10:36.163 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:10:36.163 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:10:36.163 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:10:36.163 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:10:36.164 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:10:36.164 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:10:36.164 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:10:36.164 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:10:36.164 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:10:36.166 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:10:36.166 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:10:36.166 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:10:36.166 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:10:36.166 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:10:36.166 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:10:36.166 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:10:36.166 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:10:36.166 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:10:36.169 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:10:36.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:10:36.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:10:36.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:10:36.169 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:10:36.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:10:36.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:10:36.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:36.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:10:36.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:10:36.170 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:10:36.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:36.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:36.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:36.170 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:10:36.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:36.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:36.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:36.170 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:10:36.170 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:10:36.170 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:10:36.170 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:10:36.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:36.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:36.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:36.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:10:36.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:36.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:36.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:36.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:36.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:36.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:36.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:36.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:36.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:36.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:36.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:10:36.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:36.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:36.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:36.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:36.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:36.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:36.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:10:36.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:36.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:10:36.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:36.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:10:36.174 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:10:36.652 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:10:37.121 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:10:37.585 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:10:38.054 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:10:38.527 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:10:38.999 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:10:39.464 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:10:39.938 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:10:40.410 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:10:40.886 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:10:41.357 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:10:41.828 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:10:42.304 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:10:42.776 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:10:43.251 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:10:43.723 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:10:44.198 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:10:44.670 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:10:45.141 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:10:45.616 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:10:46.088 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:10:46.559 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:10:47.035 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:10:47.506 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:10:47.977 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:10:48.453 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:10:48.925 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:10:49.400 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:10:49.881 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:10:50.353 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:10:50.828 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:10:51.300 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:10:51.776 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:10:52.248 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:10:52.722 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:10:53.194 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:10:53.666 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:10:54.141 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:10:54.613 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:10:55.088 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:10:55.560 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:10:56.036 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:10:56.507 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:10:56.978 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 02:10:57.454 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 02:10:57.926 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 02:10:58.401 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 02:10:58.873 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 02:10:59.348 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 02:10:59.820 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 02:11:00.194 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:11:00.194 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:11:00.194 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:11:00.195 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:11:00.195 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:11:00.195 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:11:00.195 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:11:00.195 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5183 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:11:00.195 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5183 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:11:00.196 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5183 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:11:00.196 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5183 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:11:00.196 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5183 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:11:00.196 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5183 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:11:00.196 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5183 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:11:05.201 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:11:05.201 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:11:05.201 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:11:05.201 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:11:05.201 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:11:05.201 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:11:05.209 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:11:05.210 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:11:05.210 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:11:05.210 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:11:05.211 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:11:05.213 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:11:05.214 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:11:05.214 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:11:05.214 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:11:05.214 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:11:05.215 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:11:05.215 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:11:05.215 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:11:05.215 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:11:05.216 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:11:05.216 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:11:05.216 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:11:05.216 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:11:05.217 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:11:05.217 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:11:05.217 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:11:05.217 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:11:05.217 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:11:05.219 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:11:05.219 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:11:05.219 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:11:05.219 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:11:05.219 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:11:05.219 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:11:05.219 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:11:05.219 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:11:05.219 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:11:05.222 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:11:05.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:11:05.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:11:05.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:11:05.222 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:11:05.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:11:05.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:11:05.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:11:05.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:11:05.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:11:05.222 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:11:05.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:11:05.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:11:05.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:11:05.222 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:11:05.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:11:05.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:11:05.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:11:05.222 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:11:05.222 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:11:05.222 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:11:05.222 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:11:05.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:11:05.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:11:05.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:11:05.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:11:05.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:11:05.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:11:05.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:11:05.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:11:05.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:11:05.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:11:05.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:11:05.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:11:05.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:11:05.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:11:05.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:11:05.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:11:05.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:11:05.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:11:05.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:11:05.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:11:05.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:11:05.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:11:05.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:11:05.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:11:05.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:11:05.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:11:05.227 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:11:05.704 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:11:06.176 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:11:06.652 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:11:07.124 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:11:07.599 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:11:08.071 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:11:08.546 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:11:09.018 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:11:09.494 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:11:09.966 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:11:10.441 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:11:10.913 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:11:11.388 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:11:11.860 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:11:12.336 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:11:12.807 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:11:13.283 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:11:13.755 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:11:14.230 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:11:14.702 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:11:15.176 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:11:15.648 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:11:16.120 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:11:16.596 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:11:17.067 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:11:17.543 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:11:18.015 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:11:18.490 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:11:18.962 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:11:19.438 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:11:19.910 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:11:20.386 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:11:20.858 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:11:21.333 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:11:21.802 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:11:22.271 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:11:22.747 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:11:23.213 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:11:23.685 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:11:24.157 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:11:24.632 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:11:25.104 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:11:25.580 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:11:26.051 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 02:11:26.527 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 02:11:27.002 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 02:11:27.475 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 02:11:27.950 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 02:11:28.422 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 02:11:28.897 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 02:11:29.369 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 02:11:29.845 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 02:11:30.317 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 02:11:30.792 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 02:11:31.264 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 02:11:31.739 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 02:11:32.211 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 02:11:32.687 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 02:11:33.161 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 02:11:33.634 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 02:11:34.106 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 02:11:34.581 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 02:11:35.053 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 02:11:35.529 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 02:11:36.001 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 02:11:36.475 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 02:11:36.947 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 02:11:37.419 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 02:11:37.893 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 02:11:38.365 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 02:11:38.837 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 02:11:39.307 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 02:11:39.780 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 02:11:40.254 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-06 02:11:40.725 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-06 02:11:41.201 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-06 02:11:41.673 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-06 02:11:42.146 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-06 02:11:42.249 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:11:42.619 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-06 02:11:43.091 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-06 02:11:43.251 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:11:43.564 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-06 02:11:44.037 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-06 02:11:44.252 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:11:44.509 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-06 02:11:44.983 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-06 02:11:45.254 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:11:45.455 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-06 02:11:45.927 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-06 02:11:46.255 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:11:46.397 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-06 02:11:46.871 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-06 02:11:47.255 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:11:47.255 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:11:47.255 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:11:47.255 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:11:47.255 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:11:47.255 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:11:47.255 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:11:47.255 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:11:47.255 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=9062 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:11:47.255 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=9062 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:11:47.255 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=9062 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:11:47.255 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=9062 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:11:47.255 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=9062 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:11:47.255 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=9062 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:11:52.262 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:11:52.262 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:11:52.262 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:11:52.262 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:11:52.262 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:11:52.262 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:11:52.270 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:11:52.271 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:11:52.271 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:11:52.271 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:11:52.271 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:11:52.274 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:11:52.274 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:11:52.274 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:11:52.274 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:11:52.275 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:11:52.275 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:11:52.275 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:11:52.275 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:11:52.275 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:11:52.276 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:11:52.277 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:11:52.277 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:11:52.277 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:11:52.277 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:11:52.277 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:11:52.277 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:11:52.277 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:11:52.277 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:11:52.279 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:11:52.279 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:11:52.279 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:11:52.279 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:11:52.279 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:11:52.279 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:11:52.279 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:11:52.279 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:11:52.279 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:11:52.282 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:11:52.282 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:11:52.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:11:52.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:11:52.282 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:11:52.282 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:11:52.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:11:52.282 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:11:52.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:11:52.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:11:52.282 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:11:52.282 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:11:52.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:11:52.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:11:52.282 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:11:52.282 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:11:52.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:11:52.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:11:52.282 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:11:52.282 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:11:52.282 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:11:52.282 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:11:52.282 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:11:52.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:11:52.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:11:52.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:11:52.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:11:52.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:11:52.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:11:52.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:11:52.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:11:52.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:11:52.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:11:52.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:11:52.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:11:52.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:11:52.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:11:52.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:11:52.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:11:52.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:11:52.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:11:52.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:11:52.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:11:52.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:11:52.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:11:52.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:11:52.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:11:52.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:11:52.287 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:11:52.767 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:11:52.810 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:11:52.811 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:11:52.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:11:52.813 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:11:52.830 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:11:52.830 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:11:52.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:11:52.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:11:52.835 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:11:52.836 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:11:52.836 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:11:52.836 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:11:52.859 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:11:52.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:11:52.875 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:11:52.875 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:11:52.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:11:52.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:11:53.238 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:11:53.285 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:11:53.285 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:11:53.286 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:11:53.286 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:11:53.710 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:11:53.725 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:11:54.181 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:11:54.286 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:11:54.286 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:11:54.287 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:11:54.287 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:11:54.654 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:11:55.127 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:11:55.287 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:11:55.287 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:11:55.287 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:11:55.288 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:11:55.599 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:11:56.070 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:11:56.289 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:11:56.289 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:11:56.289 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:11:56.289 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:11:56.541 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:11:57.014 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:11:57.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:11:57.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:11:57.097 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:11:57.097 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:11:57.117 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:11:57.117 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:11:57.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:11:57.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:11:57.119 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:11:57.120 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:11:57.120 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:11:57.120 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:11:57.149 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:11:57.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:11:57.154 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:11:57.154 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:11:57.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:11:57.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:11:57.290 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:11:57.290 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:11:57.291 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:11:57.291 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:11:57.487 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:11:57.959 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:11:58.297 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:11:58.430 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:11:58.901 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:11:59.371 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:11:59.844 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:12:00.317 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:12:00.789 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:12:01.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:12:01.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:01.188 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:12:01.188 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:12:01.207 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:12:01.207 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:12:01.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:12:01.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:01.209 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:12:01.209 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:12:01.209 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:12:01.209 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:12:01.259 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:12:01.260 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:01.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:12:01.274 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:12:01.274 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:12:01.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:01.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:01.695 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:12:01.731 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:12:02.201 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:12:02.675 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:12:03.147 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:12:03.620 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:12:04.091 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:12:04.561 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:12:04.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:12:05.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:05.001 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:12:05.001 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:12:05.019 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:12:05.019 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:12:05.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:12:05.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:05.021 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:12:05.021 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:12:05.021 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:12:05.021 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:12:05.027 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:05.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:12:05.032 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:12:05.032 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:12:05.032 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:12:05.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:05.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:05.502 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:12:05.892 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:12:05.974 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:12:06.362 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:12:06.447 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:12:06.920 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:12:07.310 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:12:07.391 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:12:07.863 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:12:08.336 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:12:08.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:12:08.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:08.728 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:12:08.728 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:12:08.738 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:12:08.738 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:12:08.738 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:12:08.738 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:12:08.741 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:12:08.741 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:12:08.741 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:12:08.741 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:12:08.741 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:12:08.741 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:12:08.741 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:12:08.741 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3558 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:12:08.741 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3558 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:12:08.741 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3558 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:12:08.741 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3558 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:12:08.741 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3558 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:12:08.741 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3558 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:12:08.741 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3558 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:12:13.744 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:12:13.744 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:12:13.744 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:12:13.744 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:12:13.744 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:12:13.744 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:12:13.751 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:12:13.752 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:12:13.752 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:12:13.752 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:12:13.752 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:12:13.753 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:12:13.753 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:12:13.753 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:12:13.753 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:12:13.753 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:12:13.753 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:12:13.753 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:12:13.753 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:12:13.753 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:12:13.754 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:12:13.754 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:12:13.754 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:12:13.754 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:12:13.754 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:12:13.754 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:12:13.754 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:12:13.754 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:12:13.754 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:12:13.755 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:12:13.755 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:12:13.755 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:12:13.755 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:12:13.755 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:12:13.755 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:12:13.756 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:12:13.756 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:12:13.756 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:12:13.759 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:12:13.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:12:13.759 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:12:13.759 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:12:13.759 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:12:13.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:12:13.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:12:13.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:12:13.759 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:12:13.759 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:12:13.759 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:12:13.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:12:13.759 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:12:13.759 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:12:13.759 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:12:13.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:12:13.759 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:12:13.759 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:12:13.759 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:12:13.759 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:12:13.759 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:12:13.759 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:12:13.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:12:13.759 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:12:13.759 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:12:13.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:12:13.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:12:13.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:12:13.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:12:13.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:12:13.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:12:13.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:12:13.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:12:13.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:12:13.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:12:13.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:12:13.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:12:13.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:12:13.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:12:13.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:12:13.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:12:13.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:12:13.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:12:13.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:12:13.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:12:13.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:12:13.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:12:13.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:12:13.764 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:12:14.243 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:12:14.287 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:12:14.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:12:14.289 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:14.291 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:12:14.323 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:12:14.323 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:12:14.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:12:14.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:14.330 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:12:14.330 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:12:14.330 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:12:14.330 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:12:14.335 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:14.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:12:14.352 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:12:14.352 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:12:14.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:14.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:14.715 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:12:14.721 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:14.762 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:12:14.762 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:12:14.763 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:12:14.763 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:12:15.186 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:12:15.200 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:15.203 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:12:15.657 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:12:15.680 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:15.763 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:12:15.763 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:12:15.763 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:12:15.764 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:12:16.130 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:12:16.160 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:16.603 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:12:16.647 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:16.764 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:12:16.765 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:12:16.765 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:12:16.765 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:12:17.076 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:12:17.127 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:17.549 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:12:17.607 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:17.766 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:12:17.766 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:12:17.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:12:17.766 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:12:18.022 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:12:18.093 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:18.494 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:12:18.573 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:18.766 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:12:18.767 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:12:18.767 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:12:18.767 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:12:18.968 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:12:19.053 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:19.440 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:12:19.539 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:19.913 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:12:20.019 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:20.386 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:12:20.499 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:20.859 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:12:20.985 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:21.331 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:12:21.465 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:21.805 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:12:21.945 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:21.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:12:21.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:21.957 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:12:21.957 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:12:21.969 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:12:21.969 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:12:21.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:12:21.971 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:21.971 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:12:21.971 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:12:21.971 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:12:21.971 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:12:21.982 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:21.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:12:21.987 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:12:21.987 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:12:21.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:21.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:22.277 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:12:22.673 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:22.749 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:12:23.152 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:23.155 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:12:23.220 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:12:23.632 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:23.693 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:12:24.112 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:24.166 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:12:24.597 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:24.638 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:12:25.077 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:25.109 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:12:25.557 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:25.579 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:12:26.037 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:26.053 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:12:26.517 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:26.525 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:12:26.998 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:12:27.003 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:27.471 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:12:27.483 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:27.943 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:12:27.969 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:28.416 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:12:28.449 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:28.889 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:12:28.929 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:29.361 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:12:29.415 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:29.834 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:12:29.895 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:29.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:12:29.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:29.903 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:12:29.903 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:12:29.917 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:12:29.917 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:12:29.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:12:29.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:29.919 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:12:29.919 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:12:29.919 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:12:29.919 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:12:29.921 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:29.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:12:29.924 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:12:29.924 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:12:29.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:29.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:30.268 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:30.304 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:12:30.739 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:30.741 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:12:30.778 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:12:31.209 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:31.250 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:12:31.686 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:31.722 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:12:32.157 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:32.193 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:12:32.628 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:32.664 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:12:33.098 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:33.135 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:12:33.569 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:33.606 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:12:34.040 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:34.076 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:12:34.511 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:34.547 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 02:12:34.981 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:35.018 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 02:12:35.452 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:35.489 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 02:12:35.923 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:35.960 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 02:12:36.394 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:36.433 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 02:12:36.864 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:36.905 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 02:12:37.341 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:37.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:12:37.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:37.350 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:12:37.350 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:12:37.362 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:12:37.362 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:12:37.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:12:37.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:37.363 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:12:37.363 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:12:37.363 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:12:37.363 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:12:37.372 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:37.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:12:37.376 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:12:37.377 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:12:37.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:37.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:37.377 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 02:12:37.767 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:37.848 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 02:12:38.237 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:38.240 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:12:38.321 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 02:12:38.708 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:38.711 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:12:38.794 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 02:12:39.184 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:39.266 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 02:12:39.675 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:39.678 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:12:39.739 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 02:12:40.125 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:40.212 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 02:12:40.602 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:40.684 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 02:12:41.073 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:41.155 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 02:12:41.544 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:41.628 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 02:12:42.014 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:42.101 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 02:12:42.491 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:42.573 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 02:12:42.962 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:43.044 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 02:12:43.433 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:43.517 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 02:12:43.903 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:43.989 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 02:12:44.380 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:44.461 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 02:12:44.850 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:44.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:12:44.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:44.856 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:12:44.856 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:12:44.863 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:12:44.863 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:12:44.863 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:12:44.863 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:12:44.864 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:12:44.864 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:12:44.864 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:12:44.864 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:12:44.864 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:12:44.864 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:12:44.864 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:12:49.870 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:12:49.871 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:12:49.871 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:12:49.871 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:12:49.871 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:12:49.871 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:12:49.879 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:12:49.881 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:12:49.881 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:12:49.882 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:12:49.882 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:12:49.886 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:12:49.887 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:12:49.887 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:12:49.887 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:12:49.888 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:12:49.888 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:12:49.889 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:12:49.889 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:12:49.889 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:12:49.892 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:12:49.892 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:12:49.892 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:12:49.893 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:12:49.893 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:12:49.893 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:12:49.894 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:12:49.894 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:12:49.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:12:49.896 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:12:49.896 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:12:49.897 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:12:49.897 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:12:49.897 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:12:49.897 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:12:49.897 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:12:49.897 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:12:49.897 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:12:49.902 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:12:49.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:12:49.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:12:49.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:12:49.902 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:12:49.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:12:49.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:12:49.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:12:49.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:12:49.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:12:49.903 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:12:49.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:12:49.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:12:49.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:12:49.903 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:12:49.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:12:49.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:12:49.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:12:49.903 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:12:49.903 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:12:49.903 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:12:49.903 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:12:49.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:12:49.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:12:49.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:12:49.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:12:49.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:12:49.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:12:49.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:12:49.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:12:49.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:12:49.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:12:49.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:12:49.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:12:49.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:12:49.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:12:49.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:12:49.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:12:49.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:12:49.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:12:49.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:12:49.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:12:49.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:12:49.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:12:49.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:12:49.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:12:49.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:12:49.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:12:49.908 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:12:50.385 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:12:50.430 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:12:50.431 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:12:50.433 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:12:50.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:12:50.442 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:12:50.442 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:12:50.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:12:50.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:50.446 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:12:50.446 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:12:50.446 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:12:50.446 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:12:50.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:12:50.490 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:12:50.490 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:12:50.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:50.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:50.858 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:12:50.909 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:12:50.910 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:12:50.911 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:12:50.914 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:12:51.328 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:12:51.799 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:12:51.909 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:12:51.912 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:12:51.912 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:12:51.914 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:12:52.270 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:12:52.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:12:52.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:52.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:12:52.589 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:12:52.608 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:12:52.608 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:12:52.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:12:52.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:52.610 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:12:52.610 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:12:52.610 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:12:52.610 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:12:52.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:12:52.651 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:12:52.652 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:12:52.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:52.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:52.741 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:12:52.911 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:12:52.913 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:12:52.914 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:12:52.915 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:12:53.212 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:12:53.685 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:12:53.912 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:12:53.915 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:12:53.915 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:12:53.917 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:12:54.158 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:12:54.630 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:12:54.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:12:54.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:54.756 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:12:54.756 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:12:54.773 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:12:54.773 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:12:54.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:12:54.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:54.774 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:12:54.774 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:12:54.774 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:12:54.774 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:12:54.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:12:54.825 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:12:54.825 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:12:54.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:54.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:54.913 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:12:54.916 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:12:54.916 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:12:54.918 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:12:55.101 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:12:55.575 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:12:56.047 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:12:56.519 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:12:56.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:12:56.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:12:56.922 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:12:56.923 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:12:56.932 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:12:56.932 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:12:56.933 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:12:56.933 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:12:56.936 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:12:56.937 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:12:56.937 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:12:56.937 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:12:56.937 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:12:56.937 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:12:56.937 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:12:56.938 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1520 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:12:56.938 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1520 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:12:56.938 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1520 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:12:56.938 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1520 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:12:56.938 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1520 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:12:56.938 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1520 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:01.938 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:13:01.938 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:13:01.938 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:13:01.938 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:13:01.938 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:13:01.938 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:13:01.946 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:13:01.947 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:13:01.947 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:01.947 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:13:01.947 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:13:01.949 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:13:01.950 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:13:01.950 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:13:01.950 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:01.950 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:13:01.951 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:13:01.951 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:13:01.951 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:13:01.951 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:01.952 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:13:01.952 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:13:01.952 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:13:01.952 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:01.953 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:13:01.953 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:13:01.953 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:13:01.953 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:13:01.953 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:01.954 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:13:01.955 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:13:01.955 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:13:01.955 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:01.955 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:13:01.955 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:13:01.955 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:13:01.955 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:13:01.955 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:01.957 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:13:01.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:13:01.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:13:01.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:13:01.958 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:13:01.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:13:01.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:13:01.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:01.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:13:01.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:13:01.958 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:13:01.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:01.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:01.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:01.958 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:01.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:01.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:01.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:01.958 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:13:01.958 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:13:01.958 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:13:01.958 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:13:01.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:01.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:01.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:01.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:13:01.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:01.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:01.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:01.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:01.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:01.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:01.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:01.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:01.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:01.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:01.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:01.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:01.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:01.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:01.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:01.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:01.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:01.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:01.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:01.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:01.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:01.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:01.963 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:13:02.440 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:13:02.484 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:13:02.485 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:13:02.487 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:13:02.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:02.507 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:02.507 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:02.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:13:02.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:02.512 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:02.513 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:02.513 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:13:02.514 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:13:02.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:02.544 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:02.544 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:02.545 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:02.545 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:02.913 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:13:02.961 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:02.961 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:02.961 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:02.961 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:03.384 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:13:03.855 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:13:03.961 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:03.962 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:03.962 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:03.962 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:04.325 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:13:04.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:04.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:04.639 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:04.640 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:04.655 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:04.655 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:04.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:13:04.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:04.656 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:04.656 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:04.657 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:13:04.657 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:13:04.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:04.731 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:04.731 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:04.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:04.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:04.798 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:13:04.962 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:04.962 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:04.963 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:04.963 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:05.271 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:13:05.743 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:13:05.963 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:05.963 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:05.963 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:05.963 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:06.215 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:13:06.688 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:13:06.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:06.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:06.825 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:06.825 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:06.836 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:06.836 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:06.836 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:06.836 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:06.839 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:13:06.839 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:13:06.839 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:13:06.839 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:13:06.839 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:13:06.839 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:13:06.839 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:13:06.839 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1055 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:06.840 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1055 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:06.840 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1055 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:06.840 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1055 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:11.844 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:13:11.844 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:13:11.844 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:13:11.844 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:13:11.844 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:13:11.844 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:13:11.851 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:13:11.852 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:13:11.852 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:11.853 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:13:11.853 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:13:11.856 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:13:11.856 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:13:11.857 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:13:11.857 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:11.857 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:13:11.858 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:13:11.858 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:13:11.858 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:13:11.859 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:11.860 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:13:11.860 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:13:11.860 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:13:11.861 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:11.861 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:13:11.861 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:13:11.861 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:13:11.861 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:13:11.862 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:11.863 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:13:11.863 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:13:11.863 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:13:11.863 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:11.863 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:13:11.863 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:13:11.864 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:13:11.864 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:13:11.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:11.867 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:13:11.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:13:11.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:13:11.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:13:11.867 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:13:11.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:13:11.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:13:11.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:11.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:13:11.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:13:11.867 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:13:11.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:11.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:11.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:11.867 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:11.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:11.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:11.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:11.867 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:13:11.867 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:13:11.867 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:13:11.868 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:13:11.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:11.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:11.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:11.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:13:11.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:11.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:11.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:11.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:11.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:11.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:11.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:11.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:11.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:11.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:11.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:11.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:11.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:11.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:11.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:11.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:11.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:11.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:11.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:11.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:11.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:11.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:11.872 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:13:12.351 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:13:12.391 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:13:12.392 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:13:12.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:12.394 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:13:12.402 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:12.402 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:12.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:13:12.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:12.405 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:12.405 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:12.405 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:13:12.405 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:13:12.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:12.451 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:12.451 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:12.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:12.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:12.823 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:13:12.870 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:12.870 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:12.871 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:12.871 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:13.295 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:13:13.768 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:13:13.871 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:13.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:13.872 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:13.872 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:14.241 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:13:14.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:14.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:14.562 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:14.562 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:14.582 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:14.582 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:14.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:13:14.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:14.584 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:14.584 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:14.584 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:13:14.584 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:13:14.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:14.622 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:14.622 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:14.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:14.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:14.713 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:13:14.873 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:14.873 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:14.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:14.873 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:15.184 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:13:15.657 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:13:15.874 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:15.874 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:15.874 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:15.875 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:16.130 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:13:16.602 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:13:16.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:16.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:16.710 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:16.710 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:16.726 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:16.726 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:16.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:13:16.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:16.727 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:16.727 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:16.727 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:13:16.727 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:13:16.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:16.741 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:16.741 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:16.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:16.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:16.875 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:16.875 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:16.875 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:16.875 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:17.073 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:13:17.547 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:13:18.019 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:13:18.492 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:13:18.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:18.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:18.854 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:18.854 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:18.865 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:18.865 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:18.866 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:18.866 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:18.868 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:13:18.868 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:13:18.868 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:13:18.868 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:13:18.868 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:13:18.868 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:13:18.868 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:13:23.873 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:13:23.873 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:13:23.873 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:13:23.873 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:13:23.873 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:13:23.873 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:13:23.876 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:13:23.876 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:13:23.876 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:23.876 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:13:23.876 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:13:23.877 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:13:23.877 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:13:23.878 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:13:23.878 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:23.878 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:13:23.878 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:13:23.878 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:13:23.878 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:13:23.878 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:23.878 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:13:23.879 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:13:23.879 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:13:23.879 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:23.879 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:13:23.879 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:13:23.879 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:13:23.879 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:13:23.879 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:23.880 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:13:23.880 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:13:23.880 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:13:23.880 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:23.880 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:13:23.880 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:13:23.880 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:13:23.880 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:13:23.880 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:13:23.882 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:13:23.882 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:13:23.882 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:23.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:23.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:23.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:23.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:23.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:23.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:23.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:23.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:23.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:23.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:23.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:23.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:23.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:23.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:23.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:23.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:23.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:23.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:23.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:23.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:23.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:23.887 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:13:24.365 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:13:24.408 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:13:24.410 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:13:24.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:24.413 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:13:24.438 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:24.438 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:24.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:13:24.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:24.443 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:24.443 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:24.443 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:13:24.443 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:13:24.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:24.469 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:24.469 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:24.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:24.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:24.837 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:13:24.885 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:24.886 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:24.886 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:24.886 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:25.308 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:13:25.779 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:13:25.887 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:25.887 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:25.887 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:25.887 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:26.250 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:13:26.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:26.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:26.569 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:26.570 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:26.588 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:26.588 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:26.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:13:26.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:26.590 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:26.590 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:26.590 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:13:26.590 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:13:26.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:26.636 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:26.636 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:26.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:26.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:26.721 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:13:26.888 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:26.889 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:26.889 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:26.889 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:27.194 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:13:27.667 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:13:27.890 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:27.890 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:27.890 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:27.890 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:28.139 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:13:28.610 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:13:28.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:28.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:28.733 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:28.733 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:28.741 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:28.742 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:28.742 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:28.742 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:28.743 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:13:28.744 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:13:28.744 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:13:28.744 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:13:28.744 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:13:28.744 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:13:28.744 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:13:28.744 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1051 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:28.744 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1051 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:28.744 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1051 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:28.744 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1051 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:28.744 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1051 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:28.744 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1051 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:33.749 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:13:33.749 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:13:33.749 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:13:33.749 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:13:33.749 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:13:33.749 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:13:33.756 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:13:33.756 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:13:33.756 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:33.757 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:13:33.757 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:13:33.759 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:13:33.759 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:13:33.759 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:13:33.759 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:33.760 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:13:33.760 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:13:33.760 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:13:33.760 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:13:33.760 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:33.761 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:13:33.761 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:13:33.761 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:13:33.761 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:33.761 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:13:33.762 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:13:33.762 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:13:33.762 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:13:33.762 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:33.763 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:13:33.763 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:13:33.763 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:13:33.763 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:33.763 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:13:33.764 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:13:33.764 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:13:33.764 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:13:33.764 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:33.766 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:13:33.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:13:33.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:13:33.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:13:33.766 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:13:33.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:13:33.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:13:33.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:33.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:13:33.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:13:33.766 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:13:33.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:33.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:33.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:33.766 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:33.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:33.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:33.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:33.766 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:13:33.766 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:13:33.766 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:13:33.767 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:33.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:33.771 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:13:34.250 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:13:34.288 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:13:34.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:34.292 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:13:34.294 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:13:34.308 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:34.308 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:34.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:13:34.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:34.313 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:34.313 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:34.314 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:13:34.314 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:13:34.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:34.356 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:34.356 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:34.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:34.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:34.720 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:13:34.770 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:34.770 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:34.770 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:34.772 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:35.193 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:13:35.665 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:13:35.771 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:35.771 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:35.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:35.773 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:36.136 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:13:36.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:36.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:36.515 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:36.515 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:36.523 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:36.524 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:36.524 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:36.524 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:36.528 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:13:36.528 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:13:36.528 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:13:36.528 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:13:36.529 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:13:36.529 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:13:36.529 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:13:36.529 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=597 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:36.529 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=597 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:36.529 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=597 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:36.529 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=597 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:36.529 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=597 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:36.530 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=597 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:41.532 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:13:41.532 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:13:41.532 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:13:41.532 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:13:41.532 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:13:41.532 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:13:41.539 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:13:41.540 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:13:41.540 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:41.541 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:13:41.541 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:13:41.543 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:13:41.543 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:13:41.543 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:13:41.543 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:41.544 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:13:41.544 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:13:41.544 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:13:41.544 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:13:41.544 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:41.545 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:13:41.545 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:13:41.546 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:13:41.546 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:41.546 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:13:41.546 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:13:41.546 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:13:41.546 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:13:41.546 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:41.547 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:13:41.547 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:13:41.548 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:13:41.548 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:41.548 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:13:41.548 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:13:41.548 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:13:41.548 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:13:41.548 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:41.550 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:13:41.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:13:41.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:13:41.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:13:41.550 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:13:41.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:13:41.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:13:41.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:41.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:13:41.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:13:41.550 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:13:41.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:41.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:41.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:41.550 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:13:41.551 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:13:41.551 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:13:41.551 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:41.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:41.555 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:13:42.034 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:13:42.070 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:13:42.070 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:13:42.071 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:13:42.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:42.088 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:42.088 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:42.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:13:42.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:42.094 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:42.094 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:42.094 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:13:42.094 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:13:42.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:42.141 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:42.142 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:42.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:42.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:42.506 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:13:42.553 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:42.553 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:42.553 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:42.553 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:42.977 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:13:43.450 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:13:43.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:43.554 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:43.554 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:43.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:43.923 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:13:44.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:44.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:44.339 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:44.339 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:44.347 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:44.348 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:44.348 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:44.348 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:44.352 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:13:44.352 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:13:44.352 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:13:44.352 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:13:44.353 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:13:44.353 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:13:44.353 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:13:44.353 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=604 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:44.353 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=604 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:44.353 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=604 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:44.353 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=604 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:44.353 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=605 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:44.353 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=605 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:44.353 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=605 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:44.353 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=605 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:44.354 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=605 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:44.354 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=605 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:44.354 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=605 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:44.354 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=605 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:49.354 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:13:49.354 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:13:49.354 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:13:49.354 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:13:49.354 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:13:49.354 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:13:49.364 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:13:49.366 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:13:49.366 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:49.366 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:13:49.366 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:13:49.372 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:13:49.372 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:13:49.373 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:13:49.373 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:49.373 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:13:49.373 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:13:49.373 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:13:49.374 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:13:49.374 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:49.377 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:13:49.378 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:13:49.378 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:13:49.378 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:49.378 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:13:49.378 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:13:49.378 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:13:49.378 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:13:49.379 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:49.381 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:13:49.382 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:13:49.382 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:13:49.382 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:49.382 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:13:49.382 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:13:49.382 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:13:49.382 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:13:49.382 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:49.386 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:13:49.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:13:49.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:13:49.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:13:49.386 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:13:49.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:13:49.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:13:49.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:49.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:13:49.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:13:49.386 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:13:49.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:49.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:49.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:49.387 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:49.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:49.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:49.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:49.387 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:13:49.387 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:13:49.387 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:13:49.387 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:13:49.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:49.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:49.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:49.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:13:49.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:49.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:49.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:49.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:49.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:49.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:49.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:49.388 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:49.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:49.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:49.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:49.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:49.388 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:49.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:49.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:49.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:49.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:49.388 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:49.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:49.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:49.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:49.388 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:49.391 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:13:49.870 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:13:49.917 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:13:49.919 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:13:49.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:49.922 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:13:49.943 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:49.943 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:49.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:13:49.970 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:49.970 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:49.970 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:49.970 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:13:49.970 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:13:50.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:50.016 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:50.017 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:50.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:50.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:50.342 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:13:50.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:50.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:50.389 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:50.389 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:50.390 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:50.390 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:50.394 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:50.394 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:50.409 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:50.409 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:50.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:13:50.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:50.419 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:50.419 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:50.419 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:13:50.419 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:13:50.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:50.435 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:50.435 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:50.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:50.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:50.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:50.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:50.813 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:50.813 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:13:50.814 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:50.825 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:50.825 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:50.825 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:50.825 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:50.829 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:13:50.830 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:13:50.830 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:13:50.830 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:13:50.830 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:13:50.830 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:13:50.830 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:13:50.830 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=311 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:50.831 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=311 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:50.831 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=311 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:50.831 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=311 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:50.831 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=311 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:50.831 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=311 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:13:55.831 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:13:55.831 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:13:55.831 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:13:55.831 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:13:55.831 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:13:55.831 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:13:55.835 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:13:55.836 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:13:55.836 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:55.836 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:13:55.836 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:13:55.838 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:13:55.839 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:13:55.839 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:13:55.839 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:55.839 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:13:55.839 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:13:55.840 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:13:55.840 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:13:55.840 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:55.841 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:13:55.841 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:13:55.841 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:13:55.841 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:55.841 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:13:55.841 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:13:55.841 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:13:55.841 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:13:55.842 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:55.843 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:13:55.843 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:13:55.843 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:13:55.843 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:13:55.844 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:13:55.844 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:13:55.844 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:13:55.844 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:13:55.844 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:55.846 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:13:55.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:13:55.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:13:55.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:13:55.846 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:13:55.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:13:55.847 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:13:55.847 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:13:55.847 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:55.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:55.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:55.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:55.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:55.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:55.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:55.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:13:55.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:55.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:55.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:55.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:13:55.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:55.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:13:55.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:13:55.852 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:13:56.330 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:13:56.373 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:13:56.375 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:13:56.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:56.379 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:13:56.398 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:56.398 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:56.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:13:56.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:56.447 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:56.447 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:56.448 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:13:56.448 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:13:56.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:56.477 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:56.478 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:56.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:56.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:56.803 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:13:56.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:56.849 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:56.849 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:56.849 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:56.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:56.850 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:56.857 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:56.857 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:56.874 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:56.875 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:56.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:13:56.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:56.885 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:56.885 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:56.885 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:13:56.885 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:13:56.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:56.893 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:13:56.893 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:13:56.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:56.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:57.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:13:57.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:13:57.273 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:13:57.273 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:13:57.274 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:13:57.281 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:13:57.282 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:13:57.282 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:13:57.282 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:13:57.285 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:13:57.285 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:13:57.285 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:13:57.285 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:13:57.285 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:13:57.285 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:13:57.286 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:13:57.286 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=310 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:02.288 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:14:02.288 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:14:02.289 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:02.289 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:02.289 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:02.289 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:02.296 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:02.296 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:14:02.296 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:02.297 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:14:02.297 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:14:02.303 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:14:02.304 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:14:02.304 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:14:02.305 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:02.305 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:02.306 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:14:02.306 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:14:02.306 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:14:02.307 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:02.309 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:14:02.310 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:14:02.310 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:14:02.310 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:02.310 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:02.310 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:14:02.310 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:14:02.310 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:14:02.311 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:02.314 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:14:02.314 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:14:02.314 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:14:02.314 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:02.314 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:02.314 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:14:02.315 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:14:02.315 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:14:02.315 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:02.319 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:14:02.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:14:02.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:14:02.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:14:02.319 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:14:02.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:14:02.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:14:02.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:02.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:14:02.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:14:02.319 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:14:02.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:02.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:02.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:02.319 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:02.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:02.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:02.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:02.320 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:14:02.320 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:14:02.320 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:14:02.320 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:14:02.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:02.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:02.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:02.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:14:02.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:02.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:02.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:02.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:02.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:02.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:02.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:02.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:02.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:02.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:02.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:02.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:02.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:02.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:02.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:02.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:02.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:02.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:02.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:02.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:02.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:02.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:02.324 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:14:02.804 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:14:02.854 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:14:02.857 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:14:02.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:02.859 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:14:02.884 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:14:02.884 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:14:02.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:14:02.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:02.933 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:14:02.933 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:14:02.933 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:14:02.933 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:14:02.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:02.951 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:14:02.952 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:14:02.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:02.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:03.276 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:14:03.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:03.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:03.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:03.323 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:03.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:03.323 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:03.328 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:14:03.328 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:14:03.346 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:14:03.346 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:14:03.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:14:03.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:03.356 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:14:03.356 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:14:03.356 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:14:03.356 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:14:03.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:03.368 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:14:03.368 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:14:03.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:03.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:03.747 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:14:03.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:03.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:03.788 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:14:03.788 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:14:03.796 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:03.797 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:03.797 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:03.797 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:03.799 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:03.799 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:03.799 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:03.799 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:03.799 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:14:03.799 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:14:03.799 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:14:08.805 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:14:08.805 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:14:08.805 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:08.805 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:08.805 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:08.805 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:08.812 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:08.813 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:14:08.813 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:08.814 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:14:08.814 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:14:08.816 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:14:08.817 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:14:08.817 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:14:08.817 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:08.817 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:08.818 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:14:08.818 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:14:08.818 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:14:08.818 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:08.819 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:14:08.819 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:14:08.819 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:14:08.819 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:08.819 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:08.819 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:14:08.819 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:14:08.819 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:14:08.820 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:08.821 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:14:08.821 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:14:08.821 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:14:08.821 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:08.821 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:08.821 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:14:08.822 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:14:08.822 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:14:08.822 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:08.824 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:14:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:14:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:14:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:14:08.824 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:14:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:14:08.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:14:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:14:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:14:08.824 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:14:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:08.824 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:08.824 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:14:08.824 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:14:08.824 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:14:08.825 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:08.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:08.829 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:14:09.308 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:14:09.354 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:14:09.357 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:14:09.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:09.359 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:14:09.383 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:14:09.383 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:14:09.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:14:09.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:09.425 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:14:09.425 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:14:09.425 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:14:09.425 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:14:09.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:09.455 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:14:09.456 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:14:09.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:09.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:09.780 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:14:09.827 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:09.827 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:09.827 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:09.828 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:10.252 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:14:10.725 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:14:10.828 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:10.828 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:10.828 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:10.829 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:11.198 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:14:11.670 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:14:11.829 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:11.829 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:11.830 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:11.830 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:12.141 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:14:12.614 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:14:12.831 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:12.831 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:12.831 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:12.831 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:13.087 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:14:13.462 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:14:13.462 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:14:13.465 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:13.465 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:13.465 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:13.465 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:13.466 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:13.466 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:13.466 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:14:13.466 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:14:13.466 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:14:13.466 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:13.466 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:13.467 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1002 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:13.467 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1002 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:13.467 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1002 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:13.467 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1002 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:13.467 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1002 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:18.473 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:14:18.473 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:14:18.473 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:18.473 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:18.473 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:18.473 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:18.480 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:18.481 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:14:18.481 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:18.482 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:14:18.482 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:14:18.484 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:14:18.484 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:14:18.485 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:14:18.485 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:18.485 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:18.485 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:14:18.486 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:14:18.486 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:14:18.486 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:18.487 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:14:18.487 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:14:18.487 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:14:18.487 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:18.487 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:18.487 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:14:18.487 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:14:18.487 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:14:18.487 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:18.489 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:14:18.489 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:14:18.489 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:14:18.489 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:18.489 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:18.489 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:14:18.489 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:14:18.489 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:14:18.490 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:18.492 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:14:18.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:14:18.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:14:18.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:14:18.492 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:14:18.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:14:18.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:14:18.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:18.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:14:18.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:14:18.492 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:14:18.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:18.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:18.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:18.492 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:18.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:18.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:18.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:18.492 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:14:18.492 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:14:18.492 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:14:18.492 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:18.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:18.497 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:14:18.975 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:14:19.021 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:14:19.024 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:14:19.026 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:14:19.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:19.033 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:14:19.033 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:14:19.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:14:19.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:19.067 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:14:19.067 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:14:19.067 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:14:19.067 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:14:19.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:19.123 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:14:19.123 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:14:19.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:19.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:19.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:19.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:19.339 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:14:19.339 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:14:19.357 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:14:19.357 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:14:19.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:14:19.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:19.368 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:14:19.368 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:14:19.368 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:14:19.368 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:14:19.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:19.402 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:14:19.402 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:14:19.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:19.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:19.447 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:14:19.496 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:19.496 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:19.496 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:19.496 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:19.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:19.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:19.618 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:14:19.618 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:14:19.626 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:19.626 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:19.626 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:19.626 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:19.630 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:19.630 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:19.630 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:19.630 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:19.630 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:14:19.630 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:14:19.631 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:14:19.631 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=245 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:19.631 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=245 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:19.631 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=245 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:19.631 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=245 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:19.632 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=245 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:19.632 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=245 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:24.633 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:14:24.633 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:14:24.633 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:24.633 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:24.633 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:24.633 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:24.641 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:24.643 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:14:24.643 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:24.643 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:14:24.643 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:14:24.646 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:14:24.647 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:14:24.647 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:14:24.647 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:24.648 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:24.648 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:14:24.648 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:14:24.648 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:14:24.649 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:24.650 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:14:24.650 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:14:24.650 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:14:24.650 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:24.650 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:24.651 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:14:24.651 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:14:24.651 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:14:24.651 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:24.652 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:14:24.653 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:14:24.653 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:14:24.653 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:24.653 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:24.653 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:14:24.653 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:14:24.653 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:14:24.653 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:24.656 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:14:24.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:14:24.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:14:24.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:14:24.656 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:14:24.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:14:24.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:14:24.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:24.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:14:24.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:14:24.656 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:14:24.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:24.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:24.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:24.656 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:24.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:24.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:24.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:24.656 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:14:24.656 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:14:24.656 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:14:24.656 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:24.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:24.661 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:14:25.140 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:14:25.177 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:14:25.179 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:14:25.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:25.181 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:14:25.192 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:14:25.192 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:14:25.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:14:25.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:25.221 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:14:25.221 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:14:25.221 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:14:25.221 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:14:25.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:25.239 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:14:25.239 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:14:25.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:25.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:25.610 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:14:25.658 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:25.659 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:25.659 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:25.660 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:26.083 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:14:26.554 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:14:26.660 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:26.660 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:26.660 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:26.660 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:27.026 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:14:27.496 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:14:27.661 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:27.662 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:27.662 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:27.662 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:27.969 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:14:28.442 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:14:28.663 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:28.663 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:28.663 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:28.663 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:28.915 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:14:29.244 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:14:29.244 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:14:29.249 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:29.249 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:29.249 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:29.249 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:29.251 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:29.251 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:29.251 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:29.251 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:29.251 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:14:29.251 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:14:29.251 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:14:29.251 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=992 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:29.251 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=993 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:29.251 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=993 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:29.251 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=993 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:29.251 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=993 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:29.251 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=993 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:29.251 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=993 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:29.251 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=993 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:29.251 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=993 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:34.257 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:14:34.257 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:14:34.257 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:34.257 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:34.257 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:34.257 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:34.265 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:34.266 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:14:34.266 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:34.266 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:14:34.266 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:14:34.269 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:14:34.269 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:14:34.270 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:14:34.270 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:34.270 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:34.270 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:14:34.271 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:14:34.271 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:14:34.271 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:34.272 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:14:34.272 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:14:34.272 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:14:34.272 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:34.272 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:34.273 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:14:34.273 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:14:34.273 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:14:34.273 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:34.274 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:14:34.275 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:14:34.275 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:14:34.275 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:34.275 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:34.275 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:14:34.275 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:14:34.275 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:14:34.275 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:34.277 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:14:34.278 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:14:34.278 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:14:34.278 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:34.278 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:34.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:34.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:34.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:34.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:34.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:34.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:34.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:34.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:34.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:34.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:34.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:34.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:34.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:34.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:34.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:34.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:34.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:34.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:34.283 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:14:34.760 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:14:34.805 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:14:34.808 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:14:34.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:34.810 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:14:34.836 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:14:34.836 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:14:34.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:14:34.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:34.880 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:14:34.881 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:14:34.881 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:14:34.881 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:14:34.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:34.908 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:14:34.909 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:14:34.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:34.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:35.233 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:14:35.280 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:35.281 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:35.281 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:35.281 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:35.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:35.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:35.628 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:14:35.628 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:14:35.637 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:35.638 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:35.638 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:35.638 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:35.641 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:35.641 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:35.641 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:35.641 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:35.641 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:14:35.641 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:14:35.641 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:14:40.645 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:14:40.645 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:14:40.645 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:40.645 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:40.645 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:40.645 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:40.655 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:40.656 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:14:40.656 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:40.656 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:14:40.656 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:14:40.658 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:14:40.658 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:14:40.658 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:14:40.658 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:40.658 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:40.658 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:14:40.658 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:14:40.658 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:14:40.658 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:40.660 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:14:40.660 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:14:40.660 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:14:40.660 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:40.660 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:40.660 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:14:40.660 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:14:40.660 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:14:40.660 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:40.661 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:14:40.661 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:14:40.661 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:14:40.661 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:40.661 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:40.661 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:14:40.661 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:14:40.661 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:14:40.661 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:40.663 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:14:40.663 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:14:40.663 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:14:40.663 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:14:40.663 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:14:40.663 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:14:40.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:14:40.663 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:14:40.664 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:14:40.664 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:14:40.664 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:40.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:40.668 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:14:41.147 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:14:41.187 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:14:41.190 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:14:41.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:41.192 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:14:41.212 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:14:41.212 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:14:41.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:14:41.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:41.241 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:14:41.242 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:14:41.242 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:14:41.242 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:14:41.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:41.295 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:14:41.295 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:14:41.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:41.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:41.619 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:14:41.667 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:41.667 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:41.667 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:41.668 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:42.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:42.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:42.014 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:14:42.014 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:14:42.024 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:42.024 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:42.025 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:42.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:42.027 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:42.027 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:42.027 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:42.027 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:42.027 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:14:42.027 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:14:42.027 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:14:47.032 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:14:47.032 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:14:47.032 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:47.032 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:47.032 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:47.032 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:47.038 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:47.039 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:14:47.039 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:47.040 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:14:47.040 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:14:47.043 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:14:47.043 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:14:47.043 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:14:47.043 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:47.044 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:47.044 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:14:47.045 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:14:47.045 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:14:47.045 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:47.047 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:14:47.047 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:14:47.047 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:14:47.047 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:47.048 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:47.048 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:14:47.048 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:14:47.048 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:14:47.048 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:47.049 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:14:47.049 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:14:47.049 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:14:47.049 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:47.050 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:47.050 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:14:47.050 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:14:47.050 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:14:47.050 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:47.053 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:14:47.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:14:47.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:14:47.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:14:47.053 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:14:47.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:14:47.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:14:47.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:47.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:14:47.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:14:47.053 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:14:47.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:47.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:47.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:47.053 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:47.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:47.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:47.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:47.053 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:14:47.053 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:14:47.053 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:14:47.053 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:14:47.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:47.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:47.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:47.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:14:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:47.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:47.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:47.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:47.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:47.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:47.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:47.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:47.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:47.058 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:14:47.537 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:14:47.579 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:14:47.581 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:14:47.584 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:14:47.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:47.607 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:14:47.607 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:14:47.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:14:47.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:47.653 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:14:47.653 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:14:47.653 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:14:47.654 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:14:47.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:47.685 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:14:47.685 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:14:47.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:47.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:48.009 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:14:48.056 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:48.056 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:48.056 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:48.056 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:48.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:48.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:48.404 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:14:48.404 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:14:48.413 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:48.413 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:48.414 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:48.414 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:48.415 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:48.415 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:14:48.415 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:14:48.415 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:14:48.415 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:48.415 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:48.415 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:48.415 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:48.415 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:48.415 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:48.415 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:48.415 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:48.415 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:14:53.420 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:14:53.420 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:14:53.420 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:53.420 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:53.420 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:53.420 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:53.427 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:53.427 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:14:53.427 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:53.427 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:14:53.427 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:14:53.429 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:14:53.429 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:14:53.429 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:14:53.429 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:53.429 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:53.429 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:14:53.430 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:14:53.430 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:14:53.430 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:53.431 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:14:53.432 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:14:53.432 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:14:53.432 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:53.432 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:53.432 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:14:53.432 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:14:53.432 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:14:53.432 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:53.433 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:14:53.433 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:14:53.433 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:14:53.433 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:53.433 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:53.433 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:14:53.433 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:14:53.433 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:14:53.434 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:53.435 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:14:53.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:14:53.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:14:53.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:14:53.435 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:14:53.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:14:53.436 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:14:53.436 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:14:53.436 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:53.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:53.440 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:14:53.918 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:14:53.961 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:14:53.962 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:14:53.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:53.964 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:14:53.978 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:14:53.978 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:14:53.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:14:54.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:54.019 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:14:54.019 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:14:54.020 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:14:54.020 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:14:54.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:54.066 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:14:54.067 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:14:54.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:54.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:54.391 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:14:54.438 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:54.439 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:54.439 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:54.439 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:54.864 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:14:54.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:14:54.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:14:54.919 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:14:54.919 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:14:54.930 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:54.930 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:54.930 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:54.930 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:54.932 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:54.932 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:54.932 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:54.932 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:54.932 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:14:54.932 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:14:54.932 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:14:59.938 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:14:59.938 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:14:59.938 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:59.938 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:59.938 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:59.938 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:59.947 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:14:59.948 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:14:59.949 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:59.949 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:14:59.949 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:14:59.954 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:14:59.954 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:14:59.955 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:14:59.955 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:59.955 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:14:59.956 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:14:59.956 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:14:59.956 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:14:59.957 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:14:59.959 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:14:59.959 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:14:59.960 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:14:59.960 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:59.960 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:14:59.961 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:14:59.961 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:14:59.961 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:14:59.962 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:14:59.963 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:14:59.964 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:14:59.964 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:14:59.964 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:14:59.964 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:14:59.964 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:14:59.964 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:14:59.964 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:14:59.964 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:14:59.969 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:14:59.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:14:59.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:14:59.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:14:59.969 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:14:59.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:14:59.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:14:59.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:59.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:14:59.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:14:59.970 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:14:59.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:59.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:59.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:59.970 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:14:59.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:59.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:59.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:59.970 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:14:59.970 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:14:59.970 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:14:59.971 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:14:59.971 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:59.971 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:59.971 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:59.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:14:59.971 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:59.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:59.971 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:59.971 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:59.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:59.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:59.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:14:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:59.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:59.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:59.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:14:59.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:59.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:14:59.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:14:59.975 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:15:00.454 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:15:00.500 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:15:00.503 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:15:00.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:15:00.504 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:15:00.526 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:15:00.526 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:15:00.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:15:00.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:15:00.573 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:15:00.574 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:15:00.575 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:15:00.575 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:15:00.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:15:00.601 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:15:00.602 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:15:00.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:15:00.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:15:00.927 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:15:00.974 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:15:00.975 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:15:00.975 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:15:00.977 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:15:01.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:15:01.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:15:01.320 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:15:01.320 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:15:01.332 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:15:01.332 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:15:01.332 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:15:01.332 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:15:01.334 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:15:01.334 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:15:01.334 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:15:01.334 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:15:01.334 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:15:01.334 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:15:01.334 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:15:06.338 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:15:06.338 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:15:06.339 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:15:06.339 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:15:06.339 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:15:06.339 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:15:06.348 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:15:06.349 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:15:06.349 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:15:06.349 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:15:06.349 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:15:06.353 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:15:06.353 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:15:06.353 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:15:06.353 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:15:06.353 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:15:06.353 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:15:06.353 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:15:06.353 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:15:06.354 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:15:06.356 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:15:06.357 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:15:06.357 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:15:06.357 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:15:06.357 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:15:06.357 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:15:06.357 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:15:06.357 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:15:06.357 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:15:06.360 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:15:06.360 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:15:06.360 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:15:06.360 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:15:06.360 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:15:06.360 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:15:06.361 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:15:06.361 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:15:06.361 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:15:06.365 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:15:06.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:15:06.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:15:06.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:15:06.365 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:15:06.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:15:06.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:15:06.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:06.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:15:06.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:15:06.365 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:15:06.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:06.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:06.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:06.365 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:15:06.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:06.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:06.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:06.365 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:15:06.365 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:15:06.366 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:15:06.366 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:15:06.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:06.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:06.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:06.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:15:06.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:06.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:06.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:06.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:06.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:06.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:06.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:06.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:06.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:06.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:06.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:06.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:06.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:06.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:06.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:06.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:06.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:06.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:06.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:06.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:06.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:06.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:06.370 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:15:06.849 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:15:06.889 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:15:06.891 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:15:06.893 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:15:06.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:15:06.913 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:15:06.913 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:15:06.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:15:06.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:15:06.955 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:15:06.955 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:15:06.956 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:15:06.956 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:15:06.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:15:06.998 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:15:06.998 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:15:06.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:15:06.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:15:07.321 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:15:07.368 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:15:07.369 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:15:07.369 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:15:07.369 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:15:07.793 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:15:07.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:15:07.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:15:07.851 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:15:07.852 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:15:07.862 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:15:07.862 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:15:07.862 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:15:07.863 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:15:07.866 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:15:07.867 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:15:07.867 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:15:07.867 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:15:07.867 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:15:07.867 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:15:07.867 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:15:07.867 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=324 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:15:07.868 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=324 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:15:07.868 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=324 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:15:07.868 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=324 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:15:07.868 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=324 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:15:07.868 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=324 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:15:07.868 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=324 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:15:12.870 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:15:12.870 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:15:12.870 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:15:12.870 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:15:12.870 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:15:12.870 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:15:12.878 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:15:12.879 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:15:12.879 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:15:12.879 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:15:12.879 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:15:12.882 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:15:12.882 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:15:12.883 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:15:12.883 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:15:12.883 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:15:12.883 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:15:12.883 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:15:12.884 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:15:12.884 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:15:12.885 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:15:12.885 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:15:12.885 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:15:12.885 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:15:12.885 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:15:12.885 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:15:12.885 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:15:12.885 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:15:12.886 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:15:12.887 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:15:12.887 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:15:12.887 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:15:12.887 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:15:12.887 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:15:12.887 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:15:12.887 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:15:12.888 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:15:12.888 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:15:12.890 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:15:12.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:15:12.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:15:12.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:15:12.890 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:15:12.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:15:12.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:15:12.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:12.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:15:12.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:15:12.890 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:15:12.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:12.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:12.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:15:12.891 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:15:12.891 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:15:12.891 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:12.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:12.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:12.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:12.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:12.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:12.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:12.895 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:15:13.374 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:15:13.414 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:15:13.416 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:15:13.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:15:13.418 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:15:13.438 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:15:13.438 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:15:13.439 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:15:13.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:15:13.443 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:15:13.443 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:15:13.443 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:15:13.443 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:15:13.847 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:15:13.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:15:13.894 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:15:13.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:15:13.894 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:15:14.318 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:15:14.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:15:14.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:15:14.592 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:15:14.592 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:15:14.610 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:15:14.610 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:15:14.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:15:14.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:15:14.611 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:15:14.611 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:15:14.611 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:15:14.611 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:15:14.790 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:15:14.894 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:15:14.894 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:15:14.895 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:15:14.895 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:15:15.263 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:15:15.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 02:15:15.735 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:15:15.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 02:15:15.775 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:15:15.775 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:15:15.784 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:15:15.784 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:15:15.784 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:15:15.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:15:15.786 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:15:15.786 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:15:15.786 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:15:15.786 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:15:15.786 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:15:15.786 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:15:15.786 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:15:15.786 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=625 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:15:15.786 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=625 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:15:15.786 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=625 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:15:15.787 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=625 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:15:15.787 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=625 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:15:15.787 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=625 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:15:20.792 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:15:20.792 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:15:20.792 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:15:20.792 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:15:20.792 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:15:20.792 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:15:20.800 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:15:20.801 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:15:20.801 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:15:20.802 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:15:20.802 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:15:20.805 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:15:20.806 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:15:20.806 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:15:20.806 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:15:20.807 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:15:20.807 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:15:20.807 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:15:20.807 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:15:20.808 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:15:20.809 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:15:20.809 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:15:20.809 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:15:20.809 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:15:20.810 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:15:20.810 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:15:20.810 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:15:20.810 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:15:20.810 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:15:20.812 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:15:20.812 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:15:20.812 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:15:20.812 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:15:20.812 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:15:20.813 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:15:20.813 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:15:20.813 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:15:20.813 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:15:20.816 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:15:20.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:15:20.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:15:20.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:15:20.816 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:15:20.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:15:20.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:15:20.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:20.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:15:20.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:15:20.816 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:15:20.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:20.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:20.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:20.816 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:15:20.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:20.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:20.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:20.816 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:15:20.816 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:15:20.816 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:15:20.816 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:20.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:20.821 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:15:21.300 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:15:21.336 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:15:21.337 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:15:21.338 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:15:21.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:15:21.351 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:15:21.351 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:15:21.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:15:21.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:15:21.355 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:15:21.355 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:15:21.356 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:15:21.356 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:15:21.772 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:15:21.819 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:15:21.819 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:15:21.819 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:15:21.819 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:15:22.243 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:15:22.717 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:15:22.819 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:15:22.820 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:15:22.820 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:15:22.820 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:15:23.189 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:15:23.661 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:15:23.821 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:15:23.821 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:15:23.821 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:15:23.821 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:15:24.132 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:15:24.605 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:15:24.822 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:15:24.823 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:15:24.823 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:15:24.823 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:15:25.078 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:15:25.550 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:15:25.824 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:15:25.824 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:15:25.824 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:15:25.825 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:15:26.021 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:15:26.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 02:15:26.282 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:15:26.282 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:15:26.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:15:26.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:15:26.493 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:15:26.967 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:15:27.439 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:15:27.913 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:15:28.386 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:15:28.858 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:15:29.329 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:15:29.802 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:15:30.276 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:15:30.749 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:15:31.223 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:15:31.697 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:15:32.170 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:15:32.642 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:15:33.116 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:15:33.589 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:15:34.062 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:15:34.536 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:15:35.008 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:15:35.482 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:15:35.955 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:15:36.427 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:15:36.901 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:15:37.373 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:15:37.845 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:15:38.319 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:15:38.792 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:15:39.264 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:15:39.738 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:15:40.210 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:15:40.682 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:15:41.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 02:15:41.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:15:41.005 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:15:41.005 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:15:41.014 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:15:41.015 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:15:41.015 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:15:41.015 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:15:41.019 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:15:41.019 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:15:41.019 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:15:41.020 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:15:41.020 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:15:41.020 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:15:41.020 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:15:41.020 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4359 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:15:41.020 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4359 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:15:41.020 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4359 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:15:41.021 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4359 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:15:41.021 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4359 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:15:41.021 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4359 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:15:46.022 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:15:46.022 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:15:46.022 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:15:46.022 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:15:46.022 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:15:46.022 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:15:46.030 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:15:46.032 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:15:46.032 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:15:46.033 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:15:46.033 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:15:46.036 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:15:46.037 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:15:46.037 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:15:46.037 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:15:46.038 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:15:46.038 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:15:46.038 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:15:46.039 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:15:46.039 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:15:46.040 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:15:46.040 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:15:46.041 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:15:46.041 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:15:46.041 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:15:46.041 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:15:46.041 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:15:46.041 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:15:46.042 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:15:46.043 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:15:46.043 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:15:46.043 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:15:46.043 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:15:46.044 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:15:46.044 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:15:46.044 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:15:46.044 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:15:46.044 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:15:46.047 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:15:46.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:15:46.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:15:46.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:15:46.047 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:15:46.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:15:46.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:15:46.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:46.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:15:46.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:15:46.047 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:15:46.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:46.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:46.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:46.047 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:15:46.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:46.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:46.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:46.048 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:15:46.048 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:15:46.048 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:15:46.048 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:15:46.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:46.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:46.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:46.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:15:46.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:46.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:46.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:46.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:46.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:46.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:46.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:46.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:46.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:46.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:46.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:46.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:46.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:46.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:15:46.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:46.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:46.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:46.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:15:46.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:46.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:15:46.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:46.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:15:46.052 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:15:46.531 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:15:46.572 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:15:46.574 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:15:46.576 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:15:46.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:15:46.597 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:15:46.597 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:15:46.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:15:46.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:15:46.602 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:15:46.602 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:15:46.603 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:15:46.603 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:15:47.003 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:15:47.050 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:15:47.050 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:15:47.051 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:15:47.051 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:15:47.474 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:15:47.947 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:15:48.051 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:15:48.051 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:15:48.051 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:15:48.051 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:15:48.419 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:15:48.892 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:15:49.053 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:15:49.053 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:15:49.053 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:15:49.053 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:15:49.362 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:15:49.836 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:15:50.054 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:15:50.054 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:15:50.055 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:15:50.055 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:15:50.308 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:15:50.780 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:15:51.055 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:15:51.056 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:15:51.056 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:15:51.056 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:15:51.251 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:15:51.507 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 02:15:51.515 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:15:51.515 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:15:51.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:15:51.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:15:51.725 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:15:52.197 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:15:52.669 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:15:53.143 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:15:53.616 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:15:54.088 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:15:54.561 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:15:55.034 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:15:55.506 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:15:55.980 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:15:56.452 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:15:56.925 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:15:57.399 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:15:57.871 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:15:58.343 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:15:58.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 02:15:58.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:15:58.517 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:15:58.517 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:15:58.528 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:15:58.528 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:15:58.528 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:15:58.528 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:15:58.532 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:15:58.533 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:15:58.533 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:15:58.533 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:15:58.533 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:15:58.533 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:15:58.533 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:15:58.533 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2695 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:15:58.533 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2695 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:15:58.534 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2695 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:15:58.534 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2695 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:15:58.534 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2695 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:15:58.534 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2695 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:16:03.535 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:16:03.535 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:16:03.535 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:16:03.535 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:16:03.535 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:16:03.535 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:16:03.543 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:16:03.544 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:16:03.545 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:16:03.545 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:16:03.545 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:16:03.548 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:16:03.549 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:16:03.549 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:16:03.549 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:16:03.550 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:16:03.550 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:16:03.550 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:16:03.550 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:16:03.551 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:03.552 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:16:03.552 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:16:03.552 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:16:03.552 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:16:03.552 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:16:03.553 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:16:03.553 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:16:03.553 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:16:03.553 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:03.555 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:16:03.555 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:16:03.555 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:16:03.555 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:16:03.555 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:16:03.555 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:16:03.555 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:16:03.555 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:16:03.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:03.558 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:16:03.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:16:03.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:16:03.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:16:03.559 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:16:03.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:16:03.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:16:03.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:03.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:16:03.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:16:03.559 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:16:03.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:03.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:03.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:03.559 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:03.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:03.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:03.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:03.559 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:16:03.559 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:16:03.559 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:16:03.559 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:16:03.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:03.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:03.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:03.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:16:03.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:03.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:03.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:03.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:03.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:03.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:03.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:03.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:03.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:03.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:03.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:03.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:03.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:03.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:03.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:03.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:03.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:03.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:03.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:03.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:03.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:03.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:03.564 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:16:04.042 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:16:04.083 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:16:04.086 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:16:04.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:16:04.090 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:16:04.114 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:16:04.114 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:16:04.115 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:16:04.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:16:04.120 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:16:04.120 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:16:04.120 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:16:04.120 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:16:04.513 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:16:04.562 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:04.562 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:04.563 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:04.563 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:04.985 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:16:05.456 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:16:05.564 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:05.564 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:05.564 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:05.564 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:05.929 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:16:06.401 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:16:06.564 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:06.565 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:06.565 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:06.565 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:06.873 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:16:07.344 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:16:07.565 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:07.566 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:07.566 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:07.566 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:07.815 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:16:08.289 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:16:08.566 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:08.567 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:08.567 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:08.567 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:08.761 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:16:09.017 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 02:16:09.024 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:16:09.025 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:16:09.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:16:09.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:16:09.233 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:16:09.707 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:16:10.179 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:16:10.652 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:16:11.125 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:16:11.597 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:16:12.070 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:16:12.543 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:16:13.015 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:16:13.488 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:16:13.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 02:16:13.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:16:13.613 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:16:13.613 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:16:13.622 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:13.622 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:13.622 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:13.622 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:13.626 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:16:13.626 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:16:13.626 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:16:13.626 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:16:13.626 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:16:13.626 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:16:13.626 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:16:13.626 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2174 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:16:13.626 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2174 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:16:13.626 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2174 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:16:13.626 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2174 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:16:13.626 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2174 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:16:13.626 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2174 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:16:18.629 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:16:18.629 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:16:18.629 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:16:18.629 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:16:18.629 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:16:18.629 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:16:18.635 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:16:18.637 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:16:18.637 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:16:18.638 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:16:18.638 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:16:18.643 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:16:18.643 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:16:18.644 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:16:18.644 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:16:18.644 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:16:18.645 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:16:18.645 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:16:18.645 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:16:18.646 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:18.648 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:16:18.649 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:16:18.649 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:16:18.649 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:16:18.650 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:16:18.650 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:16:18.650 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:16:18.650 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:16:18.651 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:18.652 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:16:18.653 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:16:18.653 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:16:18.653 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:16:18.653 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:16:18.653 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:16:18.653 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:16:18.653 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:16:18.654 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:18.657 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:16:18.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:16:18.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:16:18.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:16:18.657 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:16:18.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:16:18.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:16:18.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:18.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:16:18.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:16:18.658 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:16:18.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:18.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:18.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:18.658 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:18.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:18.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:18.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:18.658 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:16:18.658 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:16:18.658 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:16:18.658 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:16:18.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:18.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:18.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:18.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:16:18.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:18.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:18.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:18.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:18.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:18.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:18.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:18.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:18.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:18.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:18.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:18.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:18.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:18.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:18.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:18.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:18.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:18.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:18.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:18.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:18.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:18.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:18.663 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:16:19.142 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:16:19.183 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:16:19.186 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:16:19.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:16:19.189 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:16:19.212 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:16:19.213 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:16:19.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:16:19.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:16:19.218 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:16:19.218 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:16:19.219 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:16:19.219 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:16:19.614 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:16:19.660 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:19.661 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:19.661 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:19.661 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:20.085 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:16:20.559 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:16:20.661 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:20.662 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:20.662 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:20.662 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:21.031 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:16:21.502 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:16:21.662 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:21.663 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:21.663 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:21.663 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:21.974 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:16:22.447 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:16:22.664 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:22.664 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:22.664 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:22.664 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:22.920 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:16:23.392 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:16:23.665 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:23.666 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:23.666 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:23.666 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:23.865 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:16:24.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 02:16:24.123 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:16:24.123 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:16:24.123 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:16:24.123 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:16:24.338 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:16:24.810 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:16:25.283 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:16:25.756 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:16:26.228 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:16:26.702 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:16:27.174 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:16:27.647 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:16:28.120 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:16:28.593 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:16:28.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 02:16:28.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:16:28.721 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:16:28.721 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:16:28.731 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:28.731 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:28.731 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:28.731 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:28.734 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:16:28.734 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:16:28.734 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:16:28.734 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:16:28.734 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:16:28.734 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:16:28.734 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:16:28.734 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2174 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:16:28.734 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2174 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:16:28.734 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2174 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:16:28.734 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2174 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:16:28.734 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2174 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:16:28.734 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2174 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:16:33.738 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:16:33.738 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:16:33.738 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:16:33.738 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:16:33.738 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:16:33.738 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:16:33.746 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:16:33.746 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:16:33.746 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:16:33.746 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:16:33.747 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:16:33.750 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:16:33.750 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:16:33.750 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:16:33.750 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:16:33.750 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:16:33.750 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:16:33.750 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:16:33.750 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:16:33.751 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:33.754 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:16:33.754 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:16:33.754 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:16:33.754 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:16:33.755 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:16:33.755 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:16:33.755 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:16:33.755 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:16:33.755 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:33.759 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:16:33.759 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:16:33.759 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:16:33.759 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:16:33.760 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:16:33.760 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:16:33.760 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:16:33.760 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:16:33.760 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:33.766 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:16:33.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:16:33.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:16:33.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:16:33.766 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:16:33.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:16:33.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:16:33.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:33.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:16:33.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:16:33.766 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:16:33.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:33.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:33.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:33.766 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:33.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:33.767 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:16:33.767 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:16:33.767 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:16:33.767 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:16:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:33.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:16:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:33.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:33.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:33.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:33.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:33.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:33.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:33.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:33.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:33.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:33.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:33.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:33.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:33.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:33.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:33.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:33.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:33.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:33.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:33.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:33.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:33.771 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:16:34.249 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:16:34.294 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:16:34.295 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:16:34.297 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:16:34.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:16:34.316 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:16:34.316 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:16:34.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:16:34.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:16:34.322 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:16:34.322 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:16:34.322 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:16:34.322 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:16:34.721 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:16:34.770 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:34.771 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:34.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:34.771 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:35.193 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:16:35.663 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:16:35.772 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:35.772 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:35.772 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:35.773 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:36.137 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:16:36.609 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:16:36.773 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:36.773 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:36.774 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:36.774 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:37.081 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:16:37.552 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:16:37.773 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:37.774 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:37.774 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:37.774 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:38.026 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:16:38.498 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:16:38.775 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:38.775 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:38.775 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:38.775 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:38.970 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:16:39.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 02:16:39.232 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:16:39.232 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:16:39.233 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:16:39.233 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:16:39.443 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:16:39.916 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:16:40.388 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:16:40.862 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:16:41.328 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:16:41.796 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:16:42.261 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:16:42.725 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:16:43.194 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:16:43.668 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:16:43.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 02:16:43.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:16:43.792 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:16:43.793 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:16:43.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:43.799 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:43.799 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:43.799 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:43.799 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:16:43.799 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:16:43.799 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:16:43.799 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:16:43.799 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:16:43.799 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:16:43.800 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:16:48.806 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:16:48.806 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:16:48.806 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:16:48.806 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:16:48.806 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:16:48.806 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:16:48.815 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:16:48.817 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:16:48.817 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:16:48.817 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:16:48.817 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:16:48.824 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:16:48.824 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:16:48.824 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:16:48.825 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:16:48.825 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:16:48.826 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:16:48.826 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:16:48.826 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:16:48.826 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:48.829 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:16:48.829 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:16:48.829 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:16:48.829 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:16:48.830 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:16:48.830 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:16:48.830 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:16:48.830 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:16:48.830 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:48.833 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:16:48.833 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:16:48.833 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:16:48.833 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:16:48.834 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:16:48.834 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:16:48.834 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:16:48.834 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:16:48.834 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:48.838 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:16:48.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:16:48.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:16:48.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:16:48.838 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:16:48.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:16:48.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:16:48.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:48.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:16:48.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:16:48.838 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:16:48.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:48.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:48.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:48.838 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:48.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:48.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:48.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:48.839 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:16:48.839 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:16:48.839 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:16:48.839 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:16:48.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:48.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:48.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:48.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:16:48.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:48.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:48.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:48.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:48.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:48.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:48.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:48.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:48.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:48.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:48.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:16:48.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:48.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:48.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:48.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:48.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:48.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:48.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:16:48.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:48.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:16:48.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:48.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:16:48.844 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:16:49.322 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:16:49.372 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:16:49.374 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:16:49.376 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:16:49.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:16:49.794 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:16:49.843 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:49.843 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:49.843 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:49.843 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:50.269 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:16:50.741 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:16:50.844 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:50.844 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:50.844 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:50.845 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:51.215 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:16:51.688 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:16:51.846 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:51.846 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:51.846 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:51.846 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:52.159 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:16:52.649 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:16:52.847 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:52.848 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:52.848 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:52.848 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:53.121 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:16:53.596 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:16:53.849 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:53.849 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:53.849 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:53.849 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:54.068 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:16:54.543 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:16:55.015 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:16:55.489 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:16:55.961 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:16:56.433 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:16:56.908 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:16:57.380 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:16:57.855 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:16:58.327 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:16:58.801 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:16:59.273 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:16:59.388 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:16:59.388 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:16:59.389 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:16:59.389 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:16:59.390 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:16:59.390 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:16:59.390 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:16:59.390 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:16:59.390 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:16:59.390 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:16:59.390 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:16:59.390 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2271 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:16:59.390 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2271 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:16:59.390 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2271 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:16:59.390 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2271 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:16:59.390 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2271 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:16:59.390 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2271 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:16:59.390 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2271 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:17:04.394 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:17:04.395 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:17:04.395 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:17:04.395 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:17:04.395 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:17:04.395 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:17:04.397 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:17:04.398 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:17:04.398 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:17:04.398 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:17:04.398 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:17:04.399 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:17:04.399 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:17:04.399 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:17:04.399 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:17:04.399 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:17:04.399 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:17:04.399 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:17:04.399 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:17:04.400 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:17:04.400 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:17:04.400 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:17:04.400 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:17:04.400 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:17:04.400 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:17:04.400 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:17:04.400 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:17:04.400 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:17:04.400 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:17:04.401 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:17:04.401 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:17:04.402 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:17:04.402 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:17:04.402 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:17:04.402 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:17:04.402 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:17:04.402 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:17:04.402 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:17:04.404 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:17:04.404 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:17:04.404 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:04.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:04.405 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:17:04.405 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:17:04.405 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:17:04.405 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:17:04.405 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:17:04.405 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:17:04.405 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:17:09.413 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:17:09.413 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:17:09.413 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:17:09.413 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:17:09.413 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:17:09.413 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:17:09.420 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:17:09.422 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:17:09.422 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:17:09.422 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:17:09.423 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:17:09.426 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:17:09.427 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:17:09.427 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:17:09.427 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:17:09.428 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:17:09.428 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:17:09.429 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:17:09.429 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:17:09.429 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:17:09.431 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:17:09.431 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:17:09.431 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:17:09.431 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:17:09.431 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:17:09.432 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:17:09.432 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:17:09.432 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:17:09.432 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:17:09.434 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:17:09.435 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:17:09.435 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:17:09.435 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:17:09.435 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:17:09.435 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:17:09.435 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:17:09.435 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:17:09.435 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:17:09.439 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:17:09.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:17:09.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:17:09.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:17:09.439 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:17:09.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:17:09.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:17:09.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:09.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:17:09.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:17:09.439 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:17:09.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:09.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:09.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:09.439 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:17:09.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:09.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:09.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:09.439 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:17:09.439 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:17:09.439 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:17:09.440 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:17:09.440 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:09.440 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:09.440 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:09.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:17:09.440 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:09.440 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:09.440 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:09.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:09.440 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:09.440 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:09.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:09.440 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:09.440 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:09.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:09.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:09.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:09.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:09.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:09.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:09.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:09.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:09.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:09.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:09.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:09.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:09.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:09.444 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:17:09.923 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:17:09.963 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:17:09.966 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:17:09.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:17:09.968 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:17:09.972 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:17:09.972 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:17:09.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:17:09.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:17:09.972 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:17:09.973 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:17:09.973 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:17:09.973 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:17:10.395 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:17:10.442 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:17:10.442 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:17:10.443 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:17:10.443 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:17:10.866 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:17:11.339 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:17:11.442 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:17:11.462 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:17:11.463 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:17:11.463 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:17:11.812 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:17:12.284 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:17:12.463 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:17:12.463 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:17:12.463 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:17:12.464 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:17:12.755 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:17:13.228 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:17:13.464 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:17:13.465 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:17:13.465 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:17:13.465 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:17:13.700 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:17:14.172 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:17:14.466 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:17:14.466 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:17:14.466 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:17:14.466 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:17:14.643 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:17:15.116 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:17:15.589 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:17:16.061 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:17:16.532 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:17:17.005 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:17:17.478 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:17:17.950 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:17:18.018 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:17:18.018 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:17:18.024 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:17:18.024 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:17:18.025 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:17:18.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:17:18.026 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:17:18.026 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:17:18.026 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:17:18.026 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:17:18.026 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:17:18.026 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:17:18.026 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:17:23.031 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:17:23.031 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:17:23.031 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:17:23.031 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:17:23.031 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:17:23.031 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:17:23.040 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:17:23.042 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:17:23.042 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:17:23.042 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:17:23.042 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:17:23.046 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:17:23.046 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:17:23.047 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:17:23.047 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:17:23.047 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:17:23.048 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:17:23.048 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:17:23.048 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:17:23.048 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:17:23.050 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:17:23.050 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:17:23.050 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:17:23.050 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:17:23.050 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:17:23.050 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:17:23.050 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:17:23.050 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:17:23.050 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:17:23.053 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:17:23.053 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:17:23.053 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:17:23.053 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:17:23.053 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:17:23.053 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:17:23.053 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:17:23.053 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:17:23.053 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:17:23.056 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:17:23.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:17:23.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:17:23.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:17:23.057 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:17:23.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:17:23.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:17:23.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:23.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:17:23.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:17:23.057 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:17:23.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:23.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:23.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:23.057 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:17:23.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:23.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:23.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:23.057 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:17:23.057 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:17:23.057 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:17:23.057 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:17:23.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:23.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:23.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:23.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:17:23.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:23.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:23.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:23.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:23.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:23.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:23.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:23.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:23.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:23.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:23.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:23.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:23.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:23.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:23.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:23.059 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:17:23.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:23.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:23.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:23.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:23.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:23.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:23.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:23.059 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:17:23.059 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:17:23.059 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:17:23.059 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:17:23.059 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:17:23.059 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:17:28.066 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:17:28.066 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:17:28.066 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:17:28.066 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:17:28.066 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:17:28.066 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:17:28.070 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:17:28.071 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:17:28.071 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:17:28.071 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:17:28.072 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:17:28.074 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:17:28.074 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:17:28.074 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:17:28.074 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:17:28.075 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:17:28.075 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:17:28.075 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:17:28.075 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:17:28.075 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:17:28.077 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:17:28.077 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:17:28.077 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:17:28.077 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:17:28.077 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:17:28.077 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:17:28.077 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:17:28.077 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:17:28.077 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:17:28.079 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:17:28.079 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:17:28.079 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:17:28.079 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:17:28.079 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:17:28.079 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:17:28.079 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:17:28.079 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:17:28.079 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:17:28.082 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:17:28.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:17:28.082 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:17:28.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:17:28.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:17:28.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:17:28.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:17:28.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:17:28.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:28.082 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:17:28.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:28.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:17:28.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:28.082 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:17:28.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:28.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:28.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:28.082 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:17:28.082 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:17:28.082 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:17:28.083 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:28.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:28.087 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:17:28.565 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:17:28.610 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:17:28.612 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:17:28.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:17:28.615 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:17:28.618 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:17:28.618 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:17:28.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:17:28.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:17:28.619 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:17:28.619 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:17:28.620 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:17:28.620 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:17:29.037 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:17:29.085 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:17:29.086 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:17:29.086 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:17:29.086 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:17:29.509 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:17:29.979 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:17:30.087 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:17:30.087 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:17:30.087 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:17:30.087 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:17:30.453 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:17:30.925 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:17:31.088 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:17:31.088 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:17:31.089 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:17:31.089 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:17:31.397 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:17:31.868 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:17:32.089 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:17:32.089 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:17:32.090 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:17:32.090 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:17:32.342 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:17:32.814 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:17:33.090 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:17:33.091 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:17:33.091 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:17:33.091 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:17:33.286 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:17:33.757 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:17:34.231 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:17:34.703 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:17:35.175 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:17:35.646 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:17:36.119 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:17:36.591 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:17:36.658 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:17:36.658 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:17:36.659 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:17:36.660 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:17:36.660 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:17:36.660 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:17:36.660 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:17:36.660 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:17:36.660 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:17:36.660 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:17:36.660 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:17:36.660 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:17:36.660 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:17:41.668 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:17:41.668 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:17:41.668 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:17:41.668 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:17:41.668 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:17:41.668 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:17:41.675 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:17:41.676 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:17:41.676 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:17:41.677 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:17:41.677 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:17:41.680 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:17:41.680 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:17:41.680 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:17:41.680 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:17:41.681 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:17:41.681 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:17:41.681 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:17:41.681 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:17:41.681 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:17:41.682 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:17:41.682 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:17:41.683 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:17:41.683 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:17:41.683 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:17:41.683 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:17:41.683 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:17:41.683 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:17:41.683 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:17:41.685 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:17:41.685 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:17:41.685 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:17:41.685 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:17:41.685 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:17:41.685 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:17:41.685 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:17:41.685 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:17:41.685 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:17:41.688 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:17:41.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:17:41.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:17:41.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:17:41.688 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:17:41.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:17:41.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:17:41.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:41.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:17:41.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:17:41.688 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:17:41.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:41.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:41.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:41.688 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:17:41.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:41.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:41.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:41.688 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:17:41.688 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:17:41.688 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:17:41.688 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:17:41.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:41.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:41.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:41.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:17:41.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:41.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:41.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:41.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:41.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:41.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:41.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:41.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:41.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:41.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:41.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:41.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:41.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:41.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:41.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:41.689 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:17:41.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:41.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:41.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:41.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:41.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:41.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:41.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:41.690 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:17:41.690 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:17:41.690 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:17:41.690 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:17:41.690 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:17:41.690 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:17:46.697 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:17:46.697 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:17:46.697 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:17:46.697 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:17:46.697 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:17:46.697 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:17:46.705 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:17:46.706 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:17:46.706 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:17:46.706 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:17:46.706 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:17:46.709 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:17:46.710 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:17:46.710 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:17:46.710 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:17:46.711 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:17:46.711 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:17:46.712 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:17:46.712 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:17:46.712 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:17:46.714 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:17:46.714 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:17:46.714 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:17:46.714 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:17:46.715 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:17:46.715 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:17:46.715 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:17:46.715 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:17:46.716 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:17:46.717 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:17:46.717 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:17:46.717 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:17:46.717 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:17:46.718 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:17:46.718 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:17:46.718 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:17:46.718 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:17:46.718 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:17:46.721 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:17:46.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:17:46.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:17:46.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:17:46.721 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:17:46.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:17:46.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:17:46.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:46.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:17:46.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:17:46.722 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:17:46.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:46.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:46.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:46.722 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:17:46.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:46.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:46.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:46.722 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:17:46.722 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:17:46.722 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:17:46.722 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:17:46.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:46.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:46.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:46.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:17:46.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:46.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:46.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:46.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:46.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:46.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:46.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:46.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:46.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:46.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:46.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:46.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:46.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:46.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:46.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:17:46.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:46.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:46.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:46.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:46.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:17:46.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:17:46.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:17:46.727 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:17:47.205 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:17:47.247 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:17:47.249 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:17:47.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:17:47.252 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:17:47.255 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:17:47.255 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:17:47.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:17:47.256 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:17:47.256 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:17:47.257 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:17:47.257 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:17:47.257 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:17:47.677 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:17:47.724 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:17:47.725 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:17:47.725 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:17:47.726 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:17:48.149 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:17:48.622 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:17:48.725 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:17:48.726 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:17:48.726 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:17:48.726 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:17:49.094 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:17:49.567 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:17:49.726 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:17:49.726 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:17:49.727 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:17:49.727 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:17:50.040 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:17:50.512 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:17:50.726 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:17:50.727 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:17:50.728 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:17:50.728 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:17:50.984 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:17:51.455 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:17:51.727 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:17:51.728 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:17:51.728 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:17:51.728 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:17:51.929 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:17:52.401 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:17:52.873 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:17:53.344 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:17:53.815 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:17:54.288 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:17:54.761 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:17:55.233 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:17:55.299 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:17:55.299 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:17:55.304 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:17:55.305 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:17:55.305 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:17:55.305 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:17:55.307 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:17:55.307 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:17:55.307 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:17:55.307 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:17:55.307 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:17:55.308 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:17:55.308 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:17:55.308 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1854 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:17:55.308 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1854 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:17:55.308 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1854 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:17:55.308 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1854 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:17:55.308 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1854 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:17:55.308 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1854 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:18:00.311 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:18:00.311 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:18:00.311 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:18:00.311 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:18:00.311 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:18:00.311 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:18:00.319 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:18:00.320 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:18:00.320 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:18:00.320 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:18:00.320 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:18:00.322 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:18:00.323 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:18:00.323 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:18:00.323 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:18:00.323 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:18:00.324 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:18:00.324 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:18:00.324 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:18:00.324 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:18:00.325 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:18:00.325 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:18:00.325 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:18:00.325 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:18:00.326 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:18:00.326 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:18:00.326 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:18:00.326 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:18:00.326 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:18:00.327 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:18:00.328 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:18:00.328 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:18:00.328 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:18:00.328 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:18:00.328 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:18:00.328 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:18:00.328 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:18:00.328 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:18:00.330 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:18:00.330 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:18:00.330 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:18:00.330 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:18:00.330 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:18:00.330 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:18:00.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:18:00.331 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:00.331 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:18:00.331 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:18:00.331 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:18:00.331 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:00.331 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:00.331 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:00.331 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:18:00.331 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:00.331 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:00.331 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:00.331 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:18:00.331 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:18:00.331 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:18:00.331 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:18:00.331 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:00.331 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:00.331 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:00.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:18:00.332 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:18:00.332 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:18:00.332 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:18:05.338 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:18:05.338 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:18:05.338 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:18:05.338 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:18:05.338 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:18:05.338 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:18:05.347 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:18:05.348 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:18:05.348 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:18:05.349 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:18:05.349 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:18:05.353 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:18:05.353 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:18:05.353 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:18:05.353 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:18:05.354 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:18:05.354 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:18:05.354 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:18:05.355 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:18:05.355 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:18:05.356 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:18:05.356 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:18:05.356 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:18:05.356 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:18:05.356 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:18:05.356 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:18:05.356 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:18:05.356 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:18:05.357 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:18:05.359 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:18:05.359 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:18:05.359 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:18:05.359 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:18:05.359 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:18:05.359 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:18:05.359 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:18:05.359 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:18:05.359 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:18:05.362 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:18:05.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:18:05.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:18:05.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:18:05.362 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:18:05.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:18:05.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:18:05.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:05.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:18:05.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:18:05.362 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:18:05.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:05.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:05.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:05.362 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:18:05.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:05.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:05.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:05.362 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:18:05.362 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:18:05.362 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:18:05.363 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:05.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:05.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:05.367 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:18:05.846 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:18:05.885 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:18:05.885 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:18:05.887 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:18:05.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:18:05.889 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:18:05.889 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:18:05.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:18:05.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:18:05.890 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:18:05.890 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:18:05.890 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:18:05.890 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:18:06.318 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:18:06.365 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:18:06.365 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:18:06.365 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:18:06.366 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:18:06.789 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:18:07.263 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:18:07.365 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:18:07.365 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:18:07.367 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:18:07.367 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:18:07.735 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:18:08.207 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:18:08.366 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:18:08.367 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:18:08.367 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:18:08.367 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:18:08.678 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:18:09.151 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:18:09.368 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:18:09.368 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:18:09.368 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:18:09.368 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:18:09.624 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:18:10.096 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:18:10.369 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:18:10.369 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:18:10.369 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:18:10.369 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:18:10.567 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:18:11.040 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:18:11.513 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:18:11.984 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:18:12.456 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:18:12.929 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:18:13.401 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:18:13.874 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:18:13.940 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:18:13.940 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:18:13.944 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:18:13.944 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:18:13.944 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:18:13.944 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:18:13.945 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:18:13.945 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:18:13.945 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:18:13.945 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:18:13.945 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:18:13.945 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:18:13.945 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:18:18.951 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:18:18.951 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:18:18.952 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:18:18.952 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:18:18.952 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:18:18.952 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:18:18.959 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:18:18.960 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:18:18.960 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:18:18.961 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:18:18.961 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:18:18.964 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:18:18.964 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:18:18.964 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:18:18.964 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:18:18.965 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:18:18.965 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:18:18.966 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:18:18.966 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:18:18.966 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:18:18.967 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:18:18.967 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:18:18.968 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:18:18.968 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:18:18.968 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:18:18.968 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:18:18.968 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:18:18.968 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:18:18.968 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:18:18.970 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:18:18.970 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:18:18.971 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:18:18.971 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:18:18.971 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:18:18.971 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:18:18.971 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:18:18.971 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:18:18.971 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:18:18.974 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:18:18.974 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:18:18.974 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:18:18.974 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:18:18.974 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:18:18.974 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:18:18.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:18:18.974 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:18.974 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:18:18.974 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:18:18.974 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:18:18.974 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:18.974 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:18.975 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:18.975 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:18:18.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:18.975 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:18.975 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:18.975 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:18:18.975 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:18:18.975 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:18:18.975 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:18:18.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:18.975 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:18.975 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:18.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:18:18.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:18.975 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:18.975 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:18.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:18.976 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:18.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:18.976 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:18.976 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:18.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:18.976 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:18.976 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:18.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:18.976 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:18.976 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:18.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:18.976 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:18.976 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:18:18.976 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:18.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:18.976 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:18.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:18.976 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:18.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:18.976 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:18:18.976 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:18:18.976 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:18:18.976 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:18:18.976 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:18:18.976 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:18:23.985 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:18:23.985 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:18:23.985 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:18:23.985 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:18:23.985 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:18:23.985 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:18:23.993 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:18:23.995 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:18:23.995 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:18:23.995 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:18:23.995 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:18:23.999 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:18:23.999 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:18:24.000 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:18:24.000 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:18:24.000 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:18:24.000 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:18:24.001 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:18:24.001 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:18:24.001 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:18:24.003 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:18:24.003 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:18:24.003 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:18:24.003 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:18:24.003 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:18:24.004 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:18:24.004 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:18:24.004 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:18:24.004 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:18:24.005 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:18:24.005 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:18:24.006 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:18:24.006 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:18:24.006 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:18:24.006 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:18:24.006 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:18:24.006 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:18:24.006 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:18:24.009 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:18:24.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:18:24.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:18:24.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:18:24.009 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:18:24.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:18:24.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:18:24.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:24.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:18:24.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:18:24.009 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:18:24.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:24.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:24.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:24.009 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:18:24.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:24.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:24.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:24.009 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:18:24.009 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:18:24.009 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:18:24.010 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:24.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:24.014 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:18:24.493 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:18:24.531 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:18:24.533 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:18:24.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:18:24.535 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:18:24.537 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:18:24.538 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:18:24.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:18:24.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:18:24.538 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:18:24.538 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:18:24.539 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:18:24.539 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:18:24.964 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:18:25.012 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:18:25.012 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:18:25.012 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:18:25.013 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:18:25.436 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:18:25.909 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:18:26.012 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:18:26.013 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:18:26.013 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:18:26.013 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:18:26.382 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:18:26.853 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:18:27.013 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:18:27.014 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:18:27.014 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:18:27.014 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:18:27.325 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:18:27.798 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:18:28.015 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:18:28.015 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:18:28.015 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:18:28.015 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:18:28.270 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:18:28.742 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:18:29.016 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:18:29.017 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:18:29.017 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:18:29.017 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:18:29.213 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:18:29.687 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:18:30.159 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:18:30.631 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:18:31.102 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:18:31.576 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:18:32.048 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:18:32.520 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:18:32.991 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:18:33.464 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:18:33.937 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:18:34.409 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:18:34.882 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:18:35.355 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:18:35.826 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:18:36.298 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:18:36.771 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:18:37.244 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:18:37.716 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:18:38.187 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:18:38.587 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:18:38.587 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:18:38.590 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:18:38.590 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:18:38.590 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:18:38.590 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:18:38.591 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:18:38.591 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:18:38.591 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:18:38.591 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:18:38.591 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:18:38.591 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:18:38.591 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:18:43.599 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:18:43.599 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:18:43.599 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:18:43.599 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:18:43.599 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:18:43.599 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:18:43.605 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:18:43.606 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:18:43.606 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:18:43.607 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:18:43.607 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:18:43.610 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:18:43.610 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:18:43.611 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:18:43.611 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:18:43.611 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:18:43.612 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:18:43.612 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:18:43.612 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:18:43.612 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:18:43.613 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:18:43.614 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:18:43.614 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:18:43.614 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:18:43.614 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:18:43.614 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:18:43.614 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:18:43.614 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:18:43.614 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:18:43.616 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:18:43.616 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:18:43.616 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:18:43.616 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:18:43.617 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:18:43.617 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:18:43.617 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:18:43.617 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:18:43.617 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:18:43.620 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:18:43.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:18:43.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:18:43.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:18:43.620 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:18:43.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:18:43.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:18:43.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:18:43.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:43.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:18:43.620 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:18:43.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:43.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:43.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:43.620 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:18:43.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:43.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:43.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:43.620 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:18:43.620 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:18:43.620 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:18:43.620 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:18:43.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:43.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:43.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:43.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:18:43.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:43.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:43.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:43.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:43.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:43.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:43.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:43.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:43.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:43.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:43.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:43.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:43.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:43.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:43.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:43.622 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:18:43.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:43.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:43.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:43.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:43.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:43.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:43.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:43.622 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:18:43.622 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:18:43.622 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:18:43.622 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:18:43.622 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:18:43.622 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:18:48.630 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:18:48.630 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:18:48.630 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:18:48.630 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:18:48.630 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:18:48.630 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:18:48.638 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:18:48.639 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:18:48.639 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:18:48.639 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:18:48.639 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:18:48.642 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:18:48.642 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:18:48.642 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:18:48.642 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:18:48.643 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:18:48.643 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:18:48.643 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:18:48.643 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:18:48.644 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:18:48.645 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:18:48.645 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:18:48.645 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:18:48.645 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:18:48.645 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:18:48.645 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:18:48.645 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:18:48.645 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:18:48.645 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:18:48.647 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:18:48.647 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:18:48.647 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:18:48.647 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:18:48.647 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:18:48.647 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:18:48.647 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:18:48.647 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:18:48.647 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:18:48.650 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:18:48.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:18:48.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:18:48.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:18:48.650 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:18:48.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:18:48.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:18:48.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:48.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:18:48.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:18:48.650 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:18:48.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:48.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:48.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:48.650 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:18:48.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:48.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:48.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:48.650 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:18:48.650 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:18:48.650 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:18:48.651 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:48.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:18:48.655 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:18:49.132 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:18:49.171 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:18:49.172 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:18:49.174 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:18:49.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:18:49.177 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:18:49.177 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:18:49.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:18:49.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:18:49.177 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:18:49.177 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:18:49.177 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:18:49.178 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:18:49.605 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:18:49.652 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:18:49.653 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:18:49.653 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:18:49.654 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:18:50.076 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:18:50.549 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:18:50.654 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:18:50.654 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:18:50.654 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:18:50.655 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:18:51.021 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:18:51.493 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:18:51.655 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:18:51.655 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:18:51.655 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:18:51.655 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:18:51.966 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:18:52.439 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:18:52.657 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:18:52.657 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:18:52.657 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:18:52.657 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:18:52.911 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:18:53.382 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:18:53.658 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:18:53.658 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:18:53.658 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:18:53.658 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:18:53.855 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:18:54.327 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:18:54.799 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:18:55.270 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:18:55.741 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:18:56.214 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:18:56.687 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:18:57.159 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:18:57.227 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:18:57.227 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:18:57.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:18:57.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:18:57.232 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:18:57.232 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:18:57.236 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:18:57.236 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:18:57.236 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:18:57.236 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:18:57.236 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:18:57.236 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:18:57.237 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:18:57.237 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:18:57.237 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:18:57.237 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:18:57.237 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:18:57.237 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:18:57.237 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:18:57.238 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1855 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:19:02.238 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:19:02.239 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:19:02.239 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:19:02.239 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:19:02.239 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:19:02.239 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:19:02.241 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:19:02.242 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:19:02.242 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:19:02.242 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:19:02.242 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:19:02.243 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:19:02.243 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:19:02.243 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:19:02.243 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:19:02.243 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:19:02.243 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:19:02.243 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:19:02.243 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:19:02.243 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:19:02.244 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:19:02.244 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:19:02.244 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:19:02.244 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:19:02.244 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:19:02.244 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:19:02.244 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:19:02.244 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:19:02.244 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:19:02.245 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:19:02.245 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:19:02.245 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:19:02.245 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:19:02.245 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:19:02.246 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:19:02.246 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:19:02.246 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:19:02.246 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:19:02.247 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:19:02.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:19:02.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:19:02.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:19:02.247 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:19:02.248 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:19:02.248 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:19:02.248 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:02.249 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:19:02.249 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:19:02.249 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:19:02.249 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:19:02.249 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:19:02.249 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:19:02.249 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:19:07.258 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:19:07.258 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:19:07.258 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:19:07.258 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:19:07.258 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:19:07.258 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:19:07.266 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:19:07.268 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:19:07.268 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:19:07.268 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:19:07.268 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:19:07.272 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:19:07.273 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:19:07.273 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:19:07.273 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:19:07.274 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:19:07.274 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:19:07.275 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:19:07.275 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:19:07.275 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:19:07.277 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:19:07.277 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:19:07.277 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:19:07.277 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:19:07.278 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:19:07.278 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:19:07.278 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:19:07.278 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:19:07.279 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:19:07.280 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:19:07.280 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:19:07.281 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:19:07.281 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:19:07.281 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:19:07.281 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:19:07.281 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:19:07.281 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:19:07.281 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:19:07.285 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:19:07.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:19:07.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:19:07.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:19:07.285 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:19:07.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:19:07.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:19:07.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:07.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:19:07.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:19:07.285 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:19:07.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:07.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:07.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:07.285 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:19:07.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:07.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:07.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:07.285 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:19:07.286 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:19:07.286 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:19:07.286 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:19:07.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:07.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:07.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:07.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:19:07.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:07.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:07.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:07.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:07.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:07.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:07.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:07.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:07.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:07.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:07.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:07.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:07.287 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:07.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:07.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:07.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:07.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:07.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:07.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:07.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:07.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:07.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:07.290 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:19:07.769 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:19:07.798 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:19:07.798 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:19:07.799 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:19:07.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:19:07.799 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:19:07.799 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:19:07.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:19:07.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:19:07.800 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:19:07.800 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:19:07.800 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:19:07.800 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:19:08.241 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:19:08.288 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:19:08.288 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:19:08.288 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:19:08.289 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:19:08.713 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:19:09.186 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:19:09.289 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:19:09.289 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:19:09.290 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:19:09.290 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:19:09.658 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:19:10.130 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:19:10.290 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:19:10.290 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:19:10.291 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:19:10.291 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:19:10.601 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:19:11.075 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:19:11.291 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:19:11.292 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:19:11.292 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:19:11.292 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:19:11.547 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:19:12.020 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:19:12.292 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:19:12.292 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:19:12.293 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:19:12.293 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:19:12.493 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:19:12.965 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:19:13.437 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:19:13.908 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:19:14.382 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:19:14.854 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:19:15.326 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:19:15.800 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:19:16.272 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:19:16.744 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:19:17.215 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:19:17.686 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:19:17.819 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:19:17.820 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:19:17.822 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:19:17.822 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:19:17.822 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:19:17.822 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:19:17.823 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:19:17.823 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:19:17.823 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:19:17.823 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:19:17.823 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:19:17.823 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:19:17.823 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:19:17.823 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2276 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:19:17.823 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2276 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:19:17.823 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2276 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:19:17.823 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2276 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:19:17.823 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2276 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:19:17.823 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2276 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:19:22.829 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:19:22.830 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:19:22.830 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:19:22.830 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:19:22.830 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:19:22.830 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:19:22.839 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:19:22.840 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:19:22.841 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:19:22.841 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:19:22.841 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:19:22.845 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:19:22.846 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:19:22.846 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:19:22.846 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:19:22.847 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:19:22.847 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:19:22.848 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:19:22.848 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:19:22.848 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:19:22.849 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:19:22.850 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:19:22.850 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:19:22.850 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:19:22.850 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:19:22.850 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:19:22.851 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:19:22.851 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:19:22.851 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:19:22.852 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:19:22.853 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:19:22.853 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:19:22.853 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:19:22.853 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:19:22.853 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:19:22.853 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:19:22.853 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:19:22.853 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:19:22.856 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:19:22.856 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:19:22.856 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:19:22.856 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:19:22.856 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:19:22.856 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:19:22.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:19:22.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:22.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:19:22.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:19:22.857 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:19:22.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:22.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:22.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:22.857 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:19:22.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:22.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:22.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:22.857 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:19:22.857 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:19:22.857 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:19:22.857 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:19:22.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:22.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:22.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:22.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:19:22.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:22.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:22.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:22.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:22.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:22.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:22.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:22.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:22.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:22.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:22.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:22.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:22.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:22.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:22.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:22.859 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:19:22.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:22.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:22.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:22.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:22.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:22.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:22.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:22.859 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:19:22.859 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:19:22.859 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:19:22.859 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:19:22.859 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:19:22.859 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:19:27.867 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:19:27.867 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:19:27.867 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:19:27.867 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:19:27.867 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:19:27.867 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:19:27.875 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:19:27.876 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:19:27.876 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:19:27.876 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:19:27.876 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:19:27.879 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:19:27.879 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:19:27.880 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:19:27.880 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:19:27.880 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:19:27.880 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:19:27.881 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:19:27.881 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:19:27.881 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:19:27.882 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:19:27.882 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:19:27.882 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:19:27.882 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:19:27.883 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:19:27.883 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:19:27.883 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:19:27.883 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:19:27.883 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:19:27.884 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:19:27.885 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:19:27.885 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:19:27.885 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:19:27.885 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:19:27.885 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:19:27.885 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:19:27.885 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:19:27.885 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:19:27.887 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:19:27.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:19:27.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:19:27.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:19:27.888 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:19:27.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:19:27.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:19:27.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:27.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:19:27.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:19:27.888 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:19:27.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:27.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:27.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:27.888 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:19:27.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:27.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:27.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:27.888 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:19:27.888 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:19:27.888 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:19:27.888 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:19:27.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:27.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:27.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:27.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:19:27.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:27.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:27.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:27.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:27.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:27.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:27.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:27.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:27.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:27.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:27.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:27.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:27.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:27.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:27.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:27.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:27.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:27.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:27.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:27.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:27.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:27.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:27.893 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:19:28.370 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:19:28.415 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:19:28.417 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:19:28.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:19:28.419 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:19:28.422 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:19:28.423 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:19:28.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:19:28.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:19:28.424 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:19:28.425 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:19:28.425 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:19:28.426 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:19:28.842 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:19:28.891 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:19:28.891 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:19:28.892 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:19:28.892 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:19:29.313 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:19:29.784 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:19:29.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:19:29.893 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:19:29.893 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:19:29.893 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:19:30.257 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:19:30.730 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:19:30.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:19:30.894 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:19:30.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:19:30.894 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:19:31.202 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:19:31.673 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:19:31.894 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:19:31.895 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:19:31.895 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:19:31.895 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:19:32.144 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:19:32.616 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:19:32.895 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:19:32.895 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:19:32.896 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:19:32.896 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:19:33.085 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:19:33.556 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:19:34.030 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:19:34.502 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:19:34.974 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:19:35.445 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:19:35.919 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:19:36.391 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:19:36.863 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:19:37.334 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:19:37.805 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:19:38.278 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:19:38.750 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:19:39.222 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:19:39.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:19:39.466 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:19:39.472 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:19:39.472 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:19:39.472 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:19:39.472 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:19:39.476 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:19:39.477 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:19:39.477 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:19:39.477 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:19:39.477 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:19:39.477 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:19:39.477 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:19:39.477 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2505 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:19:39.477 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2505 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:19:39.477 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2505 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:19:39.477 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2505 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:19:39.477 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2505 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:19:39.477 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2505 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:19:44.478 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:19:44.478 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:19:44.478 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:19:44.478 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:19:44.478 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:19:44.478 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:19:44.486 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:19:44.486 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:19:44.486 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:19:44.486 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:19:44.486 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:19:44.490 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:19:44.490 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:19:44.490 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:19:44.491 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:19:44.491 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:19:44.491 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:19:44.491 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:19:44.491 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:19:44.491 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:19:44.495 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:19:44.495 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:19:44.495 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:19:44.495 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:19:44.495 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:19:44.495 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:19:44.496 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:19:44.496 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:19:44.496 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:19:44.499 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:19:44.499 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:19:44.499 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:19:44.499 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:19:44.499 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:19:44.499 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:19:44.499 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:19:44.499 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:19:44.499 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:19:44.503 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:19:44.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:19:44.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:19:44.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:19:44.503 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:19:44.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:19:44.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:19:44.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:44.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:19:44.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:19:44.504 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:19:44.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:44.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:44.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:44.504 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:19:44.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:44.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:44.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:44.504 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:19:44.504 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:19:44.504 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:19:44.504 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:19:44.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:44.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:44.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:44.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:19:44.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:44.505 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:44.505 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:44.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:44.505 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:44.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:44.506 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:44.506 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:44.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:44.506 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:44.506 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:44.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:44.506 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:44.506 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:44.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:44.506 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:19:44.506 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:44.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:44.506 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:44.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:44.506 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:44.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:44.506 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:44.506 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:19:44.506 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:19:44.506 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:19:44.506 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:19:44.506 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:19:44.506 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:19:49.514 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:19:49.514 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:19:49.514 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:19:49.514 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:19:49.514 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:19:49.514 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:19:49.522 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:19:49.524 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:19:49.524 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:19:49.525 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:19:49.525 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:19:49.530 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:19:49.531 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:19:49.531 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:19:49.531 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:19:49.531 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:19:49.531 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:19:49.531 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:19:49.531 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:19:49.532 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:19:49.535 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:19:49.535 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:19:49.536 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:19:49.536 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:19:49.536 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:19:49.536 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:19:49.536 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:19:49.536 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:19:49.536 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:19:49.539 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:19:49.539 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:19:49.539 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:19:49.539 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:19:49.540 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:19:49.540 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:19:49.540 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:19:49.540 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:19:49.540 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:19:49.544 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:19:49.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:19:49.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:19:49.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:19:49.544 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:19:49.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:19:49.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:19:49.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:49.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:19:49.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:19:49.544 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:19:49.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:49.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:49.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:49.544 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:19:49.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:49.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:49.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:49.544 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:19:49.545 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:19:49.545 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:19:49.545 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:19:49.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:49.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:49.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:49.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:19:49.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:49.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:49.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:49.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:49.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:49.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:49.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:49.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:49.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:49.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:49.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:49.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:49.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:49.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:49.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:19:49.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:49.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:49.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:49.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:19:49.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:49.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:19:49.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:19:49.549 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:19:50.027 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:19:50.070 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:19:50.072 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:19:50.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:19:50.075 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:19:50.078 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:19:50.078 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:19:50.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:19:50.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:19:50.079 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:19:50.079 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:19:50.079 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:19:50.079 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:19:50.499 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:19:50.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:19:50.548 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:19:50.548 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:19:50.549 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:19:50.971 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:19:51.444 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:19:51.549 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:19:51.549 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:19:51.549 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:19:51.550 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:19:51.916 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:19:52.388 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:19:52.550 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:19:52.550 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:19:52.550 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:19:52.550 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:19:52.859 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:19:53.333 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:19:53.550 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:19:53.551 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:19:53.551 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:19:53.551 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:19:53.805 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:19:54.278 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:19:54.551 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:19:54.552 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:19:54.552 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:19:54.552 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:19:54.751 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:19:55.224 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:19:55.696 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:19:56.169 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:19:56.642 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:19:57.114 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:19:57.587 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:19:58.060 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:19:58.532 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:19:59.005 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:19:59.478 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:19:59.950 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:20:00.421 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:20:00.894 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:20:01.367 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:20:01.839 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:20:02.310 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:20:02.783 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:20:03.256 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:20:03.727 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:20:04.199 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:20:04.672 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:20:05.144 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:20:05.616 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:20:06.087 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:20:06.561 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:20:07.033 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:20:07.505 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:20:07.976 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:20:08.450 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:20:08.922 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:20:09.394 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:20:09.865 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:20:10.128 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:20:10.128 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:20:10.129 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:20:10.129 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:20:10.129 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:20:10.129 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:20:10.130 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:20:10.130 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:20:10.130 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:20:10.130 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:20:10.130 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:20:10.130 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:20:10.130 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:20:15.138 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:20:15.138 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:20:15.138 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:20:15.138 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:20:15.138 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:20:15.138 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:20:15.143 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:20:15.145 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:20:15.145 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:20:15.146 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:20:15.146 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:20:15.151 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:20:15.151 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:20:15.152 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:20:15.152 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:20:15.152 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:20:15.153 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:20:15.153 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:20:15.153 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:20:15.154 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:20:15.156 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:20:15.157 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:20:15.157 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:20:15.157 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:20:15.158 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:20:15.158 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:20:15.159 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:20:15.159 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:20:15.159 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:20:15.161 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:20:15.161 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:20:15.162 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:20:15.162 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:20:15.162 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:20:15.162 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:20:15.162 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:20:15.162 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:20:15.163 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:20:15.167 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:20:15.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:20:15.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:20:15.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:20:15.168 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:20:15.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:20:15.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:20:15.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:20:15.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:15.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:20:15.168 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:20:15.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:15.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:15.168 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:20:15.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:15.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:15.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:15.168 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:20:15.168 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:20:15.168 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:20:15.169 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:20:15.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:15.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:15.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:15.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:20:15.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:15.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:15.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:15.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:15.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:15.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:15.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:15.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:15.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:15.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:15.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:15.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:15.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:15.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:15.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:15.171 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:20:15.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:15.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:15.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:15.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:15.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:15.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:15.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:15.171 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:20:15.171 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:20:15.171 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:20:15.171 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:20:15.171 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:20:15.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:20.183 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:20:20.183 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:20:20.183 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:20:20.183 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:20:20.183 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:20:20.183 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:20:20.191 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:20:20.192 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:20:20.192 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:20:20.193 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:20:20.193 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:20:20.195 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:20:20.195 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:20:20.195 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:20:20.195 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:20:20.195 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:20:20.196 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:20:20.196 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:20:20.196 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:20:20.196 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:20:20.197 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:20:20.197 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:20:20.197 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:20:20.197 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:20:20.197 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:20:20.197 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:20:20.197 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:20:20.197 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:20:20.198 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:20:20.199 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:20:20.199 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:20:20.199 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:20:20.199 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:20:20.199 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:20:20.199 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:20:20.199 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:20:20.199 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:20:20.199 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:20:20.201 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:20:20.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:20:20.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:20:20.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:20:20.201 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:20:20.202 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:20:20.202 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:20:20.202 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:20.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:20.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:20.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:20.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:20.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:20.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:20.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:20.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:20.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:20.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:20.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:20.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:20.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:20.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:20.207 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:20:20.683 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:20:20.719 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:20:20.720 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:20:20.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:20:20.722 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:20:21.147 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:20:21.204 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:20:21.205 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:20:21.205 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:20:21.205 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:20:21.617 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:20:22.090 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:20:22.206 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:20:22.207 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:20:22.207 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:20:22.207 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:20:22.563 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:20:23.035 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:20:23.208 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:20:23.208 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:20:23.208 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:20:23.208 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:20:23.508 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:20:23.981 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:20:24.209 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:20:24.210 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:20:24.210 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:20:24.210 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:20:24.453 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:20:24.928 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:20:25.211 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:20:25.211 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:20:25.211 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:20:25.211 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:20:25.400 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:20:25.874 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:20:26.346 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:20:26.818 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:20:27.293 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:20:27.765 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:20:28.241 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:20:28.713 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:20:29.188 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:20:29.660 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:20:30.133 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:20:30.606 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:20:30.733 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:20:30.733 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:20:30.734 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:20:30.734 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:20:30.735 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:20:30.735 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:20:30.735 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:20:30.735 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:20:30.735 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:20:30.735 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:20:30.735 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:20:30.735 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2273 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:20:30.735 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2273 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:20:35.741 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:20:35.741 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:20:35.741 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:20:35.741 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:20:35.741 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:20:35.741 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:20:35.747 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:20:35.749 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:20:35.749 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:20:35.749 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:20:35.749 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:20:35.753 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:20:35.754 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:20:35.754 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:20:35.754 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:20:35.754 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:20:35.754 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:20:35.754 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:20:35.754 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:20:35.755 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:20:35.757 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:20:35.757 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:20:35.757 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:20:35.757 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:20:35.758 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:20:35.758 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:20:35.758 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:20:35.758 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:20:35.758 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:20:35.760 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:20:35.760 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:20:35.761 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:20:35.761 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:20:35.761 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:20:35.761 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:20:35.761 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:20:35.761 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:20:35.761 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:20:35.764 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:20:35.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:20:35.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:20:35.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:20:35.764 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:20:35.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:20:35.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:20:35.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:35.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:20:35.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:20:35.764 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:20:35.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:35.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:35.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:35.764 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:20:35.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:35.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:35.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:35.764 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:20:35.764 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:20:35.764 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:20:35.764 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:20:35.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:35.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:35.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:35.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:20:35.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:35.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:35.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:35.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:35.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:35.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:35.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:35.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:35.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:35.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:35.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:35.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:35.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:35.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:35.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:35.766 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:20:35.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:35.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:35.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:35.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:35.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:35.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:35.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:35.766 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:20:35.766 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:20:35.766 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:20:35.766 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:20:35.766 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:20:35.766 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:20:40.775 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:20:40.775 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:20:40.775 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:20:40.775 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:20:40.775 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:20:40.775 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:20:40.783 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:20:40.784 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:20:40.784 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:20:40.785 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:20:40.785 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:20:40.788 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:20:40.788 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:20:40.788 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:20:40.789 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:20:40.789 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:20:40.789 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:20:40.789 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:20:40.789 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:20:40.789 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:20:40.792 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:20:40.792 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:20:40.793 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:20:40.793 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:20:40.793 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:20:40.793 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:20:40.794 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:20:40.794 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:20:40.794 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:20:40.795 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:20:40.795 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:20:40.795 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:20:40.795 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:20:40.795 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:20:40.795 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:20:40.796 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:20:40.796 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:20:40.796 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:20:40.799 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:20:40.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:20:40.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:20:40.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:20:40.799 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:20:40.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:20:40.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:20:40.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:40.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:20:40.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:20:40.800 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:20:40.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:40.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:40.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:40.800 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:20:40.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:40.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:40.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:40.800 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:20:40.800 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:20:40.800 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:20:40.800 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:20:40.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:40.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:40.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:40.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:20:40.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:40.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:40.801 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:40.801 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:40.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:40.801 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:40.801 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:40.801 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:40.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:40.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:40.801 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:40.801 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:40.801 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:40.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:40.801 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:40.801 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:40.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:40.801 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:40.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:40.801 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:40.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:40.801 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:40.805 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:20:41.281 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:20:41.328 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:20:41.331 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:20:41.333 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:20:41.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:20:41.751 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:20:41.803 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:20:41.804 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:20:41.804 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:20:41.804 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:20:42.218 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:20:42.681 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:20:42.805 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:20:42.805 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:20:42.805 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:20:42.806 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:20:43.145 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:20:43.608 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:20:43.807 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:20:43.807 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:20:43.807 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:20:43.807 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:20:44.080 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:20:44.551 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:20:44.808 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:20:44.808 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:20:44.808 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:20:44.808 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:20:45.020 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:20:45.491 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:20:45.809 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:20:45.810 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:20:45.810 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:20:45.810 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:20:45.963 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:20:46.438 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:20:46.904 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:20:47.376 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:20:47.847 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:20:48.317 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:20:48.781 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:20:49.251 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:20:49.725 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:20:50.194 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:20:50.657 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:20:51.120 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:20:51.584 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:20:52.047 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:20:52.519 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:20:52.988 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:20:53.348 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:20:53.348 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:20:53.349 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:20:53.349 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:20:53.350 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:20:53.350 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:20:53.350 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:20:53.350 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:20:53.351 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:20:53.351 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:20:53.351 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:20:53.351 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2733 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:20:53.351 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2733 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:20:53.351 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2733 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:20:53.351 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2733 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:20:53.351 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2733 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:20:53.351 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2733 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:20:58.360 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:20:58.360 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:20:58.360 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:20:58.360 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:20:58.360 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:20:58.360 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:20:58.367 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:20:58.367 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:20:58.367 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:20:58.367 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:20:58.367 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:20:58.369 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:20:58.369 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:20:58.369 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:20:58.369 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:20:58.369 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:20:58.369 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:20:58.369 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:20:58.369 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:20:58.369 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:20:58.371 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:20:58.371 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:20:58.371 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:20:58.371 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:20:58.371 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:20:58.371 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:20:58.371 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:20:58.371 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:20:58.371 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:20:58.373 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:20:58.373 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:20:58.373 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:20:58.373 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:20:58.373 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:20:58.373 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:20:58.373 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:20:58.373 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:20:58.373 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:20:58.375 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:20:58.376 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:20:58.376 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:20:58.376 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:58.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:58.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:58.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:58.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:58.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:58.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:58.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:58.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:58.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:58.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:58.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:20:58.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:58.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:58.377 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:20:58.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:58.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:58.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:58.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:58.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:20:58.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:20:58.378 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:20:58.378 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:20:58.378 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:20:58.378 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:20:58.378 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:20:58.378 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:20:58.378 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:21:03.385 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:21:03.385 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:21:03.385 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:21:03.385 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:21:03.385 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:21:03.385 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:21:03.392 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:21:03.393 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:21:03.393 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:03.394 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:21:03.394 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:21:03.398 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:21:03.398 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:21:03.399 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:21:03.399 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:03.399 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:21:03.400 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:21:03.400 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:21:03.401 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:21:03.401 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:03.402 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:21:03.403 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:21:03.403 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:21:03.403 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:03.403 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:21:03.404 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:21:03.404 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:21:03.404 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:21:03.404 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:03.406 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:21:03.406 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:21:03.406 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:21:03.406 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:03.406 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:21:03.406 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:21:03.406 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:21:03.406 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:21:03.406 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:03.410 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:21:03.410 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:21:03.410 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:21:03.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:21:03.410 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:21:03.410 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:21:03.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:21:03.410 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:03.410 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:21:03.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:21:03.410 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:21:03.410 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:03.410 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:03.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:03.411 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:03.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:03.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:03.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:03.411 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:21:03.411 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:21:03.411 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:21:03.411 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:21:03.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:03.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:03.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:03.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:21:03.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:03.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:03.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:03.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:03.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:03.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:03.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:03.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:03.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:03.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:03.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:03.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:03.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:03.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:03.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:03.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:03.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:03.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:03.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:03.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:03.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:03.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:03.416 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:21:03.893 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:21:03.940 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:21:03.942 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:21:03.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:21:03.944 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:21:03.948 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:21:03.948 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:21:03.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:21:03.949 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:21:03.949 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:21:03.949 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:21:03.949 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:21:03.949 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:21:03.983 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:21:03.983 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:21:03.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:21:03.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:21:04.365 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:21:04.414 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:04.414 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:04.414 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:04.414 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:04.836 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:21:05.309 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:21:05.415 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:05.416 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:05.416 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:05.416 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:05.782 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:21:06.254 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:21:06.416 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:06.417 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:06.417 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:06.417 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:06.725 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:21:07.198 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:21:07.417 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:07.417 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:07.417 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:07.418 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:07.670 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:21:08.142 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:21:08.418 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:08.418 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:08.419 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:08.419 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:08.613 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:21:09.084 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:21:09.555 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:21:10.028 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:21:10.501 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:21:10.973 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:21:11.444 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:21:11.917 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:21:11.988 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:21:11.988 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:21:11.988 [WARNING] transceiver.py:257 (MS@172.18.59.22:6700) RX TRXD message (fn=1854 tn=3 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:21:11.994 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:11.994 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:11.994 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:11.994 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:11.998 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:21:11.998 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:21:11.999 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:21:11.999 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:21:11.999 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:21:11.999 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:21:11.999 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:21:11.999 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1856 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:21:12.000 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1856 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:21:12.000 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1856 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:21:12.000 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1856 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:21:12.000 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1856 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:21:12.000 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1856 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:21:17.001 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:21:17.001 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:21:17.001 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:21:17.001 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:21:17.001 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:21:17.001 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:21:17.011 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:21:17.011 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:21:17.012 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:17.012 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:21:17.012 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:21:17.014 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:21:17.014 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:21:17.014 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:21:17.014 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:17.014 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:21:17.014 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:21:17.014 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:21:17.014 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:21:17.015 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:17.015 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:21:17.016 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:21:17.016 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:21:17.016 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:17.016 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:21:17.016 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:21:17.016 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:21:17.016 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:21:17.016 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:17.017 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:21:17.017 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:21:17.017 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:21:17.017 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:17.017 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:21:17.017 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:21:17.017 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:21:17.017 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:21:17.017 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:17.019 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:21:17.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:21:17.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:21:17.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:21:17.019 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:21:17.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:21:17.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:21:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:21:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:21:17.020 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:21:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:17.020 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:17.020 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:21:17.020 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:21:17.020 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:21:17.020 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:21:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:17.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:21:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:17.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:17.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:17.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:17.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:17.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:17.021 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:21:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:17.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:17.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:17.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:17.021 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:21:17.021 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:21:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:17.021 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:21:17.021 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:21:17.021 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:21:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:22.028 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:21:22.028 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:21:22.028 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:21:22.028 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:21:22.028 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:21:22.028 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:21:22.039 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:21:22.040 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:21:22.040 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:22.040 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:21:22.040 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:21:22.042 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:21:22.042 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:21:22.042 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:21:22.042 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:22.043 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:21:22.043 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:21:22.043 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:21:22.043 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:21:22.043 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:22.044 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:21:22.044 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:21:22.044 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:21:22.044 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:22.044 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:21:22.044 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:21:22.044 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:21:22.044 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:21:22.044 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:22.045 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:21:22.046 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:21:22.046 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:21:22.046 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:22.046 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:21:22.046 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:21:22.046 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:21:22.046 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:21:22.046 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:21:22.048 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:21:22.048 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:21:22.048 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:22.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:22.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:22.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:22.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:22.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:22.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:22.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:22.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:22.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:22.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:22.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:22.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:22.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:22.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:22.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:22.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:22.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:22.053 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:21:22.529 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:21:22.573 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:21:22.575 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:21:22.578 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:21:22.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:21:22.581 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:21:22.581 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:21:22.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:21:22.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:21:22.582 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:21:22.583 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:21:22.583 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:21:22.583 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:21:22.620 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:21:22.620 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:21:22.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:21:22.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:21:23.002 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:21:23.051 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:23.051 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:23.051 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:23.051 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:23.473 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:21:23.946 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:21:24.052 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:24.052 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:24.052 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:24.053 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:24.418 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:21:24.890 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:21:25.054 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:25.054 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:25.054 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:25.054 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:25.361 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:21:25.834 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:21:26.055 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:26.055 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:26.055 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:26.055 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:26.307 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:21:26.779 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:21:27.056 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:27.056 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:27.056 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:27.057 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:27.250 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:21:27.720 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:21:28.191 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:21:28.665 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:21:29.137 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:21:29.609 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:21:30.080 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:21:30.553 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:21:30.624 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:21:30.624 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:21:30.629 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:30.630 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:30.630 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:30.630 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:30.633 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:21:30.634 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:21:30.634 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:21:30.634 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:21:30.634 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:21:30.634 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:21:30.634 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:21:30.635 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1856 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:21:30.635 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1856 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:21:30.635 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1856 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:21:30.635 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1856 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:21:30.635 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1856 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:21:30.635 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1856 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:21:35.638 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:21:35.638 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:21:35.638 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:21:35.638 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:21:35.638 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:21:35.638 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:21:35.646 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:21:35.648 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:21:35.648 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:35.648 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:21:35.648 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:21:35.653 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:21:35.654 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:21:35.654 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:21:35.654 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:35.654 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:21:35.655 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:21:35.655 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:21:35.655 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:21:35.656 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:35.657 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:21:35.657 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:21:35.657 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:21:35.657 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:35.658 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:21:35.658 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:21:35.658 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:21:35.658 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:21:35.658 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:35.660 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:21:35.660 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:21:35.661 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:21:35.661 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:35.661 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:21:35.661 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:21:35.661 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:21:35.661 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:21:35.661 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:35.666 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:21:35.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:21:35.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:21:35.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:21:35.666 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:21:35.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:21:35.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:21:35.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:35.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:21:35.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:21:35.667 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:21:35.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:35.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:35.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:35.667 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:35.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:35.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:35.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:35.667 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:21:35.667 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:21:35.667 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:21:35.667 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:21:35.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:35.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:35.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:35.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:21:35.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:35.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:35.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:35.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:35.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:35.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:35.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:35.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:35.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:35.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:35.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:35.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:35.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:35.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:35.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:35.670 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:21:35.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:35.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:35.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:35.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:35.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:35.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:35.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:35.670 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:21:35.670 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:21:35.670 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:21:35.670 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:21:35.671 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:21:35.671 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:21:40.677 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:21:40.677 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:21:40.677 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:21:40.677 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:21:40.677 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:21:40.677 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:21:40.685 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:21:40.686 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:21:40.686 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:40.687 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:21:40.687 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:21:40.690 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:21:40.691 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:21:40.691 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:21:40.692 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:40.692 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:21:40.692 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:21:40.693 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:21:40.693 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:21:40.693 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:40.695 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:21:40.695 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:21:40.696 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:21:40.696 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:40.696 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:21:40.696 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:21:40.697 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:21:40.697 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:21:40.697 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:40.698 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:21:40.698 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:21:40.699 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:21:40.699 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:40.699 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:21:40.699 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:21:40.699 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:21:40.699 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:21:40.699 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:40.702 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:21:40.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:21:40.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:21:40.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:21:40.702 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:21:40.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:21:40.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:21:40.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:40.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:21:40.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:21:40.703 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:21:40.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:40.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:40.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:40.703 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:40.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:40.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:40.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:40.703 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:21:40.703 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:21:40.703 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:21:40.703 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:21:40.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:40.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:40.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:40.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:21:40.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:40.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:40.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:40.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:40.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:40.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:40.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:40.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:40.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:40.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:40.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:40.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:40.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:40.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:40.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:40.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:40.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:40.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:40.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:40.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:40.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:40.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:40.708 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:21:41.187 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:21:41.226 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:21:41.229 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:21:41.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:21:41.230 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:21:41.233 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:21:41.233 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:21:41.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:21:41.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:21:41.235 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:21:41.235 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:21:41.235 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:21:41.235 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:21:41.277 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:21:41.277 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:21:41.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:21:41.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:21:41.659 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:21:41.705 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:41.706 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:41.706 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:41.706 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:42.130 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:21:42.603 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:21:42.706 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:42.707 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:42.707 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:42.707 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:43.075 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:21:43.547 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:21:43.707 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:43.708 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:43.708 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:43.708 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:44.018 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:21:44.492 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:21:44.708 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:44.709 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:44.709 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:44.709 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:44.964 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:21:45.436 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:21:45.710 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:45.710 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:45.710 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:45.710 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:45.907 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:21:46.380 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:21:46.852 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:21:47.324 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:21:47.795 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:21:48.269 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:21:48.741 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:21:49.213 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:21:49.281 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:21:49.281 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:21:49.284 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:49.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:49.284 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:49.284 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:49.285 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:21:49.285 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:21:49.285 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:21:49.285 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:21:49.285 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:21:49.285 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:21:49.285 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:21:54.293 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:21:54.303 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:21:54.303 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:21:54.304 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:21:54.304 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:21:54.304 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:21:54.307 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:21:54.308 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:21:54.309 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:54.309 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:21:54.309 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:21:54.313 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:21:54.313 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:21:54.314 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:21:54.314 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:54.314 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:21:54.314 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:21:54.315 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:21:54.315 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:21:54.315 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:54.316 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:21:54.316 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:21:54.316 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:21:54.316 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:54.316 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:21:54.316 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:21:54.316 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:21:54.316 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:21:54.316 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:54.318 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:21:54.318 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:21:54.318 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:21:54.318 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:54.318 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:21:54.318 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:21:54.318 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:21:54.318 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:21:54.318 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:54.320 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:21:54.321 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:21:54.321 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:21:54.321 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:54.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:54.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:54.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:54.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:54.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:54.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:54.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:54.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:54.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:54.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:54.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:54.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:54.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:54.322 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:21:54.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:54.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:54.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:54.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:54.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:54.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:54.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:54.322 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:21:54.322 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:21:54.322 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:21:54.322 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:21:54.322 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:21:54.322 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:21:59.330 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:21:59.330 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:21:59.330 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:21:59.330 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:21:59.330 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:21:59.330 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:21:59.337 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:21:59.338 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:21:59.338 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:59.339 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:21:59.339 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:21:59.342 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:21:59.343 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:21:59.343 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:21:59.343 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:59.343 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:21:59.344 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:21:59.344 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:21:59.344 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:21:59.345 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:21:59.346 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:21:59.346 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:21:59.346 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:21:59.346 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:59.347 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:21:59.347 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:21:59.347 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:21:59.347 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:21:59.347 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:21:59.349 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:21:59.349 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:21:59.349 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:21:59.349 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:21:59.349 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:21:59.349 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:21:59.349 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:21:59.349 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:21:59.350 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:21:59.353 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:21:59.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:21:59.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:21:59.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:21:59.353 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:21:59.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:21:59.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:21:59.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:59.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:21:59.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:21:59.353 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:21:59.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:59.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:59.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:59.353 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:21:59.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:59.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:59.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:59.353 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:21:59.353 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:21:59.353 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:21:59.353 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:21:59.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:59.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:59.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:59.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:21:59.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:59.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:59.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:59.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:59.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:59.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:59.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:59.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:59.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:59.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:59.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:59.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:59.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:59.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:21:59.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:59.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:59.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:59.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:59.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:21:59.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:59.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:21:59.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:21:59.358 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:21:59.835 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:21:59.874 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:21:59.875 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:21:59.876 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:21:59.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:21:59.878 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:21:59.878 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:21:59.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:21:59.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:21:59.879 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:21:59.879 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:21:59.879 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:21:59.879 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:21:59.924 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:21:59.925 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:21:59.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:21:59.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:22:00.302 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:22:00.356 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:22:00.356 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:22:00.357 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:22:00.357 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:22:00.774 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:22:01.247 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:22:01.358 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:22:01.358 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:22:01.358 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:22:01.358 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:22:01.720 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:22:02.192 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:22:02.358 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:22:02.359 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:22:02.359 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:22:02.359 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:22:02.663 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:22:03.136 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:22:03.359 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:22:03.359 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:22:03.360 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:22:03.360 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:22:03.608 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:22:04.080 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:22:04.360 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:22:04.360 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:22:04.360 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:22:04.361 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:22:04.551 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:22:05.025 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:22:05.497 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:22:05.969 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:22:06.440 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:22:06.914 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:22:07.386 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:22:07.858 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:22:07.930 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:22:07.930 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:22:07.936 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:22:07.936 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:22:07.936 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:22:07.936 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:22:07.938 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:22:07.938 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:22:07.938 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:22:07.938 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:22:07.938 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:22:07.938 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:22:07.938 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:22:12.942 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:22:12.942 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:22:12.942 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:22:12.942 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:22:12.942 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:22:12.942 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:22:12.945 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:22:12.945 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:22:12.945 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:22:12.945 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:22:12.946 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:22:12.946 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:22:12.946 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:22:12.947 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:22:12.947 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:22:12.947 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:22:12.947 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:22:12.947 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:22:12.947 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:22:12.947 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:22:12.948 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:22:12.948 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:22:12.948 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:22:12.948 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:22:12.948 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:22:12.948 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:22:12.948 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:22:12.948 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:22:12.948 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:22:12.949 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:22:12.949 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:22:12.949 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:22:12.949 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:22:12.949 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:22:12.949 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:22:12.949 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:22:12.949 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:22:12.949 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:22:12.951 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:22:12.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:22:12.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:22:12.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:22:12.951 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:22:12.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:22:12.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:22:12.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:12.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:22:12.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:22:12.951 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:22:12.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:12.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:12.951 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:22:12.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:12.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:12.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:12.951 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:22:12.951 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:22:12.951 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:22:12.951 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:12.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:12.953 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:22:12.953 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:22:12.953 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:22:12.953 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:22:12.953 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:22:12.953 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:22:12.953 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:22:17.962 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:22:17.962 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:22:17.962 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:22:17.962 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:22:17.962 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:22:17.962 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:22:17.967 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:22:17.969 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:22:17.969 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:22:17.970 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:22:17.970 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:22:17.974 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:22:17.974 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:22:17.975 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:22:17.975 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:22:17.975 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:22:17.976 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:22:17.976 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:22:17.976 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:22:17.977 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:22:17.978 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:22:17.978 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:22:17.979 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:22:17.979 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:22:17.979 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:22:17.979 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:22:17.979 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:22:17.979 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:22:17.980 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:22:17.982 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:22:17.982 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:22:17.982 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:22:17.982 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:22:17.983 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:22:17.983 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:22:17.983 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:22:17.983 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:22:17.983 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:22:17.987 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:22:17.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:22:17.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:22:17.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:22:17.987 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:22:17.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:22:17.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:22:17.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:22:17.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:17.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:22:17.987 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:22:17.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:17.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:17.987 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:22:17.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:17.987 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:22:17.987 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:22:17.987 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:22:17.987 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:22:17.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:17.988 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:17.988 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:17.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:22:17.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:17.988 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:17.988 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:17.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:17.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:17.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:17.988 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:17.988 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:17.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:17.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:17.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:17.988 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:17.988 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:17.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:17.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:17.988 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:17.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:17.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:17.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:17.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:17.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:17.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:17.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:17.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:17.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:17.992 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:22:18.471 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:22:18.514 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:22:18.516 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:22:18.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:22:18.517 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:22:18.519 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:22:18.519 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:22:18.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:22:18.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:22:18.521 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:22:18.521 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:22:18.521 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:22:18.521 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:22:18.562 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:22:18.562 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:22:18.562 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:22:18.562 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:22:18.943 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:22:18.992 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:22:18.992 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:22:18.992 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:22:18.992 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:22:19.415 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:22:19.888 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:22:19.992 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:22:19.993 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:22:19.993 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:22:19.993 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:22:20.360 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:22:20.832 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:22:20.993 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:22:20.994 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:22:20.994 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:22:20.994 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:22:21.303 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:22:21.776 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:22:21.994 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:22:21.995 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:22:21.995 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:22:21.995 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:22:22.249 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:22:22.721 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:22:22.995 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:22:23.013 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:22:23.013 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:22:23.013 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:22:23.192 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:22:23.665 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:22:24.138 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:22:24.610 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:22:25.081 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:22:25.554 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:22:26.026 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:22:26.498 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:22:26.969 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:22:27.443 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:22:27.915 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:22:28.387 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:22:28.858 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:22:29.331 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:22:29.803 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:22:30.275 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:22:30.746 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:22:31.220 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:22:31.692 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:22:32.164 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:22:32.570 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:22:32.570 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:22:32.576 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:22:32.576 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:22:32.576 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:22:32.576 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:22:32.580 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:22:32.580 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:22:32.580 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:22:32.580 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:22:32.580 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:22:32.580 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:22:32.581 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:22:32.581 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3151 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:22:32.581 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3152 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:22:32.581 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3152 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:22:32.581 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3152 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:22:32.581 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3152 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:22:32.581 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3152 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:22:32.582 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3152 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:22:32.582 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3152 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:22:32.582 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3152 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:22:37.584 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:22:37.584 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:22:37.584 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:22:37.584 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:22:37.584 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:22:37.584 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:22:37.591 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:22:37.592 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:22:37.592 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:22:37.592 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:22:37.592 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:22:37.594 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:22:37.594 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:22:37.595 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:22:37.595 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:22:37.595 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:22:37.595 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:22:37.596 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:22:37.596 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:22:37.596 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:22:37.597 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:22:37.597 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:22:37.597 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:22:37.597 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:22:37.597 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:22:37.597 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:22:37.597 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:22:37.597 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:22:37.598 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:22:37.599 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:22:37.599 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:22:37.599 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:22:37.599 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:22:37.599 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:22:37.599 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:22:37.599 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:22:37.599 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:22:37.599 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:22:37.602 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:22:37.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:22:37.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:22:37.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:22:37.602 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:22:37.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:22:37.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:22:37.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:37.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:22:37.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:22:37.602 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:22:37.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:37.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:37.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:37.602 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:22:37.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:37.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:37.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:37.602 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:22:37.602 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:22:37.602 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:22:37.602 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:22:37.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:37.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:37.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:37.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:22:37.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:37.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:37.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:37.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:37.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:37.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:37.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:37.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:37.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:37.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:37.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:37.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:37.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:37.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:37.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:37.603 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:22:37.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:37.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:37.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:37.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:37.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:37.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:37.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:37.604 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:22:37.604 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:22:37.604 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:22:37.604 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:22:37.604 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:22:37.604 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:22:42.610 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:22:42.610 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:22:42.610 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:22:42.610 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:22:42.610 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:22:42.610 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:22:42.617 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:22:42.618 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:22:42.618 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:22:42.618 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:22:42.618 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:22:42.621 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:22:42.621 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:22:42.621 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:22:42.621 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:22:42.621 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:22:42.622 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:22:42.622 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:22:42.622 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:22:42.622 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:22:42.623 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:22:42.623 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:22:42.623 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:22:42.623 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:22:42.623 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:22:42.624 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:22:42.624 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:22:42.624 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:22:42.624 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:22:42.625 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:22:42.626 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:22:42.626 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:22:42.626 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:22:42.626 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:22:42.626 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:22:42.626 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:22:42.626 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:22:42.626 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:22:42.628 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:22:42.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:22:42.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:22:42.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:22:42.628 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:22:42.629 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:22:42.629 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:22:42.629 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:42.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:42.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:42.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:42.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:42.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:42.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:42.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:42.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:42.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:42.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:42.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:42.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:42.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:42.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:42.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:42.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:42.634 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:22:43.113 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:22:43.155 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:22:43.157 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:22:43.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:22:43.159 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:22:43.163 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:22:43.163 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:22:43.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:22:43.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:22:43.165 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:22:43.165 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:22:43.165 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:22:43.165 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:22:43.203 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:22:43.204 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:22:43.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:22:43.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:22:43.586 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:22:43.631 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:22:43.632 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:22:43.632 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:22:43.632 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:22:44.057 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:22:44.530 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:22:44.632 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:22:44.633 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:22:44.633 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:22:44.633 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:22:45.002 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:22:45.474 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:22:45.633 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:22:45.633 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:22:45.634 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:22:45.634 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:22:45.945 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:22:46.419 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:22:46.634 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:22:46.634 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:22:46.635 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:22:46.635 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:22:46.891 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:22:47.363 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:22:47.635 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:22:47.635 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:22:47.636 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:22:47.636 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:22:47.834 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:22:48.307 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:22:48.780 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:22:49.251 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:22:49.723 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:22:50.196 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:22:50.669 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:22:51.140 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:22:51.208 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:22:51.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:22:51.210 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:22:51.210 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:22:51.210 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:22:51.210 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:22:51.211 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:22:51.211 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:22:51.211 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:22:51.211 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:22:51.211 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:22:51.211 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:22:51.211 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:22:56.219 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:22:56.219 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:22:56.219 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:22:56.219 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:22:56.219 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:22:56.219 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:22:56.227 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:22:56.228 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:22:56.228 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:22:56.228 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:22:56.228 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:22:56.230 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:22:56.230 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:22:56.231 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:22:56.231 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:22:56.231 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:22:56.231 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:22:56.231 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:22:56.231 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:22:56.231 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:22:56.232 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:22:56.232 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:22:56.232 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:22:56.232 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:22:56.232 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:22:56.232 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:22:56.233 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:22:56.233 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:22:56.233 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:22:56.234 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:22:56.234 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:22:56.234 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:22:56.234 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:22:56.234 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:22:56.234 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:22:56.234 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:22:56.234 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:22:56.234 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:22:56.236 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:22:56.236 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:22:56.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:22:56.236 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:22:56.236 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:22:56.236 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:22:56.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:22:56.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:22:56.236 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:56.236 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:22:56.236 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:22:56.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:56.236 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:56.236 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:22:56.236 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:56.236 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:56.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:56.236 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:22:56.236 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:22:56.236 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:22:56.236 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:22:56.236 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:56.236 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:56.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:56.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:22:56.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:56.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:56.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:56.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:56.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:56.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:56.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:56.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:56.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:56.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:56.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:56.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:22:56.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:56.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:56.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:56.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:56.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:56.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:56.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:56.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:22:56.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:22:56.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:56.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:22:56.238 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:22:56.238 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:22:56.238 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:22:56.238 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:22:56.238 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:22:56.238 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:22:56.238 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:23:01.245 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:23:01.245 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:23:01.245 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:23:01.245 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:23:01.245 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:23:01.245 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:23:01.253 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:23:01.254 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:23:01.254 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:23:01.255 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:23:01.255 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:23:01.258 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:23:01.259 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:23:01.259 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:23:01.259 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:23:01.260 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:23:01.260 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:23:01.261 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:23:01.261 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:23:01.261 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:23:01.262 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:23:01.263 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:23:01.263 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:23:01.263 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:23:01.263 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:23:01.263 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:23:01.263 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:23:01.263 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:23:01.263 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:23:01.266 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:23:01.266 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:23:01.266 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:23:01.266 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:23:01.266 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:23:01.266 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:23:01.267 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:23:01.267 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:23:01.267 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:23:01.270 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:23:01.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:23:01.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:23:01.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:23:01.270 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:23:01.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:23:01.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:23:01.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:01.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:23:01.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:23:01.270 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:23:01.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:01.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:01.271 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:01.271 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:23:01.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:01.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:01.271 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:01.271 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:23:01.271 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:23:01.271 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:23:01.271 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:23:01.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:01.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:01.271 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:01.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:23:01.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:01.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:01.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:01.271 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:01.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:01.272 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:01.272 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:01.272 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:01.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:01.272 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:01.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:01.272 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:01.272 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:01.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:01.272 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:01.272 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:01.272 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:01.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:01.272 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:01.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:01.272 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:01.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:01.276 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:23:01.755 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:23:01.802 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:23:01.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:23:01.806 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:23:01.809 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:23:01.813 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:23:01.813 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:23:01.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:23:01.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:23:01.815 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:23:01.815 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:23:01.816 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:23:01.816 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:23:02.227 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:23:02.275 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:23:02.275 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:23:02.275 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:23:02.275 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:23:02.698 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:23:03.169 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:23:03.275 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:23:03.276 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:23:03.276 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:23:03.276 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:23:03.642 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:23:04.115 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:23:04.277 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:23:04.277 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:23:04.277 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:23:04.277 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:23:04.587 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:23:05.058 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:23:05.278 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:23:05.278 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:23:05.279 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:23:05.279 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:23:05.531 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:23:06.004 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:23:06.279 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:23:06.279 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:23:06.279 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:23:06.279 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:23:06.475 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:23:06.947 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:23:07.420 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:23:07.892 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:23:08.364 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:23:08.835 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:23:09.309 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:23:09.781 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:23:10.253 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:23:10.724 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:23:11.198 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:23:11.670 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:23:11.853 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:23:11.853 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:23:11.859 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:23:11.859 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:23:11.859 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:23:11.859 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:23:11.861 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:23:11.861 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:23:11.861 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:23:11.861 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:23:11.861 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:23:11.861 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:23:11.861 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:23:11.861 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2287 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:23:11.861 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2287 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:23:11.861 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2287 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:23:11.861 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2287 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:23:11.861 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2287 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:23:11.861 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2287 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:23:16.866 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:23:16.867 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:23:16.867 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:23:16.867 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:23:16.867 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:23:16.867 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:23:16.871 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:23:16.872 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:23:16.872 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:23:16.873 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:23:16.873 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:23:16.876 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:23:16.876 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:23:16.876 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:23:16.876 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:23:16.876 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:23:16.876 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:23:16.876 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:23:16.877 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:23:16.877 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:23:16.880 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:23:16.880 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:23:16.880 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:23:16.880 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:23:16.881 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:23:16.881 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:23:16.881 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:23:16.881 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:23:16.881 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:23:16.884 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:23:16.884 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:23:16.885 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:23:16.885 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:23:16.885 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:23:16.885 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:23:16.885 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:23:16.885 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:23:16.885 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:23:16.890 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:23:16.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:23:16.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:23:16.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:23:16.890 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:23:16.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:23:16.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:23:16.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:16.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:23:16.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:23:16.891 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:23:16.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:16.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:16.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:16.891 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:23:16.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:16.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:16.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:16.891 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:23:16.891 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:23:16.891 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:23:16.891 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:23:16.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:16.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:16.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:16.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:23:16.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:16.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:16.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:16.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:16.893 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:16.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:16.893 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:16.893 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:16.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:16.893 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:16.893 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:16.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:16.894 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:16.894 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:16.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:16.894 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:23:16.894 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:16.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:16.894 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:16.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:16.894 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:16.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:16.894 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:16.894 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:23:16.894 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:23:16.894 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:23:16.894 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:23:16.894 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:23:16.894 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:23:21.901 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:23:21.902 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:23:21.902 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:23:21.902 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:23:21.902 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:23:21.902 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:23:21.912 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:23:21.913 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:23:21.913 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:23:21.914 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:23:21.914 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:23:21.918 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:23:21.919 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:23:21.919 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:23:21.919 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:23:21.920 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:23:21.920 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:23:21.920 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:23:21.921 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:23:21.921 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:23:21.923 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:23:21.923 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:23:21.923 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:23:21.923 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:23:21.924 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:23:21.924 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:23:21.924 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:23:21.924 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:23:21.924 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:23:21.927 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:23:21.927 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:23:21.928 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:23:21.928 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:23:21.928 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:23:21.928 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:23:21.928 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:23:21.928 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:23:21.928 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:23:21.933 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:23:21.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:23:21.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:23:21.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:23:21.933 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:23:21.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:23:21.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:23:21.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:23:21.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:21.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:23:21.934 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:23:21.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:21.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:21.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:21.934 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:23:21.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:21.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:21.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:21.934 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:23:21.934 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:23:21.934 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:23:21.934 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:23:21.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:21.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:21.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:21.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:23:21.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:21.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:21.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:21.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:21.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:21.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:21.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:21.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:21.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:21.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:21.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:21.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:21.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:21.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:21.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:21.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:21.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:21.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:21.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:21.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:21.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:21.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:21.939 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:23:22.414 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:23:22.465 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:23:22.466 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:23:22.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:23:22.467 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:23:22.468 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:23:22.468 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:23:22.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:23:22.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:23:22.469 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:23:22.469 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:23:22.469 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:23:22.469 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:23:22.504 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:23:22.504 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:23:22.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:23:22.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:23:22.885 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:23:22.938 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:23:22.939 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:23:22.939 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:23:22.940 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:23:23.357 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:23:23.829 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:23:23.939 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:23:23.940 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:23:23.940 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:23:23.942 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:23:24.300 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:23:24.773 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:23:24.941 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:23:24.941 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:23:24.941 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:23:24.943 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:23:25.245 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:23:25.718 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:23:25.942 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:23:25.942 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:23:25.942 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:23:25.944 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:23:26.191 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:23:26.663 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:23:26.943 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:23:26.944 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:23:26.944 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:23:26.945 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:23:27.135 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:23:27.607 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:23:28.080 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:23:28.552 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:23:29.025 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:23:29.498 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:23:29.970 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:23:30.442 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:23:30.913 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:23:31.387 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:23:31.859 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:23:32.331 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:23:32.802 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:23:33.275 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:23:33.509 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:23:33.509 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:23:33.515 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:23:33.515 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:23:33.515 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:23:33.515 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:23:33.517 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:23:33.517 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:23:33.517 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:23:33.517 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:23:33.518 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:23:33.518 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:23:33.518 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:23:33.518 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2502 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:23:33.518 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2502 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:23:33.518 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2502 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:23:33.518 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2502 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:23:33.518 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2502 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:23:33.518 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2503 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:23:33.518 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2503 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:23:33.518 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2503 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:23:33.518 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2503 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:23:33.518 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2503 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:23:33.518 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2503 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:23:33.518 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2503 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:23:33.518 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2503 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:23:38.522 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:23:38.522 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:23:38.522 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:23:38.522 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:23:38.522 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:23:38.522 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:23:38.536 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:23:38.538 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:23:38.538 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:23:38.539 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:23:38.539 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:23:38.543 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:23:38.543 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:23:38.543 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:23:38.543 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:23:38.544 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:23:38.544 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:23:38.544 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:23:38.544 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:23:38.545 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:23:38.547 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:23:38.548 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:23:38.548 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:23:38.548 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:23:38.549 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:23:38.549 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:23:38.549 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:23:38.550 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:23:38.550 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:23:38.551 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:23:38.552 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:23:38.552 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:23:38.552 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:23:38.552 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:23:38.552 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:23:38.552 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:23:38.552 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:23:38.552 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:23:38.557 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:23:38.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:23:38.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:23:38.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:23:38.557 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:23:38.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:23:38.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:23:38.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:38.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:23:38.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:23:38.558 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:23:38.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:38.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:38.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:38.558 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:23:38.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:38.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:38.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:38.558 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:23:38.558 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:23:38.558 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:23:38.558 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:23:38.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:38.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:38.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:38.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:23:38.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:38.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:38.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:38.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:38.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:38.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:38.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:38.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:38.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:38.561 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:38.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:38.561 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:38.561 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:38.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:38.561 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:23:38.561 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:38.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:38.561 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:38.561 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:38.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:38.561 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:38.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:38.561 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:23:38.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:38.561 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:23:38.561 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:23:38.561 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:23:38.561 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:23:38.561 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:23:43.568 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:23:43.568 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:23:43.568 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:23:43.568 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:23:43.568 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:23:43.568 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:23:43.576 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:23:43.577 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:23:43.577 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:23:43.577 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:23:43.577 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:23:43.581 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:23:43.581 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:23:43.581 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:23:43.581 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:23:43.581 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:23:43.582 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:23:43.582 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:23:43.582 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:23:43.582 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:23:43.584 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:23:43.584 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:23:43.584 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:23:43.584 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:23:43.585 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:23:43.585 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:23:43.585 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:23:43.585 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:23:43.585 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:23:43.587 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:23:43.587 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:23:43.587 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:23:43.587 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:23:43.587 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:23:43.587 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:23:43.587 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:23:43.587 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:23:43.587 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:23:43.590 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:23:43.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:23:43.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:23:43.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:23:43.590 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:23:43.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:23:43.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:23:43.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:43.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:23:43.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:23:43.591 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:23:43.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:43.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:43.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:43.591 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:23:43.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:43.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:43.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:43.591 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:23:43.591 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:23:43.591 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:23:43.591 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:23:43.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:43.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:43.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:43.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:23:43.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:43.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:43.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:43.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:43.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:43.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:43.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:43.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:43.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:43.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:43.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:43.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:43.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:43.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:43.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:43.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:43.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:43.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:43.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:43.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:43.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:43.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:43.596 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:23:44.075 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:23:44.119 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:23:44.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:23:44.122 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:23:44.125 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:23:44.546 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:23:44.594 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:23:44.594 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:23:44.594 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:23:44.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:23:45.020 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:23:45.493 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:23:45.595 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:23:45.596 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:23:45.596 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:23:45.596 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:23:45.965 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:23:46.440 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:23:46.597 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:23:46.598 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:23:46.598 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:23:46.598 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:23:46.912 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:23:47.387 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:23:47.599 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:23:47.599 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:23:47.599 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:23:47.599 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:23:47.859 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:23:48.335 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:23:48.600 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:23:48.610 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:23:48.610 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:23:48.610 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:23:48.807 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:23:49.282 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:23:49.754 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:23:50.229 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:23:50.701 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:23:51.175 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:23:51.647 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:23:52.119 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:23:52.593 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:23:53.065 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:23:53.537 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:23:54.013 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:23:54.136 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:23:54.136 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:23:54.136 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:23:54.136 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:23:54.137 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:23:54.137 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:23:54.137 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:23:54.137 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:23:54.137 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:23:54.137 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:23:54.137 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:23:59.143 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:23:59.143 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:23:59.144 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:23:59.144 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:23:59.144 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:23:59.144 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:23:59.151 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:23:59.152 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:23:59.152 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:23:59.152 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:23:59.153 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:23:59.157 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:23:59.157 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:23:59.157 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:23:59.158 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:23:59.158 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:23:59.158 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:23:59.158 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:23:59.158 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:23:59.158 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:23:59.162 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:23:59.162 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:23:59.162 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:23:59.162 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:23:59.163 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:23:59.163 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:23:59.163 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:23:59.163 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:23:59.163 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:23:59.166 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:23:59.167 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:23:59.167 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:23:59.167 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:23:59.167 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:23:59.167 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:23:59.167 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:23:59.167 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:23:59.167 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:23:59.172 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:23:59.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:23:59.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:23:59.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:23:59.173 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:23:59.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:23:59.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:23:59.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:59.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:23:59.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:23:59.173 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:23:59.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:59.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:59.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:59.173 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:23:59.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:59.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:59.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:59.174 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:23:59.174 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:23:59.174 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:23:59.174 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:23:59.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:59.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:59.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:59.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:23:59.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:59.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:59.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:59.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:59.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:59.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:59.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:59.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:59.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:59.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:59.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:59.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:23:59.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:59.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:59.176 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:23:59.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:59.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:59.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:59.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:23:59.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:59.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:23:59.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:59.176 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:23:59.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:23:59.176 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:23:59.176 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:23:59.176 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:23:59.176 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:23:59.176 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:24:04.184 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:24:04.184 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:24:04.184 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:24:04.204 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:24:04.204 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:24:04.204 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:24:04.208 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:24:04.211 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:24:04.211 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:24:04.212 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:24:04.212 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:24:04.219 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:24:04.220 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:24:04.220 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:24:04.221 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:24:04.221 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:24:04.222 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:24:04.222 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:24:04.222 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:24:04.223 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:24:04.226 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:24:04.226 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:24:04.227 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:24:04.227 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:24:04.228 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:24:04.228 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:24:04.229 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:24:04.229 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:24:04.229 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:24:04.231 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:24:04.231 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:24:04.232 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:24:04.232 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:24:04.232 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:24:04.232 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:24:04.233 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:24:04.233 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:24:04.233 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:24:04.237 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:24:04.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:24:04.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:24:04.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:24:04.237 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:24:04.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:24:04.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:24:04.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:04.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:24:04.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:24:04.237 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:24:04.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:04.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:04.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:04.237 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:24:04.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:04.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:04.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:04.237 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:24:04.237 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:24:04.237 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:24:04.238 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:24:04.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:04.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:04.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:04.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:24:04.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:04.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:04.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:04.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:04.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:04.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:04.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:04.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:04.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:04.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:04.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:04.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:04.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:04.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:04.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:04.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:04.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:04.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:04.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:04.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:04.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:04.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:04.242 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:24:04.721 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:24:04.768 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:24:04.769 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:24:04.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:24:04.771 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:24:05.192 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:24:05.242 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:24:05.242 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:24:05.242 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:24:05.243 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:24:05.663 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:24:06.137 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:24:06.244 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:24:06.244 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:24:06.244 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:24:06.244 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:24:06.609 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:24:07.081 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:24:07.245 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:24:07.245 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:24:07.245 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:24:07.246 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:24:07.555 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:24:08.027 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:24:08.247 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:24:08.247 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:24:08.247 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:24:08.247 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:24:08.499 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:24:08.975 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:24:09.248 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:24:09.248 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:24:09.249 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:24:09.249 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:24:09.448 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:24:09.921 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:24:10.393 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:24:10.865 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:24:11.338 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:24:11.811 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:24:12.282 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:24:12.753 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:24:13.227 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:24:13.700 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:24:14.171 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:24:14.647 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:24:15.119 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:24:15.594 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:24:16.066 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:24:16.541 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:24:16.785 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:24:16.785 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:24:16.785 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:24:16.785 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:24:16.786 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:24:16.786 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:24:16.786 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:24:16.786 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:24:16.786 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:24:16.786 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:24:16.786 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:24:16.786 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2707 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:24:16.786 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2707 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:24:16.786 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2707 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:24:16.786 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2707 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:24:16.786 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2707 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:24:16.786 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2707 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:24:16.786 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2707 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:24:16.786 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2707 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:24:21.792 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:24:21.792 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:24:21.792 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:24:21.792 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:24:21.792 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:24:21.792 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:24:21.799 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:24:21.800 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:24:21.800 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:24:21.800 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:24:21.800 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:24:21.803 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:24:21.803 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:24:21.803 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:24:21.803 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:24:21.804 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:24:21.804 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:24:21.804 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:24:21.804 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:24:21.805 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:24:21.806 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:24:21.806 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:24:21.806 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:24:21.806 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:24:21.806 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:24:21.807 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:24:21.807 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:24:21.807 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:24:21.807 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:24:21.809 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:24:21.809 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:24:21.809 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:24:21.809 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:24:21.809 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:24:21.810 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:24:21.810 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:24:21.810 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:24:21.810 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:24:21.813 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:24:21.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:24:21.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:24:21.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:24:21.813 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:24:21.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:24:21.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:24:21.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:21.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:24:21.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:24:21.813 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:24:21.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:21.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:21.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:21.814 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:24:21.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:21.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:21.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:21.814 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:24:21.814 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:24:21.814 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:24:21.814 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:24:21.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:21.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:21.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:21.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:24:21.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:21.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:21.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:21.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:21.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:21.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:21.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:21.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:21.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:21.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:21.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:21.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:21.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:21.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:21.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:21.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:21.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:21.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:21.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:21.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:21.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:21.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:21.818 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:24:22.297 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:24:22.338 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:24:22.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:24:22.339 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:24:22.340 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:24:22.341 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:24:22.341 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:24:22.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:24:22.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:24:22.341 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:24:22.341 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:24:22.342 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:24:22.342 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:24:22.769 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:24:22.816 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:24:22.817 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:24:22.817 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:24:22.817 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:24:23.241 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:24:23.714 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:24:23.817 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:24:23.817 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:24:23.818 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:24:23.818 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:24:24.186 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:24:24.658 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:24:24.817 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:24:24.818 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:24:24.818 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:24:24.818 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:24:25.129 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:24:25.603 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:24:25.818 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:24:25.819 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:24:25.819 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:24:25.819 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:24:26.075 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:24:26.547 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:24:26.819 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:24:26.820 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:24:26.820 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:24:26.820 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:24:27.018 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:24:27.489 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:24:27.959 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:24:28.430 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:24:28.904 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:24:29.376 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:24:29.848 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:24:30.321 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:24:30.794 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:24:31.266 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:24:31.737 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:24:32.210 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:24:32.682 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:24:33.154 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:24:33.393 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:24:33.393 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:24:33.398 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:24:33.398 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:24:33.399 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:24:33.399 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:24:33.403 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:24:33.404 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:24:33.404 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:24:33.404 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:24:33.404 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:24:33.404 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:24:33.404 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:24:33.405 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2503 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:24:33.405 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2504 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:24:33.405 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2504 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:24:33.405 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2504 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:24:33.405 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2504 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:24:33.405 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2504 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:24:33.406 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2504 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:24:33.406 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2504 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:24:33.406 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2504 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:24:38.406 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:24:38.406 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:24:38.406 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:24:38.406 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:24:38.406 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:24:38.406 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:24:38.415 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:24:38.416 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:24:38.417 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:24:38.417 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:24:38.417 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:24:38.421 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:24:38.421 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:24:38.422 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:24:38.422 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:24:38.422 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:24:38.423 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:24:38.423 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:24:38.423 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:24:38.423 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:24:38.425 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:24:38.425 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:24:38.425 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:24:38.425 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:24:38.425 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:24:38.426 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:24:38.426 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:24:38.426 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:24:38.426 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:24:38.427 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:24:38.427 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:24:38.427 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:24:38.428 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:24:38.428 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:24:38.428 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:24:38.428 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:24:38.428 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:24:38.428 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:24:38.431 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:24:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:24:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:24:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:24:38.431 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:24:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:24:38.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:24:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:24:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:24:38.431 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:24:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:38.431 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:24:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:38.431 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:24:38.431 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:24:38.431 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:24:38.431 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:24:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:38.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:38.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:24:38.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:38.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:38.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:38.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:38.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:38.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:38.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:38.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:38.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:38.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:38.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:38.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:38.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:38.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:38.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:38.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:38.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:38.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:38.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:38.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:38.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:38.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:38.436 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:24:38.912 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:24:38.957 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:24:38.959 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:24:38.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:24:38.960 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:24:38.961 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:24:38.961 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:24:38.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:24:38.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:24:38.961 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:24:38.961 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:24:38.961 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:24:38.961 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:24:39.384 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:24:39.434 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:24:39.435 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:24:39.435 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:24:39.435 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:24:39.855 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:24:40.329 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:24:40.436 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:24:40.436 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:24:40.436 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:24:40.436 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:24:40.801 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:24:41.273 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:24:41.437 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:24:41.438 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:24:41.438 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:24:41.438 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:24:41.744 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:24:42.218 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:24:42.439 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:24:42.439 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:24:42.439 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:24:42.439 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:24:42.690 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:24:43.162 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:24:43.440 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:24:43.441 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:24:43.441 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:24:43.441 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:24:43.633 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:24:44.106 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:24:44.578 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:24:45.050 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:24:45.523 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:24:45.996 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:24:46.468 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:24:46.939 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:24:47.412 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:24:47.884 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:24:48.356 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:24:48.827 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:24:49.298 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:24:49.771 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:24:50.244 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:24:50.716 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:24:51.187 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:24:51.660 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:24:52.132 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:24:52.605 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:24:53.075 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:24:53.549 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:24:54.007 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:24:54.007 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:24:54.009 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:24:54.009 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:24:54.009 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:24:54.009 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:24:54.010 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:24:54.010 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:24:54.010 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:24:54.010 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:24:54.010 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:24:54.010 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:24:54.010 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:24:59.018 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:24:59.018 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:24:59.018 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:24:59.018 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:24:59.018 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:24:59.018 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:24:59.026 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:24:59.027 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:24:59.027 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:24:59.028 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:24:59.028 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:24:59.031 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:24:59.032 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:24:59.032 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:24:59.032 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:24:59.032 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:24:59.032 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:24:59.032 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:24:59.033 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:24:59.033 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:24:59.037 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:24:59.037 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:24:59.037 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:24:59.037 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:24:59.037 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:24:59.037 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:24:59.038 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:24:59.038 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:24:59.038 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:24:59.041 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:24:59.041 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:24:59.042 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:24:59.042 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:24:59.042 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:24:59.042 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:24:59.042 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:24:59.042 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:24:59.042 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:24:59.048 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:24:59.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:24:59.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:24:59.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:24:59.048 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:24:59.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:24:59.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:24:59.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:59.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:24:59.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:24:59.048 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:24:59.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:59.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:59.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:59.049 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:24:59.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:59.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:59.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:59.049 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:24:59.049 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:24:59.049 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:24:59.049 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:24:59.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:59.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:59.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:59.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:24:59.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:59.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:59.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:59.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:59.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:59.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:59.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:59.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:59.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:59.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:59.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:59.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:24:59.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:59.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:59.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:59.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:24:59.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:59.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:59.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:59.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:24:59.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:59.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:24:59.054 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:24:59.531 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:24:59.577 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:24:59.578 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:24:59.579 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:24:59.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:24:59.584 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:24:59.584 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:24:59.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:24:59.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:24:59.586 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:24:59.586 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:24:59.587 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:24:59.587 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:24:59.627 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:24:59.627 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:24:59.632 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:24:59.632 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:24:59.632 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:24:59.632 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:24:59.635 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:24:59.636 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:24:59.636 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:24:59.636 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:24:59.636 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:24:59.637 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:24:59.637 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:24:59.637 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=126 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:24:59.637 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:24:59.637 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:24:59.637 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:24:59.637 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:24:59.637 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:25:04.639 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:25:04.639 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:25:04.639 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:25:04.639 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:25:04.639 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:25:04.639 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:25:04.642 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:25:04.642 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:25:04.642 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:25:04.642 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:25:04.642 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:25:04.643 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:25:04.643 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:25:04.643 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:25:04.643 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:25:04.643 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:25:04.643 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:25:04.643 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:25:04.643 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:25:04.643 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:25:04.644 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:25:04.644 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:25:04.644 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:25:04.644 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:25:04.644 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:25:04.644 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:25:04.644 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:25:04.644 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:25:04.644 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:25:04.646 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:25:04.646 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:25:04.646 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:25:04.646 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:25:04.646 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:25:04.646 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:25:04.646 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:25:04.646 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:25:04.646 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:25:04.648 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:25:04.648 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:25:04.648 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:25:04.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:25:04.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:25:04.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:25:04.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:25:04.653 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:25:05.130 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:25:05.171 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:25:05.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:05.175 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:25:05.177 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:25:05.197 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:05.197 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:05.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:25:05.220 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:05.220 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:05.220 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:25:05.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:05.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:05.228 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:25:05.228 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:25:05.228 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:25:05.228 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:25:05.268 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:25:05.268 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:25:05.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:05.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:05.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:05.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:05.392 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:05.392 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:05.410 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:05.410 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:05.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:25:05.417 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:05.417 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:05.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:25:05.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:05.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:05.418 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:25:05.418 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:25:05.418 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:25:05.418 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:25:05.457 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:25:05.457 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:25:05.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:05.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:05.601 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:25:05.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:05.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:05.651 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:05.651 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:05.652 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:25:05.652 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:25:05.652 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:25:05.652 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:25:05.670 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:05.670 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:05.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:25:05.675 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:05.675 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:05.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:25:05.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:05.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:05.677 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:25:05.677 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:25:05.677 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:25:05.677 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:25:05.690 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:25:05.690 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:25:05.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:05.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:05.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:05.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:05.996 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:05.996 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:06.012 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:06.012 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:06.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:25:06.017 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:06.017 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:06.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:25:06.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:06.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:06.019 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:25:06.019 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:25:06.019 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:25:06.019 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:25:06.071 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:25:06.071 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:25:06.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:06.072 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:25:06.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:06.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:06.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:06.394 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:06.395 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:06.404 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:25:06.404 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:25:06.404 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:25:06.405 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:25:06.406 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:25:06.406 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:25:06.406 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:25:06.406 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:25:06.406 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:25:06.406 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:25:06.406 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:25:11.410 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:25:11.410 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:25:11.410 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:25:11.410 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:25:11.410 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:25:11.410 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:25:11.420 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:25:11.422 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:25:11.422 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:25:11.423 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:25:11.423 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:25:11.428 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:25:11.428 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:25:11.428 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:25:11.428 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:25:11.429 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:25:11.429 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:25:11.429 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:25:11.429 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:25:11.429 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:25:11.433 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:25:11.433 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:25:11.433 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:25:11.433 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:25:11.433 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:25:11.434 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:25:11.434 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:25:11.434 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:25:11.434 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:25:11.437 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:25:11.437 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:25:11.437 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:25:11.437 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:25:11.438 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:25:11.438 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:25:11.438 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:25:11.438 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:25:11.438 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:25:11.443 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:25:11.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:25:11.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:25:11.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:25:11.443 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:25:11.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:25:11.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:25:11.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:25:11.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:25:11.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:25:11.444 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:25:11.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:25:11.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:25:11.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:25:11.444 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:25:11.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:25:11.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:25:11.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:25:11.444 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:25:11.444 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:25:11.444 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:25:11.444 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:25:11.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:25:11.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:25:11.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:25:11.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:25:11.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:25:11.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:25:11.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:25:11.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:25:11.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:25:11.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:25:11.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:25:11.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:25:11.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:25:11.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:25:11.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:25:11.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:25:11.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:25:11.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:25:11.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:25:11.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:25:11.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:25:11.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:25:11.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:25:11.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:25:11.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:25:11.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:25:11.449 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:25:11.928 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:25:11.980 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:25:11.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:11.984 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:25:11.986 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:25:12.008 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:12.008 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:12.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:25:12.029 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:12.030 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:12.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:25:12.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:12.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:12.036 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:25:12.036 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:25:12.036 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:25:12.036 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:25:12.066 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:25:12.066 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:25:12.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:12.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:12.400 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:25:12.449 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:25:12.449 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:25:12.449 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:25:12.449 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:25:12.871 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:25:13.344 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:25:13.450 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:25:13.451 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:25:13.451 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:25:13.451 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:25:13.817 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:25:14.289 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:25:14.451 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:25:14.452 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:25:14.452 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:25:14.452 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:25:14.760 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:25:15.234 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:25:15.452 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:25:15.453 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:25:15.453 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:25:15.453 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:25:15.706 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:25:16.179 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:25:16.453 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:25:16.454 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:25:16.454 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:25:16.454 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:25:16.649 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:25:17.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:17.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:17.074 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:17.074 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:17.093 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:17.093 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:17.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:25:17.099 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:17.099 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:17.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:25:17.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:17.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:17.101 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:25:17.101 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:25:17.101 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:25:17.101 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:25:17.117 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:25:17.117 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:25:17.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:17.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:17.122 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:25:17.595 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:25:18.067 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:25:18.538 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:25:19.011 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:25:19.484 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:25:19.956 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:25:20.427 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:25:20.900 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:25:21.373 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:25:21.845 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:25:22.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:22.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:22.126 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:22.126 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:22.143 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:22.143 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:22.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:25:22.149 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:22.149 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:22.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:25:22.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:22.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:22.150 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:25:22.150 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:25:22.150 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:25:22.150 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:25:22.169 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:25:22.169 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:25:22.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:22.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:22.316 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:25:22.787 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:25:23.257 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:25:23.728 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:25:24.202 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:25:24.674 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:25:25.146 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:25:25.617 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:25:26.088 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:25:26.561 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:25:27.033 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:25:27.173 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:27.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:27.178 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:27.178 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:27.188 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:27.188 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:27.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:25:27.193 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:27.193 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:27.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:25:27.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:27.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:27.194 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:25:27.194 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:25:27.194 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:25:27.194 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:25:27.216 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:25:27.217 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:25:27.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:27.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:27.505 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:25:27.976 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:25:28.450 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:25:28.922 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:25:29.394 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:25:29.865 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:25:30.338 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:25:30.811 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:25:31.283 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:25:31.754 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:25:32.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:32.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:32.226 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:32.226 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:32.227 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 02:25:32.238 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:25:32.238 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:25:32.238 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:25:32.239 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:25:32.240 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:25:32.241 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:25:32.241 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:25:32.241 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:25:32.241 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:25:32.241 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:25:32.241 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:25:37.244 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:25:37.245 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:25:37.245 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:25:37.245 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:25:37.245 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:25:37.245 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:25:37.251 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:25:37.252 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:25:37.252 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:25:37.252 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:25:37.252 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:25:37.254 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:25:37.255 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:25:37.255 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:25:37.255 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:25:37.255 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:25:37.255 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:25:37.256 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:25:37.256 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:25:37.256 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:25:37.257 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:25:37.257 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:25:37.257 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:25:37.257 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:25:37.257 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:25:37.257 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:25:37.257 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:25:37.257 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:25:37.257 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:25:37.259 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:25:37.259 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:25:37.259 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:25:37.259 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:25:37.259 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:25:37.259 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:25:37.259 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:25:37.259 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:25:37.259 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:25:37.261 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:25:37.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:25:37.262 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:25:37.262 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:25:37.262 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:25:37.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:25:37.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:25:37.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:25:37.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:25:37.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:25:37.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:25:37.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:25:37.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:25:37.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:25:37.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:25:37.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:25:37.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:25:37.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:25:37.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:25:37.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:25:37.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:25:37.267 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:25:37.745 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:25:37.781 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:25:37.783 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:25:37.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:37.784 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:25:37.802 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:37.802 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:37.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:25:37.824 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:37.824 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:37.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:25:37.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:37.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:37.831 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:25:37.831 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:25:37.831 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:25:37.831 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:25:37.838 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:25:37.838 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:25:37.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:37.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:38.218 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:25:38.264 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:25:38.264 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:25:38.264 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:25:38.264 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:25:38.689 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:25:39.159 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:25:39.265 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:25:39.265 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:25:39.265 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:25:39.265 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:25:39.633 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:25:40.105 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:25:40.266 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:25:40.266 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:25:40.267 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:25:40.267 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:25:40.577 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:25:41.048 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:25:41.268 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:25:41.268 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:25:41.268 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:25:41.268 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:25:41.519 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:25:41.990 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:25:42.269 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:25:42.270 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:25:42.270 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:25:42.270 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:25:42.461 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:25:42.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:42.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:42.847 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:42.847 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:42.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:42.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:42.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:25:42.871 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:42.872 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:42.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:25:42.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:42.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:42.873 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:25:42.873 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:25:42.873 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:25:42.873 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:25:42.875 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:25:42.875 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:25:42.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:42.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:42.931 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:25:43.402 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:25:43.876 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:25:44.348 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:25:44.821 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:25:45.294 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:25:45.766 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:25:46.239 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:25:46.712 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:25:47.185 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:25:47.657 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:25:47.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:47.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:47.882 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:47.882 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:47.899 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:47.899 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:47.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:25:47.905 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:47.905 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:47.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:25:47.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:47.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:47.906 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:25:47.906 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:25:47.906 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:25:47.906 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:25:47.936 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:25:47.936 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:25:47.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:47.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:48.127 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:25:48.598 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:25:49.069 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:25:49.540 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:25:50.013 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:25:50.486 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:25:50.958 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:25:51.429 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:25:51.903 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:25:52.375 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:25:52.847 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:25:52.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:52.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:52.944 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:52.945 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:52.956 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:52.956 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:52.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:25:52.962 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:52.962 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:52.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:25:52.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:52.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:52.964 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:25:52.964 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:25:52.964 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:25:52.964 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:25:52.982 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:25:52.982 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:25:52.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:52.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:53.317 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:25:53.788 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:25:54.261 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:25:54.734 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:25:55.206 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:25:55.680 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:25:56.152 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:25:56.624 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:25:57.095 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:25:57.566 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:25:57.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:25:57.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:25:57.990 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:25:57.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:25:58.003 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:25:58.004 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:25:58.004 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:25:58.004 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:25:58.005 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:25:58.005 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:25:58.006 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:25:58.006 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:25:58.006 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:25:58.006 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:25:58.006 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:26:03.010 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:26:03.010 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:26:03.010 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:26:03.010 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:26:03.010 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:26:03.010 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:26:03.018 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:26:03.019 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:26:03.019 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:26:03.019 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:26:03.020 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:26:03.022 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:26:03.022 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:26:03.023 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:26:03.023 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:26:03.023 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:26:03.023 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:26:03.023 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:26:03.023 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:26:03.023 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:26:03.025 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:26:03.025 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:26:03.025 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:26:03.025 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:26:03.026 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:26:03.026 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:26:03.026 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:26:03.026 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:26:03.026 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:26:03.027 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:26:03.027 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:26:03.027 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:26:03.027 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:26:03.027 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:26:03.027 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:26:03.028 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:26:03.028 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:26:03.028 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:26:03.030 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:26:03.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:26:03.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:26:03.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:26:03.030 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:26:03.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:26:03.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:26:03.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:26:03.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:26:03.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:26:03.030 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:26:03.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:26:03.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:26:03.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:26:03.030 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:26:03.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:26:03.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:26:03.031 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:26:03.031 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:26:03.031 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:26:03.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:26:03.035 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:26:03.514 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:26:03.551 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:26:03.552 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:26:03.553 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:26:03.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:03.569 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:03.569 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:03.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:26:03.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:03.589 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:03.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:26:03.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:03.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:03.598 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:26:03.598 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:26:03.599 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:26:03.599 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:26:03.606 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:26:03.607 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:26:03.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:03.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:03.987 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:26:04.033 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:26:04.033 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:26:04.033 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:26:04.033 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:26:04.458 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:26:04.931 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:26:05.034 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:26:05.034 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:26:05.034 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:26:05.034 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:26:05.404 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:26:05.876 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:26:06.034 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:26:06.035 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:26:06.035 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:26:06.035 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:26:06.347 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:26:06.821 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:26:07.036 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:26:07.036 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:26:07.037 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:26:07.037 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:26:07.293 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:26:07.765 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:26:08.038 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:26:08.038 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:26:08.038 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:26:08.038 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:26:08.236 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:26:08.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:08.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:08.616 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:08.616 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:08.634 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:08.634 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:08.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:26:08.640 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:08.640 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:08.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:26:08.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:08.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:08.642 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:26:08.642 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:26:08.642 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:26:08.642 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:26:08.652 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:26:08.652 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:26:08.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:08.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:08.707 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:26:09.178 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:26:09.651 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:26:10.123 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:26:10.596 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:26:11.069 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:26:11.541 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:26:12.014 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:26:12.485 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:26:12.958 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:26:13.430 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:26:13.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:13.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:13.660 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:13.661 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:13.678 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:13.678 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:13.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:26:13.683 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:13.683 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:13.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:26:13.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:13.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:13.685 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:26:13.685 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:26:13.685 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:26:13.685 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:26:13.711 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:26:13.712 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:26:13.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:13.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:13.903 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:26:14.374 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:26:14.847 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:26:15.319 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:26:15.791 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:26:16.262 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:26:16.733 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:26:17.206 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:26:17.679 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:26:18.151 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:26:18.622 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:26:18.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:18.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:18.721 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:18.721 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:18.739 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:18.739 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:18.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:26:18.745 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:18.745 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:18.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:26:18.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:18.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:18.748 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:26:18.748 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:26:18.748 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:26:18.748 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:26:18.756 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:26:18.756 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:26:18.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:18.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:19.092 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:26:19.565 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:26:20.038 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:26:20.510 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:26:20.981 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:26:21.454 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:26:21.927 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:26:22.399 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:26:22.870 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:26:23.343 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:26:23.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:23.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:23.763 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:23.763 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:23.777 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:26:23.778 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:26:23.778 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:26:23.778 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:26:23.780 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:26:23.780 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:26:23.780 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:26:23.780 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:26:23.780 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:26:23.780 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:26:23.780 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:26:28.784 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:26:28.784 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:26:28.784 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:26:28.784 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:26:28.784 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:26:28.784 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:26:28.790 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:26:28.791 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:26:28.792 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:26:28.792 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:26:28.792 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:26:28.795 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:26:28.796 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:26:28.796 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:26:28.796 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:26:28.797 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:26:28.797 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:26:28.797 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:26:28.797 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:26:28.798 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:26:28.799 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:26:28.799 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:26:28.800 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:26:28.800 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:26:28.800 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:26:28.800 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:26:28.800 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:26:28.800 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:26:28.800 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:26:28.802 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:26:28.802 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:26:28.802 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:26:28.802 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:26:28.802 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:26:28.802 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:26:28.803 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:26:28.803 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:26:28.803 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:26:28.806 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:26:28.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:26:28.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:26:28.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:26:28.806 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:26:28.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:26:28.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:26:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:26:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:26:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:26:28.807 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:26:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:26:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:26:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:26:28.807 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:26:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:26:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:26:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:26:28.807 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:26:28.807 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:26:28.807 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:26:28.807 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:26:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:26:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:26:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:26:28.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:26:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:26:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:26:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:26:28.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:26:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:26:28.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:26:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:26:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:26:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:26:28.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:26:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:26:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:26:28.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:26:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:26:28.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:26:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:26:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:26:28.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:26:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:26:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:26:28.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:26:28.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:26:28.812 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:26:29.291 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:26:29.331 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:26:29.332 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:26:29.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:29.334 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:26:29.354 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:29.354 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:29.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:26:29.377 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:29.377 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:29.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:26:29.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:29.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:29.386 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:26:29.386 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:26:29.386 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:26:29.386 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:26:29.429 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:26:29.430 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:26:29.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:29.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:29.763 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:26:29.810 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:26:29.810 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:26:29.811 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:26:29.811 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:26:30.234 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:26:30.705 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:26:30.811 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:26:30.811 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:26:30.812 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:26:30.812 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:26:31.176 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:26:31.647 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:26:31.812 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:26:31.813 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:26:31.813 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:26:31.813 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:26:32.117 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:26:32.588 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:26:32.813 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:26:32.814 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:26:32.814 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:26:32.814 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:26:33.059 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:26:33.532 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:26:33.815 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:26:33.815 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:26:33.816 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:26:33.816 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:26:34.005 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:26:34.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:34.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:34.439 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:34.439 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:34.458 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:34.458 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:34.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:26:34.464 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:34.464 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:34.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:26:34.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:34.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:34.465 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:26:34.465 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:26:34.465 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:26:34.466 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:26:34.472 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:26:34.472 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:26:34.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:34.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:34.477 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:26:34.948 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:26:35.421 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:26:35.894 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:26:36.366 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:26:36.840 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:26:37.312 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:26:37.784 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:26:38.255 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:26:38.728 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:26:39.201 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:26:39.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:39.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:39.479 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:39.479 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:39.497 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:39.497 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:39.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:26:39.502 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:39.502 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:39.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:26:39.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:39.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:39.504 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:26:39.504 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:26:39.504 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:26:39.504 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:26:39.528 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:26:39.528 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:26:39.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:39.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:39.673 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:26:40.144 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:26:40.615 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:26:41.088 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:26:41.561 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:26:42.033 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:26:42.504 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:26:42.977 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:26:43.450 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:26:43.922 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:26:44.393 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:26:44.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:44.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:44.536 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:44.536 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:44.556 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:44.556 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:44.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:26:44.562 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:44.562 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:44.562 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:26:44.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:44.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:44.564 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:26:44.564 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:26:44.564 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:26:44.564 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:26:44.573 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:26:44.573 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:26:44.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:44.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:44.863 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:26:45.334 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:26:45.805 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:26:46.279 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:26:46.751 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:26:47.223 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:26:47.694 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:26:48.167 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:26:48.639 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:26:49.111 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:26:49.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:49.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:49.580 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:49.580 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:49.583 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 02:26:49.586 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:26:49.586 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:26:49.586 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:26:49.586 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:26:49.587 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:26:49.587 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:26:49.587 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:26:49.587 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:26:49.587 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:26:49.587 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:26:49.587 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:26:54.594 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:26:54.594 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:26:54.594 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:26:54.594 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:26:54.594 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:26:54.594 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:26:54.601 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:26:54.602 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:26:54.602 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:26:54.602 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:26:54.603 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:26:54.605 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:26:54.605 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:26:54.605 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:26:54.605 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:26:54.605 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:26:54.606 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:26:54.606 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:26:54.606 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:26:54.606 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:26:54.607 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:26:54.607 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:26:54.607 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:26:54.607 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:26:54.607 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:26:54.608 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:26:54.608 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:26:54.608 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:26:54.608 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:26:54.609 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:26:54.609 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:26:54.609 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:26:54.610 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:26:54.610 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:26:54.610 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:26:54.610 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:26:54.610 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:26:54.610 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:26:54.612 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:26:54.612 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:26:54.612 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:26:54.612 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:26:54.612 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:26:54.612 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:26:54.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:26:54.612 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:26:54.612 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:26:54.612 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:26:54.612 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:26:54.613 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:26:54.613 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:26:54.613 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:26:54.613 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:26:54.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:26:54.614 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:26:54.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:26:54.614 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:26:54.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:26:54.617 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:26:55.096 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:26:55.137 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:26:55.139 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:26:55.140 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:26:55.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:55.160 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:55.160 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:55.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:26:55.181 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:55.181 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:55.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:26:55.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:55.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:55.189 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:26:55.189 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:26:55.189 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:26:55.189 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:26:55.234 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:26:55.235 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:26:55.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:55.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:55.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:55.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:55.479 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:55.479 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:55.493 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:55.493 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:55.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:26:55.500 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:55.500 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:55.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:26:55.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:55.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:55.501 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:26:55.501 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:26:55.502 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:26:55.502 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:26:55.514 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:26:55.515 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:26:55.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:55.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:55.566 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:26:55.615 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:26:55.616 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:26:55.616 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:26:55.616 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:26:55.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:55.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:55.895 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:55.895 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:55.906 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:55.906 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:55.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:26:55.912 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:55.912 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:55.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:26:55.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:55.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:55.913 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:26:55.913 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:26:55.913 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:26:55.913 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:26:55.935 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:26:55.936 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:26:55.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:55.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:56.039 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:26:56.511 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:26:56.616 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:26:56.616 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:26:56.616 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:26:56.617 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:26:56.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:56.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:56.670 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:56.671 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:56.689 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:56.689 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:56.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:26:56.695 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:56.695 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:56.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:26:56.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:56.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:56.697 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:26:56.697 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:26:56.697 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:26:56.697 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:26:56.744 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:26:56.745 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:26:56.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:56.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:56.981 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:26:57.453 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:26:57.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:26:57.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:26:57.538 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:26:57.539 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:26:57.550 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:26:57.551 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:26:57.551 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:26:57.551 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:26:57.555 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:26:57.555 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:26:57.555 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:26:57.555 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:26:57.556 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:26:57.556 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:26:57.556 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:26:57.556 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=636 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:26:57.556 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=636 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:26:57.556 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=636 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:26:57.556 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=636 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:26:57.556 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=636 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:26:57.557 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=636 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:26:57.557 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=636 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:27:02.559 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:27:02.559 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:27:02.559 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:27:02.559 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:27:02.559 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:27:02.559 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:27:02.566 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:27:02.567 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:27:02.567 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:27:02.567 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:27:02.567 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:27:02.569 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:27:02.569 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:27:02.570 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:27:02.570 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:27:02.570 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:27:02.570 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:27:02.571 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:27:02.571 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:27:02.571 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:27:02.572 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:27:02.572 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:27:02.572 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:27:02.572 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:27:02.572 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:27:02.572 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:27:02.572 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:27:02.572 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:27:02.572 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:27:02.574 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:27:02.574 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:27:02.574 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:27:02.574 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:27:02.574 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:27:02.574 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:27:02.574 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:27:02.574 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:27:02.574 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:27:02.577 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:27:02.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:27:02.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:27:02.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:27:02.577 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:27:02.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:27:02.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:27:02.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:27:02.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:27:02.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:27:02.577 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:27:02.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:27:02.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:27:02.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:27:02.577 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:27:02.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:27:02.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:27:02.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:27:02.577 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:27:02.577 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:27:02.577 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:27:02.577 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:27:02.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:27:02.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:27:02.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:27:02.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:27:02.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:27:02.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:27:02.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:27:02.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:27:02.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:27:02.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:27:02.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:27:02.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:27:02.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:27:02.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:27:02.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:27:02.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:27:02.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:27:02.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:27:02.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:27:02.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:27:02.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:27:02.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:27:02.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:27:02.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:27:02.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:27:02.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:27:02.582 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:27:03.058 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:27:03.098 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:27:03.099 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:27:03.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:27:03.101 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:27:03.125 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:27:03.125 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:27:03.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:27:03.143 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:27:03.143 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:27:03.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:27:03.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:27:03.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:27:03.148 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:27:03.148 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:27:03.148 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:27:03.148 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:27:03.196 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:27:03.196 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:27:03.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:27:03.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:27:03.528 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:27:03.579 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:27:03.580 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:27:03.580 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:27:03.581 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:27:04.001 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:27:04.473 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:27:04.580 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:27:04.581 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:27:04.581 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:27:04.581 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:27:04.946 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:27:05.419 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:27:05.582 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:27:05.582 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:27:05.582 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:27:05.582 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:27:05.891 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:27:06.365 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:27:06.583 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:27:06.583 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:27:06.583 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:27:06.583 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:27:06.837 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:27:07.310 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:27:07.583 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:27:07.584 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:27:07.584 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:27:07.584 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:27:07.783 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:27:08.256 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:27:08.728 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:27:09.199 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:27:09.670 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:27:10.141 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:27:10.614 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:27:11.087 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:27:11.559 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:27:12.030 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:27:12.502 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:27:12.975 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:27:13.447 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:27:13.918 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:27:14.389 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:27:14.862 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:27:15.335 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:27:15.807 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:27:16.281 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:27:16.753 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:27:17.226 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:27:17.696 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:27:18.167 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:27:18.641 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:27:19.113 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:27:19.586 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:27:20.057 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:27:20.530 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:27:21.003 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:27:21.475 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:27:21.946 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:27:22.417 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:27:22.888 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:27:23.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:27:23.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:27:23.207 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:27:23.207 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:27:23.226 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:27:23.226 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:27:23.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:27:23.232 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:27:23.233 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:27:23.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:27:23.233 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:27:23.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:27:23.234 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:27:23.234 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:27:23.234 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:27:23.234 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:27:23.259 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:27:23.259 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:27:23.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:27:23.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:27:23.359 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 02:27:23.833 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 02:27:24.304 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 02:27:24.776 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 02:27:25.246 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 02:27:25.717 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 02:27:26.188 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 02:27:26.659 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 02:27:27.132 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 02:27:27.604 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 02:27:28.077 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 02:27:28.550 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 02:27:29.023 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 02:27:29.495 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 02:27:29.969 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 02:27:30.441 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 02:27:30.913 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 02:27:31.384 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 02:27:31.855 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 02:27:32.326 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 02:27:32.797 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 02:27:33.267 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 02:27:33.740 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 02:27:34.213 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 02:27:34.685 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 02:27:35.156 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 02:27:35.630 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 02:27:36.102 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 02:27:36.575 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 02:27:37.048 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 02:27:37.520 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-06 02:27:37.992 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-06 02:27:38.463 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-06 02:27:38.937 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-06 02:27:39.409 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-06 02:27:39.882 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-06 02:27:40.355 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-06 02:27:40.828 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-06 02:27:41.300 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-06 02:27:41.773 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-06 02:27:42.246 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-06 02:27:42.718 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-06 02:27:43.192 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-06 02:27:43.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:27:43.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:27:43.273 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:27:43.273 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:27:43.291 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:27:43.291 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:27:43.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:27:43.297 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:27:43.297 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:27:43.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:27:43.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:27:43.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:27:43.298 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:27:43.298 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:27:43.298 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:27:43.298 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:27:43.325 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:27:43.325 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:27:43.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:27:43.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:27:43.663 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-06 02:27:44.135 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-06 02:27:44.609 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-06 02:27:45.081 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-06 02:27:45.554 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-06 02:27:46.027 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-06 02:27:46.499 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-06 02:27:46.972 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-06 02:27:47.443 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-06 02:27:47.913 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-06 02:27:48.384 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-06 02:27:48.855 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-06 02:27:49.328 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-06 02:27:49.801 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-06 02:27:50.272 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-06 02:27:50.744 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-06 02:27:51.217 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-06 02:27:51.689 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-06 02:27:52.161 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-06 02:27:52.633 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-06 02:27:53.106 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-06 02:27:53.578 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-06 02:27:54.050 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-06 02:27:54.521 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-06 02:27:54.995 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-06 02:27:55.467 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-06 02:27:55.939 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-06 02:27:56.410 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-06 02:27:56.881 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-06 02:27:57.354 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-06 02:27:57.827 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-06 02:27:58.299 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-06 02:27:58.770 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-06 02:27:59.243 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-06 02:27:59.715 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-06 02:28:00.187 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-06 02:28:00.658 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-06 02:28:01.129 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-06 02:28:01.602 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-06 02:28:02.075 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-06 02:28:02.546 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-06 02:28:03.010 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-06 02:28:03.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:03.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:03.328 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:03.328 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:03.335 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:03.335 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:03.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:28:03.341 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:03.341 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:03.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:28:03.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:03.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:03.343 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:03.343 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:03.343 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:28:03.343 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:28:03.378 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:03.378 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:03.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:03.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:03.475 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-06 02:28:03.939 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-06 02:28:04.404 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-06 02:28:04.870 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-06 02:28:05.332 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-06 02:28:05.794 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-06 02:28:06.257 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-06 02:28:06.723 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-06 02:28:07.195 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-06 02:28:07.668 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-06 02:28:08.141 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-06 02:28:08.612 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-06 02:28:09.081 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-06 02:28:09.553 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-06 02:28:10.022 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-06 02:28:10.496 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-06 02:28:10.968 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-06 02:28:11.438 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-06 02:28:11.912 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-06 02:28:12.384 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-06 02:28:12.857 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-06 02:28:13.327 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-06 02:28:13.801 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-06 02:28:14.273 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-06 02:28:14.745 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-06 02:28:15.216 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-06 02:28:15.689 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-06 02:28:16.162 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-06 02:28:16.634 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-06 02:28:17.105 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-06 02:28:17.579 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-06 02:28:18.051 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-06 02:28:18.523 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-06 02:28:18.994 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-06 02:28:19.467 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-06 02:28:19.940 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-06 02:28:20.412 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-06 02:28:20.883 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-06 02:28:21.354 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-06 02:28:21.827 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-06 02:28:22.300 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-06 02:28:22.772 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-06 02:28:23.243 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-06 02:28:23.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:23.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:23.385 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:23.385 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:23.395 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:28:23.395 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:28:23.395 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:28:23.395 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:28:23.395 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:28:23.395 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:28:23.395 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:28:23.395 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:28:23.395 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:28:23.396 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:28:23.396 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:28:28.401 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:28:28.401 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:28:28.402 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:28:28.402 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:28:28.402 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:28:28.402 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:28:28.410 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:28:28.411 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:28:28.411 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:28:28.411 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:28:28.411 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:28:28.412 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:28:28.412 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:28:28.412 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:28:28.412 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:28:28.412 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:28:28.413 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:28:28.413 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:28:28.413 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:28:28.413 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:28:28.415 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:28:28.415 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:28:28.415 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:28:28.415 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:28:28.415 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:28:28.415 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:28:28.415 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:28:28.415 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:28:28.415 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:28:28.417 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:28:28.417 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:28:28.417 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:28:28.417 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:28:28.417 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:28:28.417 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:28:28.417 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:28:28.417 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:28:28.417 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:28:28.419 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:28:28.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:28:28.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:28:28.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:28:28.419 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:28:28.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:28:28.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:28:28.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:28:28.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:28:28.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:28:28.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:28:28.419 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:28:28.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:28:28.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:28:28.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:28:28.419 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:28:28.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:28:28.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:28:28.419 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:28:28.419 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:28:28.419 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:28:28.419 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:28:28.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:28:28.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:28:28.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:28:28.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:28:28.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:28:28.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:28:28.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:28:28.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:28:28.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:28:28.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:28:28.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:28:28.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:28:28.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:28:28.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:28:28.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:28:28.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:28:28.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:28:28.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:28:28.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:28:28.421 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:28:28.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:28:28.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:28:28.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:28:28.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:28:28.421 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:28:28.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:28:28.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:28:28.421 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:28:28.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:28:28.421 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:28:28.421 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:28:28.421 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:28:28.421 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:28:33.427 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:28:33.427 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:28:33.428 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:28:33.428 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:28:33.428 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:28:33.428 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:28:33.432 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:28:33.433 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:28:33.433 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:28:33.433 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:28:33.434 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:28:33.436 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:28:33.436 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:28:33.437 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:28:33.437 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:28:33.437 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:28:33.437 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:28:33.438 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:28:33.438 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:28:33.438 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:28:33.440 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:28:33.441 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:28:33.441 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:28:33.441 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:28:33.442 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:28:33.442 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:28:33.442 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:28:33.442 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:28:33.443 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:28:33.444 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:28:33.445 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:28:33.445 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:28:33.445 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:28:33.445 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:28:33.445 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:28:33.445 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:28:33.445 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:28:33.445 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:28:33.450 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:28:33.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:28:33.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:28:33.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:28:33.450 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:28:33.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:28:33.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:28:33.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:28:33.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:28:33.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:28:33.450 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:28:33.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:28:33.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:28:33.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:28:33.450 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:28:33.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:28:33.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:28:33.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:28:33.451 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:28:33.451 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:28:33.451 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:28:33.451 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:28:33.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:28:33.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:28:33.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:28:33.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:28:33.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:28:33.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:28:33.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:28:33.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:28:33.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:28:33.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:28:33.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:28:33.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:28:33.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:28:33.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:28:33.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:28:33.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:28:33.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:28:33.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:28:33.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:28:33.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:28:33.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:28:33.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:28:33.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:28:33.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:28:33.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:28:33.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:28:33.455 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:28:33.933 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:28:33.985 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:28:33.987 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:28:33.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:33.988 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:28:34.008 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:34.009 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:34.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:28:34.028 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:34.028 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:34.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:28:34.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:34.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:34.032 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:34.032 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:34.032 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:28:34.032 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:28:34.071 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:34.072 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:34.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:34.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:34.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:34.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:34.275 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:34.275 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:34.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:34.292 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:34.292 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:34.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:28:34.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:34.294 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:34.294 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:34.294 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:28:34.294 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:28:34.304 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:34.304 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:34.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:34.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:34.402 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:28:34.454 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:28:34.455 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:28:34.456 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:28:34.456 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:28:34.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:34.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:34.510 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:34.510 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:34.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:34.519 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:34.519 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:34.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:28:34.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:34.520 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:34.520 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:34.520 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:28:34.520 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:28:34.535 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:34.535 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:34.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:34.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:34.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:34.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:34.749 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:34.750 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:34.769 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:34.769 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:34.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:28:34.774 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:34.774 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:34.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:28:34.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:34.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:34.777 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:34.777 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:34.777 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:28:34.777 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:28:34.819 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:34.820 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:34.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:34.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:34.872 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:28:35.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:35.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:35.129 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:35.129 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:35.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:35.139 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:35.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:35.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:28:35.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:35.141 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:35.141 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:35.141 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:28:35.141 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:28:35.148 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:35.148 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:35.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:35.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:35.344 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:28:35.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:35.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:35.452 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:35.452 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:35.456 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:28:35.456 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:28:35.456 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:28:35.457 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:28:35.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:35.468 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:35.468 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:35.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:28:35.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:35.470 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:35.470 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:35.470 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:28:35.470 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:28:35.476 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:35.476 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:35.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:35.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:35.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:35.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:35.771 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:35.771 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:35.787 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:35.787 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:35.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:28:35.793 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:35.793 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:35.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:28:35.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:35.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:35.794 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:35.794 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:35.795 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:28:35.795 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:28:35.810 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:35.810 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:35.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:35.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:35.817 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:28:36.289 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:28:36.456 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:28:36.457 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:28:36.457 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:28:36.457 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:28:36.761 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:28:37.232 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:28:37.457 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:28:37.458 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:28:37.458 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:28:37.458 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:28:37.705 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:28:38.178 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:28:38.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:38.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:38.338 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:38.339 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:38.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:38.353 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:38.353 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:38.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:28:38.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:38.355 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:38.355 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:38.355 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:28:38.355 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:28:38.359 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:38.359 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:38.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:38.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:38.459 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:28:38.459 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:28:38.459 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:28:38.459 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:28:38.649 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:28:39.121 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:28:39.592 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:28:40.065 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:28:40.537 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:28:40.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:40.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:40.933 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:40.933 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:40.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:40.947 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:40.947 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:40.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:28:40.949 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:40.949 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:40.949 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:40.949 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:28:40.949 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:28:40.954 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:40.954 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:40.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:40.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:41.009 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:28:41.480 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:28:41.954 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:28:42.426 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:28:42.898 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:28:43.369 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:28:43.523 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:43.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:43.528 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:43.528 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:43.547 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:43.547 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:43.547 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:28:43.553 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:43.553 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:43.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:43.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:28:43.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:43.555 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:43.555 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:43.555 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:28:43.555 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:28:43.603 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:43.603 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:43.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:43.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:43.840 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:28:44.314 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:28:44.786 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:28:45.258 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:28:45.729 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:28:46.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:46.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:46.051 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:46.051 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:46.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:46.068 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:46.068 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:46.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:28:46.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:46.070 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:46.070 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:46.070 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:28:46.070 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:28:46.101 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:46.102 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:46.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:46.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:46.202 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:28:46.675 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:28:47.147 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:28:47.618 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:28:48.091 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:28:48.564 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:28:48.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:48.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:48.650 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:48.650 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:48.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:48.666 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:48.666 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:48.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:28:48.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:48.668 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:48.668 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:48.668 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:28:48.668 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:28:48.702 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:48.703 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:48.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:48.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:49.036 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:28:49.507 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:28:49.980 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:28:50.453 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:28:50.925 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:28:51.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:51.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:51.246 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:51.247 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:51.261 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:28:51.262 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:28:51.262 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:28:51.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:28:51.266 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:28:51.266 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:28:51.266 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:28:51.266 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:28:51.266 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:28:51.266 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:28:51.267 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:28:51.267 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3850 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:28:51.267 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3850 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:28:51.267 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3850 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:28:51.267 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3850 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:28:51.267 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3850 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:28:51.268 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3850 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:28:56.273 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:28:56.273 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:28:56.274 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:28:56.274 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:28:56.274 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:28:56.274 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:28:56.286 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:28:56.287 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:28:56.287 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:28:56.287 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:28:56.287 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:28:56.289 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:28:56.289 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:28:56.289 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:28:56.289 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:28:56.290 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:28:56.290 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:28:56.290 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:28:56.290 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:28:56.290 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:28:56.291 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:28:56.291 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:28:56.291 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:28:56.291 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:28:56.291 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:28:56.291 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:28:56.291 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:28:56.291 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:28:56.291 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:28:56.293 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:28:56.293 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:28:56.293 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:28:56.293 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:28:56.293 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:28:56.293 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:28:56.293 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:28:56.293 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:28:56.294 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:28:56.296 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:28:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:28:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:28:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:28:56.296 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:28:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:28:56.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:28:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:28:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:28:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:28:56.297 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:28:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:28:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:28:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:28:56.297 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:28:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:28:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:28:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:28:56.297 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:28:56.297 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:28:56.297 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:28:56.297 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:28:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:28:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:28:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:28:56.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:28:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:28:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:28:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:28:56.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:28:56.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:28:56.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:28:56.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:28:56.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:28:56.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:28:56.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:28:56.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:28:56.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:28:56.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:28:56.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:28:56.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:28:56.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:28:56.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:28:56.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:28:56.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:28:56.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:28:56.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:28:56.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:28:56.302 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:28:56.779 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:28:56.827 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:28:56.829 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:28:56.831 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:28:56.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:56.855 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:56.855 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:56.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:28:56.867 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:28:56.867 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:28:56.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:28:56.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:28:56.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:56.870 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:56.870 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:56.870 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:28:56.870 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:28:56.917 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:28:56.917 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:28:56.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:56.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:28:57.250 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:28:57.301 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:28:57.301 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:28:57.301 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:28:57.301 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:28:57.723 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:28:58.194 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:28:58.302 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:28:58.302 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:28:58.302 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:28:58.303 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:28:58.667 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:28:59.140 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:28:59.303 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:28:59.303 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:28:59.303 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:28:59.303 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:28:59.612 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:29:00.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:00.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:00.035 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:00.035 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:00.054 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:00.054 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:00.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:00.059 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:00.059 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:00.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:00.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:00.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:00.061 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:00.061 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:00.061 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:29:00.061 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:29:00.079 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:00.079 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:00.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:00.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:00.082 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:29:00.304 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:00.304 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:00.304 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:00.304 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:00.553 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:29:01.032 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:29:01.305 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:01.305 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:01.305 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:01.305 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:01.503 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:29:01.975 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:29:02.447 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:29:02.920 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:29:03.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:03.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:03.285 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:03.285 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:03.302 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:03.302 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:03.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:03.307 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:03.307 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:03.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:03.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:03.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:03.308 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:03.308 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:03.308 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:29:03.308 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:29:03.340 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:03.340 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:03.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:03.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:03.392 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:29:03.863 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:29:04.334 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:29:04.805 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:29:05.276 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:29:05.747 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:29:06.220 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:29:06.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:06.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:06.623 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:06.623 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:06.639 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:06.639 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:06.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:06.644 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:06.644 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:06.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:06.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:06.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:06.646 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:06.646 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:06.646 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:29:06.646 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:29:06.686 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:06.686 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:06.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:06.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:06.692 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:29:07.164 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:29:07.635 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:29:08.108 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:29:08.581 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:29:09.053 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:29:09.524 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:29:09.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:09.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:09.849 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:09.849 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:09.862 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:09.862 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:09.863 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:09.863 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:09.866 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:29:09.867 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:29:09.867 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:29:09.867 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:29:09.867 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:29:09.867 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:29:09.868 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:29:09.868 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2932 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:09.868 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2932 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:09.868 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2932 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:09.868 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2932 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:09.868 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2932 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:09.868 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2932 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:09.868 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2932 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:14.871 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:29:14.871 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:29:14.871 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:29:14.871 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:29:14.871 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:29:14.871 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:29:14.879 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:29:14.880 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:29:14.880 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:29:14.881 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:29:14.881 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:29:14.885 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:29:14.885 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:29:14.885 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:29:14.885 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:29:14.885 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:29:14.885 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:29:14.886 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:29:14.886 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:29:14.886 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:14.890 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:29:14.890 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:29:14.890 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:29:14.890 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:29:14.890 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:29:14.891 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:29:14.891 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:29:14.891 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:29:14.891 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:14.895 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:29:14.895 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:29:14.895 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:29:14.895 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:29:14.895 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:29:14.895 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:29:14.896 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:29:14.896 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:29:14.896 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:14.901 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:29:14.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:29:14.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:29:14.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:29:14.901 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:29:14.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:29:14.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:29:14.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:14.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:29:14.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:29:14.902 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:29:14.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:14.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:14.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:14.902 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:14.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:14.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:14.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:14.902 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:29:14.902 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:29:14.902 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:29:14.902 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:29:14.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:14.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:14.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:14.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:29:14.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:14.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:14.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:14.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:14.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:14.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:14.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:14.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:14.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:14.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:14.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:14.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:14.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:14.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:14.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:14.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:14.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:14.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:14.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:14.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:14.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:14.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:14.907 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:29:15.385 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:29:15.438 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:29:15.441 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:29:15.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:15.443 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:29:15.460 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:15.460 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:15.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:15.479 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:15.479 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:15.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:15.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:15.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:15.491 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:15.491 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:15.491 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:29:15.491 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:29:15.523 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:15.524 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:15.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:15.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:15.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:15.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:15.846 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:15.846 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:15.857 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:29:15.863 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:15.863 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:15.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:15.868 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:15.868 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:15.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:15.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:15.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:15.870 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:15.870 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:15.870 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:29:15.870 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:29:15.901 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:15.901 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:15.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:15.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:15.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:15.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:15.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:15.908 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:16.328 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:29:16.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:16.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:16.386 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:16.386 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:16.405 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:16.405 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:16.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:16.411 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:16.411 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:16.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:16.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:16.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:16.413 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:16.413 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:16.413 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:29:16.413 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:29:16.415 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:16.415 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:16.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:16.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:16.799 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:29:16.907 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:16.908 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:16.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:16.908 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:17.269 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:29:17.740 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:29:17.909 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:17.909 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:17.909 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:17.909 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:18.213 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:29:18.686 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:29:18.909 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:18.910 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:18.910 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:18.910 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:19.158 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:29:19.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:19.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:19.317 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:19.317 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:19.334 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:19.334 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:19.334 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:19.339 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:19.339 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:19.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:19.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:19.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:19.341 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:19.341 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:19.341 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:29:19.341 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:29:19.392 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:19.392 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:19.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:19.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:19.629 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:29:19.910 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:19.911 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:19.911 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:19.911 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:20.102 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:29:20.575 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:29:21.047 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:29:21.518 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:29:21.992 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:29:22.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:22.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:22.310 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:22.310 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:22.324 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:22.324 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:22.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:22.324 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:22.328 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:29:22.328 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:29:22.328 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:29:22.328 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:29:22.328 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:29:22.329 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:29:22.329 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:29:22.329 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1604 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:22.329 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1605 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:22.329 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1605 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:22.329 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1605 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:22.329 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1605 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:22.330 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1605 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:22.330 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1605 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:22.330 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1605 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:22.330 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1605 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:22.330 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1606 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:22.330 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1606 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:22.330 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1606 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:22.330 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1606 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:22.330 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1606 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:22.330 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1606 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:22.330 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1606 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:22.331 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1606 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:27.331 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:29:27.331 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:29:27.331 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:29:27.331 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:29:27.331 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:29:27.331 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:29:27.342 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:29:27.344 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:29:27.344 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:29:27.345 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:29:27.345 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:29:27.349 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:29:27.349 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:29:27.349 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:29:27.350 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:29:27.350 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:29:27.350 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:29:27.351 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:29:27.351 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:29:27.351 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:27.354 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:29:27.354 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:29:27.355 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:29:27.355 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:29:27.355 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:29:27.355 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:29:27.356 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:29:27.356 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:29:27.356 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:27.358 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:29:27.358 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:29:27.359 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:29:27.359 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:29:27.359 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:29:27.359 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:29:27.359 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:29:27.359 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:29:27.359 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:27.364 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:29:27.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:29:27.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:29:27.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:29:27.364 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:29:27.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:29:27.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:29:27.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:27.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:29:27.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:29:27.365 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:29:27.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:27.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:27.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:27.365 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:27.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:27.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:27.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:27.365 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:29:27.365 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:29:27.365 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:29:27.365 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:29:27.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:27.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:27.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:27.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:29:27.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:27.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:27.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:27.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:27.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:27.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:27.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:27.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:27.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:27.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:27.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:27.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:27.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:27.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:27.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:27.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:27.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:27.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:27.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:27.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:27.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:27.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:27.370 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:29:27.847 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:29:27.881 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:29:27.881 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:29:27.882 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:29:27.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:27.896 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:27.896 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:27.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:27.919 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:27.919 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:27.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:27.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:27.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:27.924 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:27.924 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:27.924 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:29:27.924 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:29:27.938 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:27.939 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:27.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:27.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:28.319 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:29:28.368 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:28.368 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:28.369 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:28.369 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:28.790 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:29:29.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:29.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:29.227 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:29.227 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:29.247 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:29.247 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:29.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:29.253 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:29.253 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:29.253 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:29.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:29.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:29.254 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:29.254 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:29.254 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:29:29.254 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:29:29.255 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:29.255 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:29.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:29.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:29.260 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:29:29.369 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:29.370 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:29.370 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:29.370 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:29.732 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:29:30.205 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:29:30.371 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:30.371 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:30.371 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:30.371 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:30.678 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:29:31.150 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:29:31.372 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:31.372 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:31.372 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:31.372 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:31.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:31.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:31.393 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:31.393 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:31.413 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:31.413 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:31.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:31.419 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:31.419 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:31.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:31.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:31.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:31.420 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:31.420 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:31.421 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:29:31.421 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:29:31.427 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:31.427 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:31.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:31.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:31.621 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:29:32.092 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:29:32.373 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:32.373 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:32.373 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:32.373 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:32.562 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:29:33.033 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:29:33.506 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:29:33.979 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:29:34.451 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:29:34.924 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:29:35.397 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:29:35.869 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:29:36.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:36.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:36.332 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:36.332 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:36.340 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:29:36.340 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:36.340 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:36.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:36.347 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:36.347 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:36.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:36.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:36.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:36.348 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:36.348 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:36.348 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:29:36.349 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:29:36.384 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:36.384 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:36.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:36.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:36.810 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:29:37.282 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:29:37.755 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:29:38.227 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:29:38.699 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:29:39.170 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:29:39.641 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:29:40.112 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:29:40.585 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:29:41.057 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:29:41.211 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:41.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:41.215 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:41.215 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:41.228 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:41.228 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:41.228 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:41.229 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:41.230 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:29:41.231 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:29:41.231 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:29:41.231 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:29:41.231 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:29:41.231 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:29:41.231 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:29:41.231 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2997 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:41.231 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2997 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:41.231 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2997 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:41.231 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2997 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:46.240 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:29:46.240 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:29:46.240 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:29:46.240 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:29:46.240 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:29:46.241 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:29:46.249 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:29:46.250 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:29:46.250 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:29:46.250 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:29:46.250 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:29:46.252 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:29:46.252 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:29:46.252 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:29:46.252 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:29:46.252 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:29:46.252 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:29:46.252 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:29:46.252 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:29:46.253 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:46.253 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:29:46.253 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:29:46.253 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:29:46.253 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:29:46.253 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:29:46.253 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:29:46.253 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:29:46.253 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:29:46.253 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:46.254 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:29:46.254 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:29:46.254 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:29:46.254 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:29:46.255 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:29:46.255 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:29:46.255 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:29:46.255 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:29:46.255 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:46.256 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:29:46.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:29:46.257 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:29:46.257 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:29:46.257 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:46.262 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:29:46.739 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:29:46.776 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:29:46.777 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:29:46.778 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:29:46.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:46.802 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:46.802 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:46.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:46.826 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:46.826 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:46.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:46.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:46.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:46.832 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:46.832 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:46.832 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:29:46.832 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:29:46.876 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:46.876 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:46.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:46.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:47.212 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:29:47.259 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:47.260 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:47.260 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:47.260 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:47.496 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:47.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:47.500 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:47.500 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:47.517 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:47.517 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:47.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:47.523 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:47.523 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:47.523 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:47.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:47.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:47.524 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:47.524 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:47.524 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:29:47.524 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:29:47.535 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:47.535 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:47.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:47.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:47.684 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:29:48.157 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:29:48.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:48.261 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:48.261 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:48.261 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:48.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:48.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:48.466 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:48.466 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:48.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:48.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:48.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:48.490 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:48.490 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:48.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:48.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:48.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:48.491 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:48.491 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:48.492 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:29:48.492 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:29:48.531 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:48.531 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:48.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:48.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:48.629 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:29:49.100 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:29:49.261 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:49.262 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:49.262 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:49.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:49.574 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:29:50.046 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:29:50.263 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:50.263 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:50.263 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:50.263 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:50.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:50.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:50.442 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:50.442 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:50.460 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:50.460 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:50.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:50.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:50.465 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:50.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:50.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:50.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:50.467 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:50.467 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:50.467 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:29:50.467 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:29:50.516 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:50.517 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:50.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:50.518 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:29:50.518 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:50.989 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:29:51.264 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:51.264 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:51.264 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:51.264 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:51.463 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:29:51.935 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:29:52.407 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:29:52.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:52.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:52.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:52.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:52.503 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:52.503 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:52.503 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:52.503 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:52.507 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:29:52.507 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:29:52.507 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:29:52.507 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:29:52.507 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:29:52.508 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:29:52.508 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:29:52.508 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1350 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:52.508 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1350 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:52.508 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1350 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:52.508 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1350 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:52.508 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1350 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:52.508 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1350 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:52.509 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1350 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:52.509 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1350 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:29:57.510 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:29:57.510 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:29:57.510 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:29:57.510 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:29:57.510 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:29:57.510 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:29:57.514 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:29:57.515 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:29:57.515 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:29:57.515 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:29:57.515 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:29:57.517 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:29:57.517 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:29:57.517 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:29:57.517 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:29:57.518 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:29:57.518 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:29:57.518 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:29:57.518 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:29:57.518 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:57.520 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:29:57.520 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:29:57.520 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:29:57.520 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:29:57.520 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:29:57.520 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:29:57.520 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:29:57.520 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:29:57.520 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:57.522 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:29:57.522 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:29:57.522 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:29:57.522 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:29:57.522 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:29:57.522 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:29:57.522 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:29:57.522 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:29:57.522 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:57.525 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:29:57.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:29:57.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:29:57.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:29:57.525 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:29:57.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:29:57.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:29:57.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:57.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:29:57.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:29:57.525 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:29:57.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:57.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:57.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:57.525 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:57.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:57.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:29:57.526 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:29:57.526 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:29:57.526 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:57.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:29:57.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:29:57.530 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:29:58.006 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:29:58.047 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:29:58.048 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:29:58.049 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:29:58.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:58.065 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:58.066 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:58.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:58.088 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:29:58.088 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:29:58.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:29:58.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:29:58.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:58.098 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:58.099 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:58.099 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:29:58.099 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:29:58.144 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:29:58.144 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:29:58.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:58.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:29:58.478 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:29:58.528 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:58.528 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:58.529 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:58.529 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:58.949 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:29:59.422 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:29:59.530 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:29:59.530 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:29:59.530 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:29:59.530 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:29:59.895 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:30:00.367 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:30:00.530 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:30:00.531 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:30:00.531 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:30:00.531 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:30:00.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:00.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:30:00.591 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:00.591 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:00.610 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:00.610 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:00.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:30:00.616 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:00.616 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:00.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:30:00.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:30:00.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:00.617 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:30:00.618 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:30:00.618 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:30:00.618 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:30:00.646 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:30:00.647 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:30:00.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:00.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:00.838 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:30:01.309 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:30:01.532 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:30:01.532 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:30:01.532 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:30:01.532 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:30:01.782 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:30:02.255 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:30:02.533 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:30:02.533 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:30:02.533 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:30:02.533 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:30:02.727 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:30:03.198 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:30:03.334 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:03.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:30:03.338 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:03.338 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:03.357 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:03.357 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:03.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:30:03.363 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:03.363 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:03.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:30:03.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:30:03.364 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:03.364 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:30:03.365 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:30:03.365 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:30:03.365 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:30:03.379 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:30:03.379 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:30:03.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:03.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:03.668 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:30:04.142 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:30:04.614 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:30:05.086 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:30:05.557 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:30:06.028 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:30:06.501 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:30:06.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:06.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:30:06.658 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:06.658 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:06.668 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:06.668 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:06.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:30:06.673 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:06.673 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:06.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:30:06.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:30:06.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:06.676 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:30:06.676 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:30:06.676 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:30:06.676 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:30:06.678 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:30:06.678 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:30:06.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:06.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:06.973 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:30:07.445 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:30:07.918 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:30:08.391 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:30:08.863 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:30:09.336 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:30:09.809 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:30:10.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:10.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:30:10.133 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:10.133 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:10.145 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:30:10.146 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:30:10.146 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:30:10.146 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:30:10.148 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:30:10.148 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:30:10.148 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:30:10.148 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:30:10.148 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:30:10.148 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:30:10.148 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:30:10.148 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2727 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:30:10.148 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2727 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:30:10.148 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2727 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:30:10.148 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2727 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:30:10.148 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2727 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:30:10.148 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2727 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:30:10.149 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2727 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:30:15.150 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:30:15.151 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:30:15.151 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:30:15.151 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:30:15.151 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:30:15.151 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:30:15.161 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:30:15.161 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:30:15.161 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:30:15.162 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:30:15.162 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:30:15.165 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:30:15.165 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:30:15.165 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:30:15.165 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:30:15.165 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:30:15.165 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:30:15.165 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:30:15.166 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:30:15.166 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:30:15.168 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:30:15.169 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:30:15.169 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:30:15.169 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:30:15.169 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:30:15.169 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:30:15.169 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:30:15.169 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:30:15.169 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:30:15.172 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:30:15.172 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:30:15.172 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:30:15.172 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:30:15.172 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:30:15.172 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:30:15.172 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:30:15.172 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:30:15.172 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:30:15.178 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:30:15.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:30:15.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:30:15.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:30:15.178 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:30:15.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:30:15.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:30:15.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:30:15.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:30:15.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:30:15.179 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:30:15.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:30:15.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:30:15.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:30:15.179 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:30:15.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:30:15.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:30:15.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:30:15.179 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:30:15.179 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:30:15.179 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:30:15.179 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:30:15.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:30:15.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:30:15.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:30:15.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:30:15.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:30:15.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:30:15.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:30:15.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:30:15.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:30:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:30:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:30:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:30:15.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:30:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:30:15.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:30:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:30:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:30:15.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:30:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:30:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:30:15.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:30:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:30:15.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:30:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:30:15.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:30:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:30:15.184 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:30:15.661 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:30:15.721 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:30:15.722 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:30:15.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:30:15.724 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:30:15.737 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:15.737 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:15.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:30:15.747 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:15.747 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:15.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:30:15.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:30:15.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:15.750 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:30:15.750 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:30:15.750 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:30:15.750 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:30:15.801 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:30:15.801 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:30:15.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:15.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:16.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:16.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:30:16.021 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:16.021 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:16.038 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:16.038 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:16.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:30:16.044 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:16.044 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:16.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:30:16.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:30:16.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:16.045 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:30:16.045 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:30:16.045 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:30:16.045 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:30:16.081 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:30:16.081 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:30:16.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:16.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:16.132 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:30:16.184 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:30:16.185 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:30:16.186 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:30:16.187 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:30:16.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:16.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:30:16.419 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:16.419 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:16.432 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:16.432 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:16.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:30:16.438 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:16.438 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:16.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:30:16.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:30:16.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:16.440 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:30:16.440 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:30:16.440 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:30:16.440 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:30:16.454 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:30:16.454 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:30:16.454 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:16.454 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:16.604 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:30:16.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:16.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:30:17.000 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:17.000 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:17.012 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:17.012 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:17.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:30:17.017 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:17.017 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:17.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:30:17.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:30:17.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:17.019 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:30:17.019 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:30:17.019 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:30:17.019 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:30:17.020 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:30:17.020 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:30:17.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:17.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:17.075 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:30:17.185 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:30:17.186 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:30:17.187 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:30:17.187 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:30:17.547 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:30:17.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:17.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:30:17.632 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:17.632 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:17.642 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:30:17.642 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:30:17.642 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:30:17.642 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:30:17.645 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:30:17.645 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:30:17.645 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:30:17.645 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:30:17.645 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:30:17.645 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:30:17.645 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:30:17.645 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=533 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:30:17.645 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=533 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:30:17.645 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=533 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:30:17.645 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=533 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:30:17.645 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=533 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:30:17.645 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=533 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:30:22.648 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:30:22.648 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:30:22.648 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:30:22.648 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:30:22.648 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:30:22.648 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:30:22.671 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:30:22.674 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:30:22.674 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:30:22.675 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:30:22.675 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:30:22.681 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:30:22.681 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:30:22.681 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:30:22.682 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:30:22.682 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:30:22.683 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:30:22.683 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:30:22.683 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:30:22.683 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:30:22.685 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:30:22.685 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:30:22.686 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:30:22.686 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:30:22.686 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:30:22.686 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:30:22.686 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:30:22.686 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:30:22.687 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:30:22.688 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:30:22.688 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:30:22.688 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:30:22.689 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:30:22.689 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:30:22.689 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:30:22.689 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:30:22.689 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:30:22.689 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:30:22.692 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:30:22.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:30:22.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:30:22.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:30:22.692 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:30:22.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:30:22.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:30:22.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:30:22.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:30:22.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:30:22.692 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:30:22.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:30:22.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:30:22.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:30:22.693 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:30:22.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:30:22.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:30:22.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:30:22.693 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:30:22.693 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:30:22.693 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:30:22.693 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:30:22.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:30:22.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:30:22.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:30:22.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:30:22.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:30:22.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:30:22.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:30:22.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:30:22.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:30:22.694 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:30:22.694 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:30:22.694 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:30:22.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:30:22.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:30:22.694 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:30:22.694 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:30:22.694 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:30:22.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:30:22.694 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:30:22.694 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:30:22.694 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:30:22.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:30:22.694 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:30:22.694 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:30:22.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:30:22.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:30:22.698 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:30:23.176 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:30:23.227 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:30:23.229 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:30:23.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:30:23.231 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:30:23.254 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:23.254 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:23.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:30:23.269 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:23.269 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:23.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:30:23.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:30:23.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:23.273 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:30:23.273 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:30:23.273 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:30:23.273 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:30:23.313 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:30:23.314 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:30:23.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:23.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:23.647 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:30:23.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:30:23.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:30:23.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:30:23.697 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:30:24.119 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:30:24.593 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:30:24.698 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:30:24.698 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:30:24.698 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:30:24.698 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:30:25.065 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:30:25.538 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:30:25.698 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:30:25.699 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:30:25.699 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:30:25.699 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:30:26.011 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:30:26.483 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:30:26.699 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:30:26.700 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:30:26.700 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:30:26.700 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:30:26.955 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:30:27.426 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:30:27.701 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:30:27.701 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:30:27.701 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:30:27.702 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:30:27.897 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:30:28.368 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:30:28.841 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:30:29.314 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:30:29.786 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:30:30.259 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:30:30.732 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:30:31.204 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:30:31.675 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:30:32.149 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:30:32.621 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:30:33.094 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:30:33.565 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:30:34.038 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:30:34.511 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:30:34.983 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:30:35.454 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:30:35.925 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:30:36.398 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:30:36.871 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:30:37.343 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:30:37.817 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:30:38.289 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:30:38.762 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:30:39.233 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:30:39.706 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:30:40.179 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:30:40.651 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:30:41.122 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:30:41.592 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:30:42.064 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:30:42.537 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:30:43.010 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:30:43.482 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 02:30:43.953 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 02:30:44.426 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 02:30:44.899 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 02:30:45.371 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 02:30:45.845 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 02:30:46.317 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 02:30:46.790 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 02:30:47.261 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 02:30:47.734 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 02:30:48.207 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 02:30:48.679 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 02:30:49.152 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 02:30:49.625 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 02:30:50.097 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 02:30:50.568 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 02:30:51.039 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 02:30:51.510 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 02:30:51.983 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 02:30:52.456 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 02:30:52.928 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 02:30:53.402 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 02:30:53.874 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 02:30:54.347 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 02:30:54.820 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 02:30:55.293 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 02:30:55.765 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 02:30:56.236 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 02:30:56.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:56.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:30:56.300 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:56.300 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:56.316 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:56.316 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:56.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:30:56.322 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:30:56.322 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:30:56.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:30:56.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:30:56.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:56.323 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:30:56.323 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:30:56.323 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:30:56.323 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:30:56.372 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:30:56.372 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:30:56.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:56.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:30:56.707 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 02:30:57.180 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 02:30:57.652 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-06 02:30:58.125 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-06 02:30:58.596 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-06 02:30:59.066 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-06 02:30:59.537 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-06 02:31:00.008 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-06 02:31:00.479 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-06 02:31:00.952 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-06 02:31:01.424 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-06 02:31:01.897 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-06 02:31:02.370 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-06 02:31:02.843 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-06 02:31:03.315 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-06 02:31:03.786 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-06 02:31:04.259 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-06 02:31:04.732 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-06 02:31:05.204 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-06 02:31:05.678 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-06 02:31:06.150 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-06 02:31:06.622 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-06 02:31:07.093 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-06 02:31:07.567 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-06 02:31:08.039 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-06 02:31:08.511 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-06 02:31:08.982 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-06 02:31:09.456 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-06 02:31:09.928 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-06 02:31:10.400 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-06 02:31:10.871 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-06 02:31:11.344 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-06 02:31:11.817 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-06 02:31:12.289 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-06 02:31:12.760 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-06 02:31:13.233 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-06 02:31:13.706 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-06 02:31:14.178 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-06 02:31:14.652 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-06 02:31:15.124 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-06 02:31:15.597 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-06 02:31:16.068 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-06 02:31:16.541 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-06 02:31:17.013 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-06 02:31:17.485 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-06 02:31:17.956 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-06 02:31:18.427 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-06 02:31:18.901 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-06 02:31:19.373 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-06 02:31:19.846 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-06 02:31:20.317 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-06 02:31:20.790 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-06 02:31:21.262 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-06 02:31:21.735 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-06 02:31:22.205 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-06 02:31:22.679 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-06 02:31:23.152 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-06 02:31:23.624 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-06 02:31:24.095 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-06 02:31:24.568 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-06 02:31:25.040 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-06 02:31:25.512 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-06 02:31:25.984 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-06 02:31:26.457 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-06 02:31:26.929 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-06 02:31:27.401 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-06 02:31:27.872 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-06 02:31:28.343 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-06 02:31:28.814 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-06 02:31:29.285 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-06 02:31:29.755 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-06 02:31:29.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:31:29.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:31:29.909 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:31:29.909 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:31:29.921 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:31:29.922 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:31:29.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:31:29.926 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:31:29.927 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:31:29.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:31:29.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:31:29.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:31:29.928 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:31:29.928 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:31:29.928 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:31:29.928 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:31:29.935 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:31:29.935 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:31:29.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:31:29.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:31:30.226 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-06 02:31:30.699 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-06 02:31:31.172 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-06 02:31:31.644 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-06 02:31:32.115 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-06 02:31:32.588 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-06 02:31:33.061 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-06 02:31:33.533 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-06 02:31:34.004 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-06 02:31:34.477 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-06 02:31:34.950 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-06 02:31:35.422 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-06 02:31:35.893 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-06 02:31:36.366 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-06 02:31:36.839 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-06 02:31:37.311 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-06 02:31:37.782 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-06 02:31:38.255 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-06 02:31:38.727 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-06 02:31:39.199 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-06 02:31:39.670 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-06 02:31:40.141 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-06 02:31:40.612 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-06 02:31:41.085 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-06 02:31:41.558 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-06 02:31:42.030 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-06 02:31:42.501 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-06 02:31:42.971 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-06 02:31:43.442 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-06 02:31:43.913 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-06 02:31:44.386 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-06 02:31:44.859 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-06 02:31:45.331 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-06 02:31:45.802 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-06 02:31:46.275 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-06 02:31:46.748 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-06 02:31:47.220 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-06 02:31:47.691 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-06 02:31:48.162 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-06 02:31:48.632 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-03-06 02:31:49.106 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-03-06 02:31:49.578 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-03-06 02:31:50.050 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-03-06 02:31:50.524 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-03-06 02:31:50.996 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-03-06 02:31:51.468 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-03-06 02:31:51.939 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-03-06 02:31:52.412 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-03-06 02:31:52.885 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-03-06 02:31:53.357 [DEBUG] clck_gen.py:113 IND CLOCK 19584
2026-03-06 02:31:53.828 [DEBUG] clck_gen.py:113 IND CLOCK 19686
2026-03-06 02:31:54.302 [DEBUG] clck_gen.py:113 IND CLOCK 19788
2026-03-06 02:31:54.774 [DEBUG] clck_gen.py:113 IND CLOCK 19890
2026-03-06 02:31:55.246 [DEBUG] clck_gen.py:113 IND CLOCK 19992
2026-03-06 02:31:55.717 [DEBUG] clck_gen.py:113 IND CLOCK 20094
2026-03-06 02:31:56.190 [DEBUG] clck_gen.py:113 IND CLOCK 20196
2026-03-06 02:31:56.662 [DEBUG] clck_gen.py:113 IND CLOCK 20298
2026-03-06 02:31:57.135 [DEBUG] clck_gen.py:113 IND CLOCK 20400
2026-03-06 02:31:57.605 [DEBUG] clck_gen.py:113 IND CLOCK 20502
2026-03-06 02:31:58.076 [DEBUG] clck_gen.py:113 IND CLOCK 20604
2026-03-06 02:31:58.547 [DEBUG] clck_gen.py:113 IND CLOCK 20706
2026-03-06 02:31:59.018 [DEBUG] clck_gen.py:113 IND CLOCK 20808
2026-03-06 02:31:59.491 [DEBUG] clck_gen.py:113 IND CLOCK 20910
2026-03-06 02:31:59.964 [DEBUG] clck_gen.py:113 IND CLOCK 21012
2026-03-06 02:32:00.436 [DEBUG] clck_gen.py:113 IND CLOCK 21114
2026-03-06 02:32:00.909 [DEBUG] clck_gen.py:113 IND CLOCK 21216
2026-03-06 02:32:01.382 [DEBUG] clck_gen.py:113 IND CLOCK 21318
2026-03-06 02:32:01.854 [DEBUG] clck_gen.py:113 IND CLOCK 21420
2026-03-06 02:32:02.325 [DEBUG] clck_gen.py:113 IND CLOCK 21522
2026-03-06 02:32:02.795 [DEBUG] clck_gen.py:113 IND CLOCK 21624
2026-03-06 02:32:03.269 [DEBUG] clck_gen.py:113 IND CLOCK 21726
2026-03-06 02:32:03.741 [DEBUG] clck_gen.py:113 IND CLOCK 21828
2026-03-06 02:32:04.213 [DEBUG] clck_gen.py:113 IND CLOCK 21930
2026-03-06 02:32:04.684 [DEBUG] clck_gen.py:113 IND CLOCK 22032
2026-03-06 02:32:05.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:32:05.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:32:05.042 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:32:05.042 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:32:05.051 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:32:05.051 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:32:05.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:32:05.057 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:32:05.057 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:32:05.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:32:05.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:32:05.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:32:05.058 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:32:05.058 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:32:05.058 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:32:05.058 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:32:05.102 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:32:05.102 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:32:05.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:32:05.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:32:05.156 [DEBUG] clck_gen.py:113 IND CLOCK 22134
2026-03-06 02:32:05.629 [DEBUG] clck_gen.py:113 IND CLOCK 22236
2026-03-06 02:32:06.101 [DEBUG] clck_gen.py:113 IND CLOCK 22338
2026-03-06 02:32:06.572 [DEBUG] clck_gen.py:113 IND CLOCK 22440
2026-03-06 02:32:07.046 [DEBUG] clck_gen.py:113 IND CLOCK 22542
2026-03-06 02:32:07.518 [DEBUG] clck_gen.py:113 IND CLOCK 22644
2026-03-06 02:32:07.990 [DEBUG] clck_gen.py:113 IND CLOCK 22746
2026-03-06 02:32:08.461 [DEBUG] clck_gen.py:113 IND CLOCK 22848
2026-03-06 02:32:08.934 [DEBUG] clck_gen.py:113 IND CLOCK 22950
2026-03-06 02:32:09.407 [DEBUG] clck_gen.py:113 IND CLOCK 23052
2026-03-06 02:32:09.879 [DEBUG] clck_gen.py:113 IND CLOCK 23154
2026-03-06 02:32:10.350 [DEBUG] clck_gen.py:113 IND CLOCK 23256
2026-03-06 02:32:10.823 [DEBUG] clck_gen.py:113 IND CLOCK 23358
2026-03-06 02:32:11.296 [DEBUG] clck_gen.py:113 IND CLOCK 23460
2026-03-06 02:32:11.767 [DEBUG] clck_gen.py:113 IND CLOCK 23562
2026-03-06 02:32:12.239 [DEBUG] clck_gen.py:113 IND CLOCK 23664
2026-03-06 02:32:12.712 [DEBUG] clck_gen.py:113 IND CLOCK 23766
2026-03-06 02:32:13.184 [DEBUG] clck_gen.py:113 IND CLOCK 23868
2026-03-06 02:32:13.656 [DEBUG] clck_gen.py:113 IND CLOCK 23970
2026-03-06 02:32:14.127 [DEBUG] clck_gen.py:113 IND CLOCK 24072
2026-03-06 02:32:14.601 [DEBUG] clck_gen.py:113 IND CLOCK 24174
2026-03-06 02:32:15.073 [DEBUG] clck_gen.py:113 IND CLOCK 24276
2026-03-06 02:32:15.545 [DEBUG] clck_gen.py:113 IND CLOCK 24378
2026-03-06 02:32:16.016 [DEBUG] clck_gen.py:113 IND CLOCK 24480
2026-03-06 02:32:16.489 [DEBUG] clck_gen.py:113 IND CLOCK 24582
2026-03-06 02:32:16.962 [DEBUG] clck_gen.py:113 IND CLOCK 24684
2026-03-06 02:32:17.434 [DEBUG] clck_gen.py:113 IND CLOCK 24786
2026-03-06 02:32:17.905 [DEBUG] clck_gen.py:113 IND CLOCK 24888
2026-03-06 02:32:18.378 [DEBUG] clck_gen.py:113 IND CLOCK 24990
2026-03-06 02:32:18.850 [DEBUG] clck_gen.py:113 IND CLOCK 25092
2026-03-06 02:32:19.322 [DEBUG] clck_gen.py:113 IND CLOCK 25194
2026-03-06 02:32:19.793 [DEBUG] clck_gen.py:113 IND CLOCK 25296
2026-03-06 02:32:20.266 [DEBUG] clck_gen.py:113 IND CLOCK 25398
2026-03-06 02:32:20.739 [DEBUG] clck_gen.py:113 IND CLOCK 25500
2026-03-06 02:32:21.211 [DEBUG] clck_gen.py:113 IND CLOCK 25602
2026-03-06 02:32:21.685 [DEBUG] clck_gen.py:113 IND CLOCK 25704
2026-03-06 02:32:22.157 [DEBUG] clck_gen.py:113 IND CLOCK 25806
2026-03-06 02:32:22.629 [DEBUG] clck_gen.py:113 IND CLOCK 25908
2026-03-06 02:32:23.101 [DEBUG] clck_gen.py:113 IND CLOCK 26010
2026-03-06 02:32:23.574 [DEBUG] clck_gen.py:113 IND CLOCK 26112
2026-03-06 02:32:24.046 [DEBUG] clck_gen.py:113 IND CLOCK 26214
2026-03-06 02:32:24.518 [DEBUG] clck_gen.py:113 IND CLOCK 26316
2026-03-06 02:32:24.989 [DEBUG] clck_gen.py:113 IND CLOCK 26418
2026-03-06 02:32:25.460 [DEBUG] clck_gen.py:113 IND CLOCK 26520
2026-03-06 02:32:25.931 [DEBUG] clck_gen.py:113 IND CLOCK 26622
2026-03-06 02:32:26.404 [DEBUG] clck_gen.py:113 IND CLOCK 26724
2026-03-06 02:32:26.877 [DEBUG] clck_gen.py:113 IND CLOCK 26826
2026-03-06 02:32:27.349 [DEBUG] clck_gen.py:113 IND CLOCK 26928
2026-03-06 02:32:27.820 [DEBUG] clck_gen.py:113 IND CLOCK 27030
2026-03-06 02:32:28.290 [DEBUG] clck_gen.py:113 IND CLOCK 27132
2026-03-06 02:32:28.761 [DEBUG] clck_gen.py:113 IND CLOCK 27234
2026-03-06 02:32:29.235 [DEBUG] clck_gen.py:113 IND CLOCK 27336
2026-03-06 02:32:29.707 [DEBUG] clck_gen.py:113 IND CLOCK 27438
2026-03-06 02:32:30.179 [DEBUG] clck_gen.py:113 IND CLOCK 27540
2026-03-06 02:32:30.650 [DEBUG] clck_gen.py:113 IND CLOCK 27642
2026-03-06 02:32:31.123 [DEBUG] clck_gen.py:113 IND CLOCK 27744
2026-03-06 02:32:31.596 [DEBUG] clck_gen.py:113 IND CLOCK 27846
2026-03-06 02:32:32.067 [DEBUG] clck_gen.py:113 IND CLOCK 27948
2026-03-06 02:32:32.539 [DEBUG] clck_gen.py:113 IND CLOCK 28050
2026-03-06 02:32:33.012 [DEBUG] clck_gen.py:113 IND CLOCK 28152
2026-03-06 02:32:33.485 [DEBUG] clck_gen.py:113 IND CLOCK 28254
2026-03-06 02:32:33.957 [DEBUG] clck_gen.py:113 IND CLOCK 28356
2026-03-06 02:32:34.428 [DEBUG] clck_gen.py:113 IND CLOCK 28458
2026-03-06 02:32:34.901 [DEBUG] clck_gen.py:113 IND CLOCK 28560
2026-03-06 02:32:35.373 [DEBUG] clck_gen.py:113 IND CLOCK 28662
2026-03-06 02:32:35.845 [DEBUG] clck_gen.py:113 IND CLOCK 28764
2026-03-06 02:32:36.316 [DEBUG] clck_gen.py:113 IND CLOCK 28866
2026-03-06 02:32:36.790 [DEBUG] clck_gen.py:113 IND CLOCK 28968
2026-03-06 02:32:37.262 [DEBUG] clck_gen.py:113 IND CLOCK 29070
2026-03-06 02:32:37.734 [DEBUG] clck_gen.py:113 IND CLOCK 29172
2026-03-06 02:32:38.205 [DEBUG] clck_gen.py:113 IND CLOCK 29274
2026-03-06 02:32:38.679 [DEBUG] clck_gen.py:113 IND CLOCK 29376
2026-03-06 02:32:39.151 [DEBUG] clck_gen.py:113 IND CLOCK 29478
2026-03-06 02:32:39.623 [DEBUG] clck_gen.py:113 IND CLOCK 29580
2026-03-06 02:32:40.094 [DEBUG] clck_gen.py:113 IND CLOCK 29682
2026-03-06 02:32:40.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:32:40.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:32:40.384 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:32:40.384 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:32:40.392 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:32:40.392 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:32:40.392 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:32:40.392 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:32:40.392 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:32:40.392 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:32:40.392 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:32:40.392 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:32:40.392 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:32:40.392 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:32:40.393 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:32:45.398 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:32:45.398 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:32:45.398 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:32:45.398 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:32:45.398 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:32:45.398 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:32:45.403 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:32:45.404 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:32:45.404 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:32:45.404 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:32:45.404 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:32:45.406 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:32:45.407 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:32:45.407 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:32:45.407 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:32:45.407 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:32:45.407 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:32:45.407 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:32:45.407 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:32:45.408 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:32:45.409 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:32:45.410 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:32:45.410 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:32:45.410 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:32:45.410 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:32:45.410 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:32:45.410 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:32:45.410 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:32:45.410 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:32:45.412 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:32:45.412 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:32:45.412 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:32:45.412 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:32:45.412 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:32:45.412 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:32:45.412 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:32:45.412 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:32:45.412 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:32:45.416 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:32:45.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:32:45.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:32:45.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:32:45.416 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:32:45.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:32:45.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:32:45.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:32:45.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:32:45.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:32:45.416 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:32:45.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:32:45.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:32:45.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:32:45.416 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:32:45.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:32:45.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:32:45.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:32:45.416 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:32:45.416 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:32:45.416 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:32:45.417 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:32:45.417 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:32:45.417 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:32:45.417 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:32:45.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:32:45.417 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:32:45.417 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:32:45.417 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:32:45.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:32:45.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:32:45.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:32:45.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:32:45.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:32:45.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:32:45.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:32:45.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:32:45.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:32:45.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:32:45.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:32:45.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:32:45.418 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:32:45.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:32:45.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:32:45.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:32:45.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:32:45.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:32:45.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:32:45.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:32:45.419 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:32:45.419 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:32:45.419 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:32:45.419 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:32:45.419 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:32:45.419 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:32:50.427 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:32:50.427 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:32:50.427 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:32:50.427 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:32:50.427 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:32:50.427 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:32:50.434 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:32:50.435 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:32:50.435 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:32:50.435 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:32:50.435 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:32:50.437 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:32:50.437 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:32:50.438 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:32:50.438 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:32:50.438 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:32:50.438 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:32:50.439 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:32:50.439 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:32:50.439 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:32:50.440 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:32:50.440 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:32:50.440 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:32:50.440 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:32:50.440 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:32:50.440 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:32:50.440 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:32:50.440 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:32:50.440 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:32:50.442 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:32:50.442 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:32:50.442 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:32:50.442 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:32:50.442 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:32:50.442 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:32:50.442 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:32:50.442 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:32:50.442 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:32:50.445 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:32:50.445 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:32:50.445 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:32:50.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:32:50.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:32:50.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:32:50.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:32:50.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:32:50.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:32:50.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:32:50.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:32:50.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:32:50.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:32:50.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:32:50.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:32:50.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:32:50.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:32:50.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:32:50.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:32:50.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:32:50.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:32:50.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:32:50.450 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:32:50.927 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:32:50.959 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:32:50.960 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:32:50.960 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:32:50.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:32:50.971 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:32:50.971 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:32:50.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:32:50.990 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:32:50.990 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:32:50.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:32:50.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:32:51.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:32:51.000 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:32:51.000 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:32:51.000 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:32:51.000 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:32:51.019 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:32:51.019 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:32:51.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:32:51.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:32:51.399 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:32:51.448 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:32:51.448 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:32:51.448 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:32:51.448 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:32:51.871 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:32:52.342 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:32:52.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:32:52.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:32:52.449 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:32:52.449 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:32:52.450 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:32:52.450 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:32:52.450 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:32:52.450 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:32:52.462 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:32:52.462 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:32:52.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:32:52.468 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:32:52.469 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:32:52.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:32:52.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:32:52.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:32:52.470 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:32:52.470 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:32:52.470 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:32:52.470 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:32:52.475 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:32:52.475 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:32:52.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:32:52.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:32:52.814 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:32:53.287 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:32:53.450 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:32:53.450 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:32:53.451 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:32:53.451 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:32:53.760 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:32:54.233 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:32:54.451 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:32:54.451 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:32:54.452 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:32:54.452 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:32:54.706 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:32:54.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:32:54.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:32:54.779 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:32:54.779 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:32:54.797 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:32:54.798 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:32:54.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:32:54.803 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:32:54.803 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:32:54.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:32:54.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:32:54.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:32:54.805 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:32:54.805 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:32:54.805 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:32:54.805 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:32:54.844 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:32:54.844 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:32:54.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:32:54.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:32:55.177 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:32:55.453 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:32:55.453 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:32:55.453 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:32:55.453 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:32:55.649 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:32:56.122 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:32:56.594 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:32:57.066 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:32:57.537 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:32:58.008 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:32:58.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:32:58.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:32:58.168 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:32:58.168 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:32:58.178 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:32:58.178 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:32:58.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:32:58.183 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:32:58.183 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:32:58.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:32:58.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:32:58.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:32:58.185 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:32:58.185 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:32:58.185 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:32:58.185 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:32:58.187 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:32:58.187 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:32:58.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:32:58.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:32:58.478 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:32:58.950 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:32:59.420 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:32:59.891 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:33:00.364 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:33:00.837 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:33:01.309 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:33:01.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:33:01.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:33:01.630 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:33:01.630 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:33:01.642 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:33:01.643 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:33:01.643 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:33:01.643 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:33:01.645 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:33:01.645 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:33:01.645 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:33:01.645 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:33:01.645 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:33:01.645 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:33:01.645 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:33:01.645 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2421 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:33:01.645 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2421 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:33:01.645 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2421 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:33:01.645 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2421 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:33:01.645 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2421 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:33:01.645 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2421 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:33:06.651 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:33:06.651 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:33:06.651 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:33:06.651 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:33:06.651 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:33:06.651 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:33:06.654 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:33:06.654 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:33:06.654 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:33:06.654 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:33:06.654 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:33:06.655 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:33:06.655 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:33:06.655 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:33:06.655 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:33:06.655 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:33:06.656 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:33:06.656 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:33:06.656 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:33:06.656 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:33:06.656 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:33:06.656 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:33:06.656 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:33:06.656 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:33:06.656 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:33:06.656 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:33:06.657 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:33:06.657 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:33:06.657 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:33:06.658 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:33:06.658 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:33:06.658 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:33:06.658 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:33:06.658 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:33:06.658 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:33:06.658 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:33:06.658 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:33:06.658 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:33:06.660 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:33:06.660 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:33:06.660 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:33:06.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:33:06.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:33:06.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:33:06.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:33:06.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:33:06.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:33:06.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:33:06.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:33:06.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:33:06.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:33:06.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:33:06.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:33:06.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:33:06.665 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:33:07.143 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:33:07.182 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:33:07.186 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:33:07.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:33:07.188 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:33:07.208 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:33:07.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:33:07.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:33:07.225 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:33:07.225 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:33:07.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:33:07.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:33:07.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:33:07.232 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:33:07.233 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:33:07.233 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:33:07.233 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:33:07.281 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:33:07.282 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:33:07.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:33:07.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:33:07.615 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:33:07.664 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:33:07.664 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:33:07.664 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:33:07.664 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:33:08.087 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:33:08.558 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:33:08.665 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:33:08.665 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:33:08.665 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:33:08.666 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:33:09.031 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:33:09.503 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:33:09.666 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:33:09.667 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:33:09.667 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:33:09.667 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:33:09.976 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:33:10.450 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:33:10.667 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:33:10.668 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:33:10.668 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:33:10.668 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:33:10.922 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:33:11.394 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:33:11.668 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:33:11.668 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:33:11.669 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:33:11.669 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:33:11.865 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:33:12.339 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:33:12.812 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:33:13.284 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:33:13.757 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:33:14.230 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:33:14.703 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:33:15.176 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:33:15.649 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:33:16.121 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:33:16.592 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:33:17.063 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:33:17.533 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:33:18.007 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:33:18.479 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:33:18.952 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:33:19.425 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:33:19.898 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:33:20.371 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:33:20.841 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:33:21.315 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:33:21.788 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:33:22.260 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:33:22.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:33:22.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:33:22.558 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:33:22.558 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:33:22.576 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:33:22.576 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:33:22.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:33:22.582 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:33:22.582 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:33:22.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:33:22.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:33:22.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:33:22.584 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:33:22.584 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:33:22.584 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:33:22.584 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:33:22.631 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:33:22.632 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:33:22.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:33:22.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:33:22.730 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:33:23.201 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:33:23.672 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:33:24.146 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:33:24.618 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:33:25.091 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:33:25.561 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:33:26.035 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:33:26.507 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:33:26.980 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:33:27.453 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 02:33:27.926 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 02:33:28.402 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 02:33:28.875 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 02:33:29.346 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 02:33:29.816 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 02:33:30.287 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 02:33:30.758 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 02:33:31.229 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 02:33:31.702 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 02:33:32.174 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 02:33:32.647 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 02:33:33.120 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 02:33:33.593 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 02:33:34.065 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 02:33:34.539 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 02:33:35.011 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 02:33:35.483 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 02:33:35.954 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 02:33:36.425 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 02:33:36.896 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 02:33:37.367 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 02:33:37.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:33:37.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:33:37.719 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:33:37.719 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:33:37.738 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:33:37.738 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:33:37.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:33:37.744 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:33:37.744 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:33:37.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:33:37.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:33:37.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:33:37.745 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:33:37.745 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:33:37.745 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:33:37.745 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:33:37.785 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:33:37.785 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:33:37.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:33:37.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:33:37.837 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 02:33:38.310 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 02:33:38.783 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 02:33:39.255 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 02:33:39.726 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 02:33:40.197 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 02:33:40.668 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 02:33:41.141 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 02:33:41.613 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-06 02:33:42.086 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-06 02:33:42.559 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-06 02:33:43.031 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-06 02:33:43.504 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-06 02:33:43.977 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-06 02:33:44.449 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-06 02:33:44.921 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-06 02:33:45.392 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-06 02:33:45.866 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-06 02:33:46.338 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-06 02:33:46.810 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-06 02:33:47.284 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-06 02:33:47.756 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-06 02:33:48.229 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-06 02:33:48.699 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-06 02:33:49.173 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-06 02:33:49.645 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-06 02:33:50.117 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-06 02:33:50.588 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-06 02:33:51.062 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-06 02:33:51.534 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-06 02:33:51.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:33:51.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:33:51.976 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:33:51.976 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:33:51.995 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:33:51.995 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:33:51.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:33:52.000 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:33:52.000 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:33:52.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:33:52.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:33:52.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:33:52.002 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:33:52.002 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:33:52.002 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:33:52.002 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:33:52.006 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-06 02:33:52.051 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:33:52.051 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:33:52.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:33:52.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:33:52.477 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-06 02:33:52.951 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-06 02:33:53.423 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-06 02:33:53.895 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-06 02:33:54.366 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-06 02:33:54.837 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-06 02:33:55.308 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-06 02:33:55.781 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-06 02:33:56.253 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-06 02:33:56.725 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-06 02:33:57.196 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-06 02:33:57.670 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-06 02:33:58.142 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-06 02:33:58.614 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-06 02:33:59.085 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-06 02:33:59.558 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-06 02:34:00.030 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-06 02:34:00.502 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-06 02:34:00.973 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-06 02:34:01.447 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-06 02:34:01.919 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-06 02:34:02.391 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-06 02:34:02.862 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-06 02:34:03.335 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-06 02:34:03.808 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-06 02:34:04.280 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-06 02:34:04.751 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-06 02:34:05.222 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-06 02:34:05.695 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-06 02:34:06.167 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-06 02:34:06.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:06.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:34:06.564 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:34:06.564 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:34:06.579 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:34:06.579 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:34:06.579 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:34:06.579 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:34:06.583 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:34:06.583 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:34:06.584 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:34:06.584 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:34:06.584 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:34:06.584 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:34:06.584 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:34:06.584 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=12944 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:34:06.585 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=12944 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:34:06.585 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=12944 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:34:06.585 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=12944 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:34:06.585 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=12944 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:34:06.585 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=12944 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:34:06.585 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=12944 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:34:11.583 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:34:11.583 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:34:11.583 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:34:11.584 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:34:11.584 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:34:11.584 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:34:11.591 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:34:11.592 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:34:11.592 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:34:11.592 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:34:11.592 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:34:11.595 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:34:11.595 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:34:11.595 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:34:11.595 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:34:11.596 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:34:11.596 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:34:11.596 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:34:11.597 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:34:11.597 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:34:11.598 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:34:11.598 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:34:11.598 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:34:11.598 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:34:11.598 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:34:11.598 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:34:11.598 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:34:11.598 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:34:11.599 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:34:11.600 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:34:11.601 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:34:11.601 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:34:11.601 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:34:11.601 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:34:11.601 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:34:11.601 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:34:11.601 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:34:11.601 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:34:11.604 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:34:11.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:34:11.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:34:11.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:34:11.604 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:34:11.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:34:11.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:34:11.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:34:11.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:34:11.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:34:11.604 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:34:11.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:34:11.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:34:11.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:34:11.604 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:34:11.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:34:11.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:34:11.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:34:11.604 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:34:11.605 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:34:11.605 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:34:11.605 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:34:11.605 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:34:11.605 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:34:11.605 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:34:11.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:34:11.605 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:34:11.605 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:34:11.605 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:34:11.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:34:11.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:34:11.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:34:11.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:34:11.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:34:11.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:34:11.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:34:11.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:34:11.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:34:11.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:34:11.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:34:11.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:34:11.606 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:34:11.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:34:11.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:34:11.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:34:11.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:34:11.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:34:11.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:34:11.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:34:11.606 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:34:11.606 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:34:11.606 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:34:11.606 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:34:11.606 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:34:11.606 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:34:16.613 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:34:16.613 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:34:16.613 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:34:16.613 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:34:16.613 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:34:16.614 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:34:16.621 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:34:16.622 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:34:16.622 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:34:16.622 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:34:16.622 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:34:16.624 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:34:16.625 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:34:16.625 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:34:16.625 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:34:16.625 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:34:16.626 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:34:16.626 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:34:16.626 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:34:16.626 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:34:16.627 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:34:16.627 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:34:16.627 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:34:16.627 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:34:16.627 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:34:16.627 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:34:16.627 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:34:16.627 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:34:16.627 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:34:16.629 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:34:16.629 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:34:16.629 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:34:16.629 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:34:16.629 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:34:16.629 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:34:16.629 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:34:16.629 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:34:16.629 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:34:16.632 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:34:16.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:34:16.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:34:16.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:34:16.632 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:34:16.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:34:16.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:34:16.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:34:16.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:34:16.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:34:16.632 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:34:16.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:34:16.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:34:16.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:34:16.632 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:34:16.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:34:16.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:34:16.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:34:16.632 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:34:16.632 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:34:16.632 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:34:16.632 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:34:16.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:34:16.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:34:16.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:34:16.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:34:16.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:34:16.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:34:16.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:34:16.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:34:16.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:34:16.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:34:16.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:34:16.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:34:16.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:34:16.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:34:16.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:34:16.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:34:16.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:34:16.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:34:16.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:34:16.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:34:16.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:34:16.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:34:16.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:34:16.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:34:16.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:34:16.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:34:16.637 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:34:17.115 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:34:17.163 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:34:17.166 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:34:17.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:34:17.169 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:34:17.189 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:34:17.190 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:34:17.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:34:17.213 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:34:17.213 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:34:17.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:34:17.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:34:17.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:17.222 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:34:17.223 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:34:17.223 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:34:17.223 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:34:17.253 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:34:17.253 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:34:17.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:17.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:17.587 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:34:17.635 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:34:17.635 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:34:17.635 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:34:17.635 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:34:18.061 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:34:18.533 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:34:18.636 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:34:18.636 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:34:18.637 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:34:18.637 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:34:19.006 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:34:19.477 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:34:19.637 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:34:19.638 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:34:19.638 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:34:19.638 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:34:19.950 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:34:20.423 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:34:20.638 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:34:20.638 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:34:20.639 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:34:20.639 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:34:20.895 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:34:21.366 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:34:21.640 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:34:21.640 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:34:21.640 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:34:21.640 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:34:21.837 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:34:22.307 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:34:22.778 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:34:23.251 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:34:23.724 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:34:24.196 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:34:24.667 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:34:25.141 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:34:25.613 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:34:26.085 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:34:26.556 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:34:27.027 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:34:27.498 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:34:27.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:27.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:34:27.705 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:34:27.705 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:34:27.723 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:34:27.723 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:34:27.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:34:27.728 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:34:27.728 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:34:27.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:34:27.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:34:27.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:27.730 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:34:27.730 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:34:27.730 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:34:27.730 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:34:27.778 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:34:27.778 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:34:27.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:27.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:27.968 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:34:28.439 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:34:28.913 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:34:29.385 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:34:29.857 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:34:30.328 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:34:30.802 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:34:31.274 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:34:31.746 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:34:32.217 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:34:32.691 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:34:33.164 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:34:33.636 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:34:34.107 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:34:34.578 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:34:35.051 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:34:35.524 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:34:35.996 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:34:36.470 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:34:36.942 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:34:37.413 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 02:34:37.887 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 02:34:38.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:38.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:34:38.054 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:34:38.055 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:34:38.074 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:34:38.074 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:34:38.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:34:38.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:34:38.080 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:34:38.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:34:38.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:34:38.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:38.082 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:34:38.082 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:34:38.082 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:34:38.082 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:34:38.117 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:34:38.117 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:34:38.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:38.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:38.358 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 02:34:38.830 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 02:34:39.301 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 02:34:39.772 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 02:34:40.246 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 02:34:40.718 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 02:34:41.190 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 02:34:41.661 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 02:34:42.134 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 02:34:42.606 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 02:34:43.079 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 02:34:43.549 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 02:34:44.022 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 02:34:44.495 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 02:34:44.967 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 02:34:45.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:45.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:34:45.010 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:34:45.010 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:34:45.019 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:34:45.019 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:34:45.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:34:45.024 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:34:45.024 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:34:45.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:34:45.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:34:45.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:45.026 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:34:45.026 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:34:45.026 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:34:45.026 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:34:45.057 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:34:45.058 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:34:45.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:45.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:45.438 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 02:34:45.909 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 02:34:46.382 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 02:34:46.854 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 02:34:47.326 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 02:34:47.800 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 02:34:48.272 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 02:34:48.744 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 02:34:49.215 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 02:34:49.689 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 02:34:50.161 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 02:34:50.633 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 02:34:51.104 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 02:34:51.578 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-06 02:34:52.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:52.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:34:52.043 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:34:52.043 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:34:52.050 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-06 02:34:52.056 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:34:52.057 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:34:52.057 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:34:52.057 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:34:52.060 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:34:52.060 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:34:52.060 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:34:52.060 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:34:52.060 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:34:52.060 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:34:52.060 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:34:52.060 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7654 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:34:52.060 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7654 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:34:52.060 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7654 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:34:52.060 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7654 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:34:52.060 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7654 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:34:52.060 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7654 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:34:57.065 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:34:57.065 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:34:57.065 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:34:57.065 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:34:57.065 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:34:57.065 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:34:57.076 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:34:57.077 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:34:57.077 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:34:57.077 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:34:57.077 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:34:57.080 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:34:57.080 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:34:57.080 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:34:57.080 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:34:57.081 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:34:57.081 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:34:57.081 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:34:57.081 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:34:57.082 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:34:57.082 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:34:57.083 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:34:57.083 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:34:57.083 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:34:57.083 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:34:57.083 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:34:57.083 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:34:57.083 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:34:57.083 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:34:57.087 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:34:57.087 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:34:57.087 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:34:57.087 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:34:57.087 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:34:57.087 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:34:57.087 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:34:57.087 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:34:57.087 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:34:57.090 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:34:57.090 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:34:57.090 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:34:57.090 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:34:57.090 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:34:57.091 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:34:57.091 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:34:57.091 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:34:57.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:34:57.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:34:57.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:34:57.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:34:57.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:34:57.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:34:57.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:34:57.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:34:57.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:34:57.096 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:34:57.572 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:34:57.619 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:34:57.621 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:34:57.623 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:34:57.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:34:57.645 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:34:57.645 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:34:57.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:34:57.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:34:57.661 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:34:57.661 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:34:57.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:34:57.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:57.664 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:34:57.664 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:34:57.664 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:34:57.664 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:34:57.710 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:34:57.710 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:34:57.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:57.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:58.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:58.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:34:58.032 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:34:58.032 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:34:58.044 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:34:58.051 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:34:58.051 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:34:58.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:34:58.057 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:34:58.057 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:34:58.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:34:58.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:34:58.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:58.058 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:34:58.058 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:34:58.058 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:34:58.058 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:34:58.087 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:34:58.088 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:34:58.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:58.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:58.094 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:34:58.094 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:34:58.095 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:34:58.095 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:34:58.515 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:34:58.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:58.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:34:58.573 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:34:58.573 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:34:58.587 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:34:58.587 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:34:58.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:34:58.593 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:34:58.593 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:34:58.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:34:58.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:34:58.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:58.594 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:34:58.594 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:34:58.594 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:34:58.594 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:34:58.602 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:34:58.602 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:34:58.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:58.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:58.986 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:34:59.095 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:34:59.095 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:34:59.096 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:34:59.096 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:34:59.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:59.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:34:59.380 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:34:59.381 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:34:59.390 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:34:59.390 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:34:59.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:34:59.395 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:34:59.395 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:34:59.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:34:59.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:34:59.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:59.396 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:34:59.396 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:34:59.396 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:34:59.396 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:34:59.400 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:34:59.401 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:34:59.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:59.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:34:59.457 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:34:59.931 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:35:00.096 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:35:00.096 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:35:00.097 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:35:00.097 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:35:00.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:00.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:00.253 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:00.253 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:00.259 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:35:00.259 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:35:00.259 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:35:00.259 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:35:00.260 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:35:00.260 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:35:00.260 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:35:00.260 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:35:00.260 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:35:00.260 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:35:00.260 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:35:05.266 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:35:05.266 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:35:05.266 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:35:05.266 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:35:05.266 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:35:05.266 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:35:05.269 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:35:05.270 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:35:05.270 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:35:05.270 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:35:05.270 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:35:05.271 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:35:05.271 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:35:05.271 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:35:05.271 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:35:05.271 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:35:05.271 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:35:05.271 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:35:05.271 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:35:05.271 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:35:05.272 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:35:05.272 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:35:05.272 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:35:05.272 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:35:05.272 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:35:05.272 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:35:05.272 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:35:05.272 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:35:05.272 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:35:05.273 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:35:05.273 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:35:05.273 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:35:05.273 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:35:05.273 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:35:05.273 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:35:05.273 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:35:05.273 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:35:05.273 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:35:05.275 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:35:05.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:35:05.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:35:05.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:35:05.275 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:35:05.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:35:05.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:35:05.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:35:05.276 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:35:05.276 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:35:05.276 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:35:05.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:35:05.280 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:35:05.756 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:35:05.800 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:35:05.801 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:35:05.803 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:35:05.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:05.818 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:05.818 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:05.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:35:05.832 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:05.832 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:05.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:35:05.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:05.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:05.855 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:35:05.855 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:35:05.856 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:35:05.856 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:35:05.895 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:35:05.895 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:35:05.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:05.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:06.228 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:35:06.279 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:35:06.279 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:35:06.279 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:35:06.280 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:35:06.700 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:35:07.171 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:35:07.280 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:35:07.281 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:35:07.281 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:35:07.281 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:35:07.645 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:35:08.117 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:35:08.281 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:35:08.282 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:35:08.282 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:35:08.282 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:35:08.590 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:35:09.064 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:35:09.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:09.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:09.127 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:09.127 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:09.141 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:09.141 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:09.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:35:09.147 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:09.147 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:09.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:35:09.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:09.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:09.149 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:35:09.149 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:35:09.149 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:35:09.149 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:35:09.152 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:35:09.152 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:35:09.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:09.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:09.282 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:35:09.282 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:35:09.282 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:35:09.283 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:35:09.536 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:35:10.007 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:35:10.283 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:35:10.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:35:10.284 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:35:10.284 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:35:10.477 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:35:10.948 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:35:11.421 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:35:11.894 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:35:12.366 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:35:12.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:12.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:12.493 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:12.493 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:12.511 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:12.512 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:12.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:35:12.517 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:12.517 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:12.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:35:12.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:12.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:12.519 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:35:12.519 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:35:12.519 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:35:12.519 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:35:12.548 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:35:12.549 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:35:12.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:12.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:12.837 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:35:13.308 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:35:13.782 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:35:14.254 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:35:14.726 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:35:15.197 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:35:15.670 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:35:16.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:16.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:16.062 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:16.062 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:16.081 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:16.081 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:16.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:35:16.086 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:16.086 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:16.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:35:16.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:16.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:16.088 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:35:16.088 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:35:16.088 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:35:16.088 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:35:16.136 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:35:16.137 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:35:16.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:16.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:16.142 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:35:16.614 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:35:17.085 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:35:17.559 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:35:18.031 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:35:18.503 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:35:18.974 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:35:19.445 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:35:19.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:19.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:19.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:19.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:19.783 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:35:19.783 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:35:19.783 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:35:19.783 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:35:19.785 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:35:19.785 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:35:19.785 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:35:19.785 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:35:19.785 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:35:19.785 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:35:19.785 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:35:24.789 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:35:24.789 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:35:24.789 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:35:24.789 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:35:24.789 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:35:24.789 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:35:24.793 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:35:24.793 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:35:24.793 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:35:24.794 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:35:24.794 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:35:24.796 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:35:24.796 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:35:24.796 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:35:24.796 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:35:24.796 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:35:24.796 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:35:24.797 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:35:24.797 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:35:24.797 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:35:24.798 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:35:24.798 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:35:24.798 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:35:24.799 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:35:24.799 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:35:24.799 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:35:24.799 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:35:24.799 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:35:24.799 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:35:24.801 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:35:24.801 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:35:24.801 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:35:24.801 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:35:24.801 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:35:24.801 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:35:24.801 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:35:24.801 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:35:24.801 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:35:24.804 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:35:24.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:35:24.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:35:24.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:35:24.804 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:35:24.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:35:24.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:35:24.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:35:24.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:35:24.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:35:24.804 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:35:24.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:35:24.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:35:24.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:35:24.805 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:35:24.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:35:24.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:35:24.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:35:24.805 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:35:24.805 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:35:24.805 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:35:24.805 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:35:24.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:35:24.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:35:24.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:35:24.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:35:24.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:35:24.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:35:24.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:35:24.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:35:24.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:35:24.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:35:24.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:35:24.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:35:24.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:35:24.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:35:24.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:35:24.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:35:24.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:35:24.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:35:24.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:35:24.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:35:24.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:35:24.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:35:24.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:35:24.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:35:24.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:35:24.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:35:24.809 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:35:25.288 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:35:25.332 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:35:25.335 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:35:25.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:25.338 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:35:25.363 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:25.363 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:25.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:35:25.377 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:25.377 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:25.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:35:25.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:25.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:25.385 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:35:25.385 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:35:25.385 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:35:25.385 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:35:25.426 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:35:25.426 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:35:25.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:25.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:25.759 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:35:25.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:25.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:25.804 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:25.804 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:25.808 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:35:25.808 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:35:25.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:35:25.809 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:35:25.823 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:25.823 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:25.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:35:25.829 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:25.829 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:25.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:35:25.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:25.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:25.831 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:35:25.831 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:35:25.831 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:35:25.831 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:35:25.844 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:35:25.845 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:35:25.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:25.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:26.231 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:35:26.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:26.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:26.412 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:26.412 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:26.431 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:26.431 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:26.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:35:26.436 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:26.437 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:26.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:35:26.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:26.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:26.438 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:35:26.438 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:35:26.438 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:35:26.438 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:35:26.465 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:35:26.465 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:35:26.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:26.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:26.703 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:35:26.809 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:35:26.809 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:35:26.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:35:26.809 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:35:27.173 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:35:27.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:27.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:27.567 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:27.567 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:27.586 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:27.586 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:27.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:35:27.592 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:27.592 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:27.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:35:27.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:27.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:27.593 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:35:27.593 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:35:27.593 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:35:27.593 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:35:27.642 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:35:27.643 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:35:27.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:27.644 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:35:27.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:27.810 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:35:27.810 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:35:27.810 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:35:27.810 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:35:28.115 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:35:28.589 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:35:28.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:28.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:28.672 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:28.672 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:28.684 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:35:28.684 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:35:28.685 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:35:28.685 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:35:28.686 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:35:28.686 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:35:28.686 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:35:28.686 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:35:28.686 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:35:28.686 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:35:28.686 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:35:28.686 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=839 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:35:28.686 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=840 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:35:28.686 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=840 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:35:28.686 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=840 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:35:28.686 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=840 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:35:28.686 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=840 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:35:28.686 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=840 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:35:28.686 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=840 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:35:28.686 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=840 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:35:33.691 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:35:33.691 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:35:33.691 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:35:33.691 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:35:33.691 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:35:33.691 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:35:33.698 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:35:33.698 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:35:33.698 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:35:33.699 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:35:33.699 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:35:33.704 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:35:33.705 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:35:33.705 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:35:33.705 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:35:33.705 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:35:33.705 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:35:33.706 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:35:33.706 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:35:33.706 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:35:33.710 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:35:33.710 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:35:33.710 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:35:33.710 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:35:33.710 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:35:33.711 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:35:33.711 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:35:33.711 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:35:33.711 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:35:33.713 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:35:33.713 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:35:33.713 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:35:33.714 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:35:33.714 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:35:33.714 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:35:33.714 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:35:33.714 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:35:33.714 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:35:33.717 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:35:33.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:35:33.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:35:33.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:35:33.718 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:35:33.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:35:33.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:35:33.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:35:33.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:35:33.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:35:33.718 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:35:33.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:35:33.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:35:33.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:35:33.718 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:35:33.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:35:33.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:35:33.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:35:33.718 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:35:33.718 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:35:33.718 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:35:33.718 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:35:33.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:35:33.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:35:33.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:35:33.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:35:33.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:35:33.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:35:33.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:35:33.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:35:33.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:35:33.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:35:33.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:35:33.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:35:33.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:35:33.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:35:33.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:35:33.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:35:33.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:35:33.720 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:35:33.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:35:33.720 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:35:33.720 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:35:33.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:35:33.720 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:35:33.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:35:33.720 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:35:33.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:35:33.723 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:35:34.201 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:35:34.245 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:35:34.246 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:35:34.248 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:35:34.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:34.261 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:34.261 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:34.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:35:34.283 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:34.283 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:34.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:35:34.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:34.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:34.291 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:35:34.291 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:35:34.291 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:35:34.291 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:35:34.340 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:35:34.341 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:35:34.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:34.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:34.674 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:35:34.723 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:35:34.723 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:35:34.723 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:35:34.723 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:35:35.145 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:35:35.616 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:35:35.724 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:35:35.724 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:35:35.725 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:35:35.725 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:35:36.086 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:35:36.560 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:35:36.726 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:35:36.726 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:35:36.726 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:35:36.726 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:35:37.032 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:35:37.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:37.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:37.188 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:37.188 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:37.208 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:37.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:37.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:35:37.215 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:37.215 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:37.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:35:37.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:37.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:37.216 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:35:37.216 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:35:37.216 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:35:37.216 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:35:37.267 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:35:37.268 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:35:37.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:37.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:37.504 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:35:37.726 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:35:37.727 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:35:37.727 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:35:37.727 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:35:37.975 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:35:38.446 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:35:38.727 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:35:38.728 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:35:38.728 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:35:38.728 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:35:38.917 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:35:39.388 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:35:39.861 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:35:40.333 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:35:40.806 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:35:41.279 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:35:41.752 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:35:41.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:41.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:41.820 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:41.820 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:41.838 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:41.838 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:41.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:35:41.845 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:41.845 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:41.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:35:41.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:41.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:41.846 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:35:41.846 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:35:41.846 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:35:41.846 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:35:41.889 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:35:41.889 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:35:41.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:41.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:42.223 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:35:42.695 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:35:43.165 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:35:43.638 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:35:44.111 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:35:44.583 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:35:45.054 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:35:45.528 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:35:46.000 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:35:46.472 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:35:46.946 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:35:47.418 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:35:47.890 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:35:48.361 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:35:48.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:48.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:48.520 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:48.521 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:48.531 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:48.531 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:48.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:35:48.537 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:48.537 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:48.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:35:48.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:48.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:48.539 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:35:48.539 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:35:48.539 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:35:48.539 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:35:48.540 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:35:48.540 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:35:48.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:48.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:48.831 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:35:49.303 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:35:49.773 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:35:50.244 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:35:50.717 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:35:51.190 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:35:51.662 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:35:52.133 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:35:52.606 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:35:53.079 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:35:53.551 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:35:54.022 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:35:54.495 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 02:35:54.968 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 02:35:55.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:35:55.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:35:55.290 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:35:55.290 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:35:55.306 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:35:55.306 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:35:55.307 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:35:55.307 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:35:55.308 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:35:55.308 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:35:55.308 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:35:55.309 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:35:55.309 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:35:55.309 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:35:55.309 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:36:00.311 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:36:00.311 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:36:00.311 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:36:00.311 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:36:00.311 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:36:00.311 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:36:00.318 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:36:00.319 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:36:00.319 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:00.319 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:36:00.319 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:36:00.320 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:36:00.320 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:36:00.320 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:36:00.320 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:00.320 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:36:00.320 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:36:00.320 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:36:00.320 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:36:00.320 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:00.322 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:36:00.322 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:36:00.322 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:36:00.322 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:00.322 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:36:00.322 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:36:00.322 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:36:00.322 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:36:00.322 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:00.324 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:36:00.324 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:36:00.324 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:36:00.324 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:00.324 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:36:00.324 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:36:00.324 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:36:00.324 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:36:00.324 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:00.326 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:36:00.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:36:00.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:36:00.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:36:00.326 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:36:00.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:36:00.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:36:00.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:00.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:36:00.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:36:00.326 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:36:00.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:00.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:00.326 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:00.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:00.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:00.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:00.326 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:36:00.326 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:36:00.326 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:36:00.326 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:36:00.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:00.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:00.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:00.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:36:00.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:00.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:00.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:00.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:00.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:00.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:00.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:00.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:00.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:00.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:00.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:00.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:00.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:00.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:00.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:00.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:00.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:00.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:00.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:00.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:00.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:00.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:00.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:00.331 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:36:00.807 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:36:00.847 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:36:00.848 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:36:00.850 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:36:00.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:00.869 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:36:00.869 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:36:00.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:36:00.894 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:36:00.894 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:36:00.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:36:00.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:00.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:36:00.902 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:36:00.902 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:36:00.902 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:36:00.902 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:36:00.945 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:36:00.946 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:36:00.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:36:00.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:36:01.280 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:36:01.330 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:01.330 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:01.331 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:01.331 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:01.751 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:36:02.225 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:36:02.332 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:02.332 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:02.332 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:02.332 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:02.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:36:02.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:02.690 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:36:02.691 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:36:02.697 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:36:02.710 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:36:02.710 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:36:02.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:36:02.717 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:36:02.717 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:36:02.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:36:02.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:02.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:36:02.719 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:36:02.719 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:36:02.719 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:36:02.719 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:36:02.742 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:36:02.742 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:36:02.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:36:02.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:36:03.169 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:36:03.333 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:03.333 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:03.333 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:03.333 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:03.640 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:36:04.114 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:36:04.334 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:04.334 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:04.334 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:04.335 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:04.586 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:36:05.059 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:36:05.335 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:05.336 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:05.336 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:05.336 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:05.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:36:05.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:05.500 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:36:05.500 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:36:05.518 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:36:05.518 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:36:05.518 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:36:05.524 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:36:05.524 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:36:05.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:36:05.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:05.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:36:05.526 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:36:05.526 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:36:05.526 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:36:05.526 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:36:05.529 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:36:05.573 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:36:05.574 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:36:05.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:36:05.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:36:06.000 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:36:06.471 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:36:06.944 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:36:07.417 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:36:07.889 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:36:08.360 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:36:08.833 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:36:09.306 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:36:09.777 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:36:09.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:36:09.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:09.938 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:36:09.938 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:36:09.957 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:36:09.957 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:36:09.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:36:09.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:36:09.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:36:09.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:36:09.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:09.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:36:09.967 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:36:09.967 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:36:09.967 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:36:09.967 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:36:10.013 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:36:10.013 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:36:10.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:36:10.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:36:10.248 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:36:10.719 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:36:11.190 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:36:11.661 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:36:12.134 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:36:12.607 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:36:13.079 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:36:13.550 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:36:14.023 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:36:14.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:36:14.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:14.341 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:36:14.342 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:36:14.353 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:14.354 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:14.354 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:14.354 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:14.356 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:36:14.356 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:36:14.356 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:36:14.356 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:36:14.356 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:36:14.356 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:36:14.356 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:36:14.356 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3033 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:36:14.356 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3033 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:36:14.356 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3033 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:36:14.356 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3033 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:36:14.356 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3033 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:36:14.356 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3033 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:36:19.361 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:36:19.361 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:36:19.361 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:36:19.361 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:36:19.361 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:36:19.361 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:36:19.368 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:36:19.370 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:36:19.370 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:19.370 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:36:19.371 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:36:19.374 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:36:19.375 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:36:19.375 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:36:19.375 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:19.376 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:36:19.376 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:36:19.376 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:36:19.376 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:36:19.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:19.379 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:36:19.379 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:36:19.380 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:36:19.380 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:19.380 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:36:19.380 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:36:19.381 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:36:19.381 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:36:19.381 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:19.383 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:36:19.383 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:36:19.383 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:36:19.384 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:19.384 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:36:19.384 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:36:19.384 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:36:19.384 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:36:19.384 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:19.389 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:36:19.389 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:36:19.389 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:36:19.389 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:36:19.389 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:36:19.389 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:36:19.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:36:19.390 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:19.390 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:36:19.390 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:36:19.390 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:36:19.390 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:19.390 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:19.390 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:19.390 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:19.390 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:19.390 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:19.390 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:19.390 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:36:19.390 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:36:19.390 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:36:19.390 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:36:19.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:19.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:19.391 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:19.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:36:19.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:19.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:19.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:19.391 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:19.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:19.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:19.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:19.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:19.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:19.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:19.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:19.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:19.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:19.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:19.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:19.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:19.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:19.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:19.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:19.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:19.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:19.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:19.395 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:36:19.871 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:36:19.922 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:36:19.924 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:36:19.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:19.926 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:36:19.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:19.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:20.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:20.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:20.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:20.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:20.341 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:36:20.396 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:20.396 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:20.397 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:20.397 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:20.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:20.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:20.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:20.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:20.812 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:36:20.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:20.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:20.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:20.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:21.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:21.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:21.265 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:21.265 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:21.265 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:21.265 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:21.266 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:36:21.266 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:36:21.266 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:36:21.266 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:36:21.266 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:36:21.266 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:36:21.266 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:36:26.274 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:36:26.274 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:36:26.274 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:36:26.274 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:36:26.274 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:36:26.274 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:36:26.281 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:36:26.282 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:36:26.282 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:26.282 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:36:26.282 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:36:26.285 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:36:26.285 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:36:26.286 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:36:26.286 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:26.286 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:36:26.287 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:36:26.287 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:36:26.287 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:36:26.288 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:26.290 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:36:26.290 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:36:26.290 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:36:26.291 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:26.291 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:36:26.291 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:36:26.291 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:36:26.292 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:36:26.292 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:26.294 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:36:26.294 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:36:26.295 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:36:26.295 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:26.295 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:36:26.295 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:36:26.295 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:36:26.295 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:36:26.295 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:26.300 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:36:26.300 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:36:26.300 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:36:26.300 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:36:26.300 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:36:26.300 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:36:26.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:36:26.300 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:26.300 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:36:26.300 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:36:26.300 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:36:26.300 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:26.300 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:26.300 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:26.300 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:26.300 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:26.300 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:26.300 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:26.300 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:36:26.300 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:36:26.300 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:36:26.301 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:36:26.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:26.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:26.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:26.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:36:26.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:26.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:26.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:26.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:26.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:26.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:26.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:26.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:26.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:26.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:26.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:26.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:26.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:26.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:26.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:26.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:26.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:26.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:26.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:26.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:26.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:26.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:26.305 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:36:26.781 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:36:26.828 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:36:26.830 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:36:26.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:26.832 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:36:26.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:26.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:26.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:26.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:27.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:27.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:27.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:27.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:27.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:27.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:27.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:27.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:27.250 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:36:27.303 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:27.304 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:27.305 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:27.305 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:27.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:27.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:27.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:27.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:27.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:27.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:27.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:27.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:27.724 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:36:27.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:27.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:27.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:27.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:27.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:27.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:27.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:27.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:28.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:28.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:28.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:28.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:28.160 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:28.160 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:28.160 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:28.160 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:28.161 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:36:28.161 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:36:28.161 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:36:28.161 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:36:28.161 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:36:28.161 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:36:28.161 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:36:33.169 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:36:33.169 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:36:33.169 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:36:33.169 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:36:33.169 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:36:33.169 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:36:33.183 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:36:33.184 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:36:33.184 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:33.184 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:36:33.184 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:36:33.186 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:36:33.186 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:36:33.187 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:36:33.187 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:33.187 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:36:33.187 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:36:33.187 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:36:33.187 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:36:33.187 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:33.188 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:36:33.188 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:36:33.188 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:36:33.188 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:33.189 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:36:33.189 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:36:33.189 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:36:33.189 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:36:33.189 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:33.190 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:36:33.190 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:36:33.190 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:36:33.190 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:33.190 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:36:33.190 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:36:33.190 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:36:33.190 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:36:33.190 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:33.192 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:36:33.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:36:33.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:36:33.192 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:36:33.192 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:36:33.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:36:33.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:36:33.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:36:33.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:33.192 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:36:33.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:33.192 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:36:33.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:33.192 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:33.192 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:33.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:33.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:33.192 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:33.192 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:36:33.192 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:36:33.192 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:36:33.192 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:33.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:33.197 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:36:33.673 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:36:33.716 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:36:33.718 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:36:33.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:33.719 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:36:33.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:33.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:34.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:34.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:34.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:34.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:34.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:34.144 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:36:34.196 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:34.196 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:34.197 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:34.197 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:34.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:34.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:34.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:34.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:34.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:34.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:34.616 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:36:34.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:34.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:34.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:34.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:34.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:34.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:35.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:35.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:35.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:35.077 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:35.077 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:35.077 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:35.077 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:35.078 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:36:35.078 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:36:35.078 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:36:35.078 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:36:35.078 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:36:35.078 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:36:35.078 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:36:35.078 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=408 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:36:35.078 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=408 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:36:35.078 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=408 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:36:35.078 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=408 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:36:35.078 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=408 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:36:35.078 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=408 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:36:40.085 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:36:40.085 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:36:40.085 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:36:40.085 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:36:40.085 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:36:40.085 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:36:40.109 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:36:40.111 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:36:40.111 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:40.112 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:36:40.112 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:36:40.120 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:36:40.120 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:36:40.121 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:36:40.121 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:40.121 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:36:40.122 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:36:40.123 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:36:40.123 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:36:40.123 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:40.126 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:36:40.126 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:36:40.127 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:36:40.127 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:40.127 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:36:40.128 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:36:40.128 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:36:40.128 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:36:40.129 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:40.130 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:36:40.131 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:36:40.131 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:36:40.131 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:40.131 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:36:40.131 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:36:40.131 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:36:40.131 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:36:40.131 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:40.135 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:36:40.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:36:40.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:36:40.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:36:40.136 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:36:40.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:36:40.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:36:40.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:40.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:36:40.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:36:40.136 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:36:40.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:40.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:40.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:40.136 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:40.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:40.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:40.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:40.136 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:36:40.136 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:36:40.136 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:36:40.136 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:36:40.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:40.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:40.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:40.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:36:40.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:40.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:40.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:40.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:40.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:40.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:40.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:40.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:40.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:40.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:40.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:40.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:40.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:40.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:40.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:40.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:40.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:40.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:40.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:40.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:40.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:40.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:40.141 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:36:40.619 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:36:40.669 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:36:40.671 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:36:40.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:40.674 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:36:40.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:40.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:40.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:41.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:41.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:41.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:41.090 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:36:41.141 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:41.142 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:41.142 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:41.142 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:41.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:41.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:41.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:41.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:41.564 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:36:41.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:41.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:41.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:41.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:41.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:41.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:41.996 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:41.996 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:41.996 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:41.996 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:41.997 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:36:41.997 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:36:41.997 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:36:41.997 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:36:41.997 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:36:41.997 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:36:41.997 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:36:47.003 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:36:47.003 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:36:47.003 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:36:47.003 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:36:47.003 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:36:47.003 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:36:47.011 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:36:47.012 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:36:47.012 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:47.012 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:36:47.012 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:36:47.015 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:36:47.016 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:36:47.016 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:36:47.016 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:47.016 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:36:47.016 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:36:47.017 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:36:47.017 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:36:47.017 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:47.019 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:36:47.019 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:36:47.019 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:36:47.019 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:47.019 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:36:47.019 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:36:47.019 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:36:47.019 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:36:47.019 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:47.021 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:36:47.021 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:36:47.021 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:36:47.021 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:47.021 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:36:47.021 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:36:47.021 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:36:47.021 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:36:47.021 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:47.024 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:36:47.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:36:47.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:36:47.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:36:47.024 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:36:47.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:36:47.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:36:47.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:47.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:36:47.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:36:47.024 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:36:47.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:47.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:47.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:47.024 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:47.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:47.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:47.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:47.024 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:36:47.024 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:36:47.024 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:36:47.024 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:36:47.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:47.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:47.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:47.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:36:47.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:47.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:47.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:47.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:47.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:47.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:47.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:47.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:47.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:47.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:47.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:47.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:47.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:47.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:47.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:47.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:47.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:47.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:47.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:47.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:47.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:47.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:47.029 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:36:47.508 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:36:47.543 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:36:47.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:47.546 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:36:47.549 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:36:47.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:47.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:47.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:47.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:47.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:47.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:47.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:47.979 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:36:48.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:48.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:48.028 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:48.028 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:48.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:48.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:48.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:48.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:48.450 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:36:48.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:48.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:48.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:48.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:48.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:48.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:48.864 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:48.864 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:48.864 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:48.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:48.865 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:36:48.865 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:36:48.865 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:36:48.865 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:36:48.865 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:36:48.865 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:36:48.865 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:36:48.865 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=398 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:36:48.865 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=398 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:36:48.865 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=398 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:36:48.865 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=398 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:36:48.865 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=398 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:36:48.865 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=398 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:36:53.872 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:36:53.872 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:36:53.872 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:36:53.872 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:36:53.872 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:36:53.872 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:36:53.881 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:36:53.882 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:36:53.882 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:53.883 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:36:53.883 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:36:53.886 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:36:53.886 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:36:53.887 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:36:53.887 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:53.887 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:36:53.888 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:36:53.888 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:36:53.888 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:36:53.888 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:53.889 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:36:53.890 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:36:53.890 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:36:53.890 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:53.890 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:36:53.890 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:36:53.890 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:36:53.890 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:36:53.890 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:53.892 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:36:53.892 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:36:53.892 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:36:53.892 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:36:53.893 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:36:53.893 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:36:53.893 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:36:53.893 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:36:53.893 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:53.896 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:36:53.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:36:53.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:36:53.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:36:53.896 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:36:53.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:36:53.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:36:53.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:53.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:36:53.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:36:53.896 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:36:53.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:53.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:53.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:53.896 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:53.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:53.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:53.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:53.896 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:36:53.896 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:36:53.896 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:36:53.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:53.896 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:36:53.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:53.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:53.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:36:53.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:53.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:53.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:53.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:53.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:53.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:53.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:53.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:53.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:53.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:53.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:53.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:53.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:53.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:53.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:36:53.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:53.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:53.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:53.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:53.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:36:53.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:53.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:36:53.901 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:36:54.379 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:36:54.427 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:36:54.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:54.429 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:36:54.431 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:36:54.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:36:54.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:54.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:54.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:54.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:54.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:54.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:54.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:54.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:54.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:54.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:54.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:54.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:54.849 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:36:54.900 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:54.900 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:54.900 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:54.900 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:55.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:55.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:55.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:55.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:55.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:55.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:55.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:55.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:55.321 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:36:55.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:55.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:55.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:55.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:55.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:55.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:55.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:55.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:55.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:55.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:55.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:55.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:36:55.793 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:36:55.797 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:36:55.797 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:36:55.798 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:36:55.798 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:36:55.801 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:36:55.802 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:36:55.802 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:36:55.802 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:36:55.802 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:36:55.802 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:36:55.803 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:36:55.803 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=412 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:36:55.803 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=412 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:36:55.803 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=412 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:36:55.803 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=412 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:36:55.803 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=412 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:36:55.804 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=412 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:36:55.804 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=412 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:37:00.809 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:37:00.810 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:37:00.810 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:00.810 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:00.810 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:00.810 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:00.819 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:00.819 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:37:00.819 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:00.819 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:37:00.819 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:37:00.821 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:37:00.821 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:37:00.821 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:37:00.821 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:00.821 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:00.821 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:37:00.821 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:37:00.821 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:37:00.821 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:00.822 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:37:00.822 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:37:00.822 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:37:00.822 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:00.822 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:00.822 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:37:00.822 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:37:00.822 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:37:00.822 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:00.824 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:37:00.824 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:37:00.824 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:37:00.824 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:00.824 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:00.824 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:37:00.824 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:37:00.824 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:37:00.824 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:37:00.826 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:37:00.826 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:00.826 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:00.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:00.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:00.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:00.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:00.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:00.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:00.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:00.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:00.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:00.831 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:37:01.309 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:37:01.351 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:37:01.354 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:37:01.354 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:37:01.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:01.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:01.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:01.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:01.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:01.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:01.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:01.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:01.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:01.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:01.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:01.780 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:37:01.829 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:01.830 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:01.830 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:01.830 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:02.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:02.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:02.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:02.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:02.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:02.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:02.252 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:37:02.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:02.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:02.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:02.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:02.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:02.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:02.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:02.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:02.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:02.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:02.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:02.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:02.696 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:02.696 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:02.697 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:02.697 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:02.697 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:02.697 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:37:02.697 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:37:02.697 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:37:07.704 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:37:07.704 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:37:07.704 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:07.704 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:07.704 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:07.704 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:07.714 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:07.715 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:37:07.715 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:07.715 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:37:07.715 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:37:07.717 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:37:07.717 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:37:07.717 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:37:07.717 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:07.718 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:07.718 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:37:07.718 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:37:07.718 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:37:07.718 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:07.719 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:37:07.719 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:37:07.719 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:37:07.719 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:07.719 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:07.719 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:37:07.719 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:37:07.719 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:37:07.719 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:07.721 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:37:07.721 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:37:07.721 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:37:07.721 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:07.721 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:07.721 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:37:07.721 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:37:07.721 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:37:07.721 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:07.723 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:37:07.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:37:07.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:37:07.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:37:07.723 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:37:07.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:37:07.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:37:07.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:07.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:37:07.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:37:07.723 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:37:07.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:07.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:07.723 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:07.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:07.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:07.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:07.723 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:37:07.723 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:37:07.723 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:37:07.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:07.723 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:37:07.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:07.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:07.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:37:07.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:07.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:07.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:07.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:07.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:07.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:07.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:07.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:07.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:07.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:07.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:07.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:07.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:07.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:07.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:07.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:07.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:07.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:07.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:07.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:07.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:07.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:07.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:07.728 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:37:08.207 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:37:08.249 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:37:08.250 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:37:08.251 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:37:08.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:08.320 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:08.320 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:08.320 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:08.320 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:08.321 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:08.321 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:08.321 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:37:08.321 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:37:08.321 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:37:08.322 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:08.322 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:13.330 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:37:13.330 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:37:13.330 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:13.330 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:13.331 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:13.331 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:13.339 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:13.341 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:37:13.341 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:13.341 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:37:13.341 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:37:13.345 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:37:13.345 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:37:13.345 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:37:13.345 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:13.346 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:13.346 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:37:13.347 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:37:13.347 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:37:13.347 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:13.348 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:37:13.348 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:37:13.348 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:37:13.348 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:13.349 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:13.349 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:37:13.349 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:37:13.349 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:37:13.349 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:13.351 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:37:13.351 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:37:13.351 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:37:13.351 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:13.351 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:13.351 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:37:13.352 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:37:13.352 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:37:13.352 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:13.354 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:37:13.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:37:13.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:37:13.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:37:13.355 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:37:13.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:37:13.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:37:13.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:37:13.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:13.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:37:13.355 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:37:13.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:13.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:13.355 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:13.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:13.355 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:37:13.355 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:37:13.355 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:37:13.355 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:37:13.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:13.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:13.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:13.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:13.360 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:37:13.837 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:37:13.882 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:37:13.885 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:37:13.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.887 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:37:13.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:13.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:14.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:14.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:14.004 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:14.004 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:14.004 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:14.004 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:14.005 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:14.005 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:14.005 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:37:14.005 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:37:14.005 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:37:14.005 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:14.005 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:19.012 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:37:19.012 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:37:19.012 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:19.012 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:19.012 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:19.012 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:19.023 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:19.024 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:37:19.024 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:19.024 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:37:19.024 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:37:19.026 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:37:19.026 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:37:19.026 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:37:19.026 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:19.027 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:19.027 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:37:19.027 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:37:19.027 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:37:19.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:19.028 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:37:19.028 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:37:19.028 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:37:19.028 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:19.028 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:19.028 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:37:19.029 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:37:19.029 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:37:19.029 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:19.030 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:37:19.030 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:37:19.031 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:37:19.031 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:19.031 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:19.031 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:37:19.031 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:37:19.031 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:37:19.031 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:19.034 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:37:19.034 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:37:19.034 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:37:19.034 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:37:19.034 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:37:19.034 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:37:19.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:37:19.034 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:19.034 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:37:19.034 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:37:19.034 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:37:19.034 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:19.034 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:19.034 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:19.034 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:19.034 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:19.034 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:19.034 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:19.034 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:37:19.034 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:37:19.034 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:37:19.034 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:37:19.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:19.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:19.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:19.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:37:19.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:19.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:19.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:19.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:19.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:19.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:19.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:19.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:19.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:19.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:19.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:19.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:19.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:19.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:19.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:19.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:19.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:19.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:19.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:19.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:19.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:19.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:19.039 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:37:19.516 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:37:19.565 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:37:19.569 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:37:19.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.573 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:37:19.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:19.671 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:19.671 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:19.671 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:19.671 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:19.672 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:19.672 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:19.672 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:19.672 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:19.672 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:37:19.672 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:37:19.672 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:37:24.680 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:37:24.680 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:37:24.680 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:24.680 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:24.680 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:24.680 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:24.687 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:24.688 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:37:24.688 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:24.688 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:37:24.688 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:37:24.691 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:37:24.691 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:37:24.691 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:37:24.691 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:24.691 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:24.692 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:37:24.692 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:37:24.692 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:37:24.692 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:24.693 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:37:24.693 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:37:24.693 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:37:24.693 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:24.694 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:24.694 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:37:24.694 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:37:24.694 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:37:24.694 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:24.695 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:37:24.696 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:37:24.696 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:37:24.696 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:24.696 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:24.696 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:37:24.696 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:37:24.696 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:37:24.696 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:24.698 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:37:24.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:37:24.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:37:24.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:37:24.698 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:37:24.699 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:37:24.699 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:37:24.699 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:24.699 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:24.700 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:24.700 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:24.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:24.700 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:24.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:24.700 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:24.700 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:24.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:24.700 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:24.700 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:24.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:24.700 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:24.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:24.700 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:24.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:24.704 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:37:25.180 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:37:25.225 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:37:25.228 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:37:25.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.230 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:37:25.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:25.313 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:25.313 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:25.314 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:25.314 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:25.315 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:25.315 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:37:25.315 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:37:25.315 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:37:25.315 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:25.315 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:25.315 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:25.315 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=133 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:37:25.315 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=133 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:37:25.315 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=133 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:37:25.315 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=133 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:37:25.315 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=133 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:37:25.315 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=133 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:37:30.323 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:37:30.323 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:37:30.323 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:30.323 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:30.324 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:30.324 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:30.331 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:30.333 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:37:30.333 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:30.333 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:37:30.333 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:37:30.338 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:37:30.338 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:37:30.338 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:37:30.338 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:30.338 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:30.338 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:37:30.339 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:37:30.339 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:37:30.339 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:30.343 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:37:30.343 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:37:30.343 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:37:30.343 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:30.343 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:30.343 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:37:30.344 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:37:30.344 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:37:30.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:30.347 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:37:30.347 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:37:30.347 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:37:30.347 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:30.348 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:30.348 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:37:30.348 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:37:30.348 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:37:30.348 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:30.353 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:37:30.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:37:30.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:37:30.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:37:30.353 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:37:30.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:37:30.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:37:30.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:30.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:37:30.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:37:30.354 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:37:30.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:30.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:30.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:30.354 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:30.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:30.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:30.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:30.354 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:37:30.354 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:37:30.354 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:37:30.354 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:37:30.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:30.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:30.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:30.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:37:30.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:30.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:30.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:30.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:30.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:30.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:30.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:30.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:30.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:30.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:30.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:30.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:30.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:30.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:30.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:30.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:30.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:30.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:30.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:30.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:30.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:30.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:30.359 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:37:30.837 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:37:30.899 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:37:30.901 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:37:30.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.903 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:37:30.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:30.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:30.976 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:30.976 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:30.976 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:30.976 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:30.977 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:30.977 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:30.977 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:30.977 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:30.977 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:37:30.977 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:37:30.977 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:37:35.984 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:37:35.984 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:37:35.984 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:35.984 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:35.984 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:35.984 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:35.992 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:35.993 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:37:35.993 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:35.993 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:37:35.994 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:37:35.997 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:37:35.997 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:37:35.997 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:37:35.997 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:35.998 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:35.998 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:37:35.998 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:37:35.998 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:37:35.999 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:36.000 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:37:36.000 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:37:36.000 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:37:36.000 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:36.000 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:36.000 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:37:36.000 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:37:36.000 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:37:36.000 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:36.002 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:37:36.002 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:37:36.002 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:37:36.002 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:36.002 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:36.002 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:37:36.002 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:37:36.002 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:37:36.002 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:36.005 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:37:36.005 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:37:36.005 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:37:36.005 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:37:36.005 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:37:36.005 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:37:36.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:37:36.005 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:36.005 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:37:36.005 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:37:36.005 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:37:36.005 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:36.005 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:36.005 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:36.005 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:36.005 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:36.005 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:36.005 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:36.005 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:37:36.005 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:37:36.005 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:37:36.005 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:36.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:36.010 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:37:36.488 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:37:36.520 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:37:36.521 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:37:36.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.521 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:37:36.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:36.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:36.605 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:36.605 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:36.605 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:36.605 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:36.606 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:36.606 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:36.606 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:36.606 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:36.606 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:37:36.606 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:37:36.606 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:37:41.613 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:37:41.613 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:37:41.613 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:41.613 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:41.613 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:41.613 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:41.619 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:41.620 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:37:41.620 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:41.621 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:37:41.621 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:37:41.627 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:37:41.627 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:37:41.627 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:37:41.627 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:41.627 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:41.627 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:37:41.628 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:37:41.628 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:37:41.628 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:41.631 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:37:41.632 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:37:41.632 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:37:41.632 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:41.632 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:41.632 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:37:41.632 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:37:41.632 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:37:41.632 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:41.635 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:37:41.635 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:37:41.635 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:37:41.635 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:41.635 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:41.635 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:37:41.636 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:37:41.636 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:37:41.636 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:41.640 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:37:41.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:37:41.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:37:41.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:37:41.640 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:37:41.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:37:41.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:37:41.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:37:41.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:41.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:37:41.640 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:37:41.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:41.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:41.640 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:41.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:41.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:41.640 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:37:41.640 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:37:41.640 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:37:41.640 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:37:41.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:41.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:41.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:41.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:37:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:41.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:41.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:41.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:41.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:41.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:41.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:41.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:41.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:41.645 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:37:42.122 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:37:42.177 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:37:42.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.181 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:37:42.184 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:37:42.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:42.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:42.281 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:42.281 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:42.281 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:42.281 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:42.282 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:42.282 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:42.282 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:42.282 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:42.282 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:37:42.282 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:37:42.282 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:37:47.288 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:37:47.288 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:37:47.288 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:47.288 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:47.289 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:47.289 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:47.301 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:47.302 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:37:47.302 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:47.302 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:37:47.302 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:37:47.304 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:37:47.304 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:37:47.304 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:37:47.304 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:47.304 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:47.305 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:37:47.305 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:37:47.305 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:37:47.305 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:47.306 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:37:47.307 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:37:47.307 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:37:47.307 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:47.307 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:47.307 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:37:47.307 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:37:47.307 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:37:47.307 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:47.308 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:37:47.308 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:37:47.308 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:37:47.308 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:47.308 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:47.308 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:37:47.309 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:37:47.309 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:37:47.309 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:47.310 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:37:47.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:37:47.310 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:37:47.311 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:37:47.311 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:37:47.311 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:47.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:47.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:47.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:47.316 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:37:47.794 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:37:47.831 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:37:47.832 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:37:47.833 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:37:47.834 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:37:47.834 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:37:47.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:37:47.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:47.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:37:47.835 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:37:47.835 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:37:47.835 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:37:47.835 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:37:48.265 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:37:48.314 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:48.314 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:48.315 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:48.315 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:48.737 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:37:49.210 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:37:49.315 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:49.315 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:49.316 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:49.316 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:49.683 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:37:50.155 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:37:50.316 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:50.316 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:50.316 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:50.317 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:50.626 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:37:51.100 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:37:51.304 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:37:51.304 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:37:51.310 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:51.310 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:51.310 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:51.311 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:51.312 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:51.312 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:51.312 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:37:51.312 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:37:51.312 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:37:51.312 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:51.312 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:56.317 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:37:56.317 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:37:56.317 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:56.317 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:56.317 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:56.317 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:56.324 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:56.326 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:37:56.326 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:56.326 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:37:56.327 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:37:56.331 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:37:56.332 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:37:56.332 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:37:56.332 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:56.332 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:56.332 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:37:56.333 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:37:56.333 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:37:56.333 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:56.336 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:37:56.336 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:37:56.337 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:37:56.337 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:56.337 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:56.337 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:37:56.337 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:37:56.337 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:37:56.337 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:56.340 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:37:56.340 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:37:56.340 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:37:56.340 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:37:56.340 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:56.341 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:37:56.341 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:37:56.341 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:37:56.341 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:56.345 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:37:56.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:37:56.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:37:56.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:37:56.345 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:37:56.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:37:56.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:37:56.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:56.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:37:56.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:37:56.345 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:37:56.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:56.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:56.345 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:56.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:56.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:56.345 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:37:56.345 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:37:56.345 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:37:56.345 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:37:56.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:56.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:56.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:56.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:37:56.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:56.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:56.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:56.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:56.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:56.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:56.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:56.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:56.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:56.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:56.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:37:56.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:56.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:56.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:56.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:56.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:56.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:56.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:56.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:56.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:56.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:37:56.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:56.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:37:56.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:37:56.350 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:37:56.828 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:37:56.877 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:37:56.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:56.881 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:37:56.883 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:37:56.908 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:37:56.908 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:37:56.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:37:56.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:37:56.911 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:37:56.911 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:37:56.911 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:37:56.911 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:37:56.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:37:56.924 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:37:56.924 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:37:56.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:37:56.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:37:57.301 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:37:57.349 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:57.349 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:57.349 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:57.349 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:57.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:37:57.422 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:37:57.422 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:37:57.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:37:57.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:37:57.423 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:37:57.423 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:37:57.424 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:37:57.424 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:37:57.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:37:57.439 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:37:57.439 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:37:57.446 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:37:57.446 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:37:57.447 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:37:57.447 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:37:57.447 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:37:57.447 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:37:57.447 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:37:57.447 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:37:57.447 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:37:57.447 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:37:57.447 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:37:57.447 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=238 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:37:57.447 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=238 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:37:57.448 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=238 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:37:57.448 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=238 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:37:57.448 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=238 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:37:57.448 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=238 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:38:02.454 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:38:02.455 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:38:02.455 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:38:02.455 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:38:02.455 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:38:02.455 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:38:02.462 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:38:02.463 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:38:02.464 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:38:02.464 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:38:02.464 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:38:02.467 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:38:02.467 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:38:02.467 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:38:02.467 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:38:02.468 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:38:02.468 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:38:02.468 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:38:02.468 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:38:02.469 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:38:02.469 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:38:02.470 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:38:02.470 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:38:02.470 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:38:02.470 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:38:02.470 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:38:02.470 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:38:02.470 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:38:02.470 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:38:02.472 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:38:02.472 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:38:02.472 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:38:02.472 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:38:02.472 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:38:02.472 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:38:02.472 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:38:02.472 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:38:02.472 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:38:02.475 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:38:02.475 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:38:02.475 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:02.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:02.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:02.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:02.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:02.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:02.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:02.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:02.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:02.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:02.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:02.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:02.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:02.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:02.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:02.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:02.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:02.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:02.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:02.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:02.480 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:38:02.958 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:38:03.001 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:38:03.003 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:38:03.006 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:38:03.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:38:03.026 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:38:03.026 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:38:03.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:38:03.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:38:03.032 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:38:03.032 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:38:03.032 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:38:03.032 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:38:03.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:38:03.061 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:38:03.061 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:38:03.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:38:03.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:38:03.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:38:03.173 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:38:03.174 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:38:03.174 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:38:03.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:38:03.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:38:03.175 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:38:03.175 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:38:03.175 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:38:03.175 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:38:03.430 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:38:03.478 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:38:03.478 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:38:03.478 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:38:03.478 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:38:03.901 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:38:04.372 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:38:04.479 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:38:04.480 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:38:04.480 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:38:04.480 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:38:04.845 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:38:05.318 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:38:05.480 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:38:05.481 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:38:05.481 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:38:05.481 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:38:05.790 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:38:06.261 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:38:06.481 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:38:06.482 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:38:06.482 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:38:06.482 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:38:06.732 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:38:07.205 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:38:07.483 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:38:07.483 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:38:07.484 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:38:07.484 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:38:07.678 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:38:08.150 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:38:08.621 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:38:09.094 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:38:09.567 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:38:10.039 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:38:10.512 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:38:10.985 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:38:11.458 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:38:11.928 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:38:12.402 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:38:12.874 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:38:13.346 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:38:13.817 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:38:14.291 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:38:14.763 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:38:15.235 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:38:15.706 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:38:16.180 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:38:16.652 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:38:17.125 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:38:17.596 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:38:18.069 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:38:18.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:38:18.362 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:38:18.362 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:38:18.362 [WARNING] transceiver.py:257 (MS@172.18.59.22:6700) RX TRXD message (fn=3432 tn=4 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:38:18.362 [WARNING] transceiver.py:257 (MS@172.18.59.22:6700) RX TRXD message (fn=3432 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:38:18.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:38:18.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:38:18.370 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:38:18.370 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:38:18.370 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:38:18.370 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:38:18.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:38:18.394 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:38:18.394 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:38:18.403 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:38:18.403 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:38:18.404 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:38:18.404 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:38:18.406 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:38:18.406 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:38:18.406 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:38:18.406 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:38:18.406 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:38:18.406 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:38:18.406 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:38:23.411 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:38:23.411 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:38:23.411 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:38:23.411 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:38:23.411 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:38:23.411 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:38:23.419 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:38:23.419 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:38:23.420 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:38:23.420 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:38:23.420 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:38:23.422 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:38:23.422 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:38:23.423 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:38:23.423 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:38:23.423 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:38:23.423 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:38:23.424 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:38:23.424 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:38:23.424 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:38:23.425 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:38:23.425 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:38:23.425 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:38:23.425 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:38:23.425 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:38:23.425 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:38:23.426 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:38:23.426 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:38:23.426 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:38:23.427 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:38:23.427 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:38:23.427 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:38:23.427 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:38:23.428 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:38:23.428 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:38:23.428 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:38:23.428 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:38:23.428 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:38:23.431 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:38:23.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:38:23.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:38:23.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:38:23.431 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:38:23.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:38:23.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:38:23.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:38:23.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:38:23.431 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:38:23.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:23.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:23.432 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:38:23.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:23.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:23.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:23.432 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:38:23.432 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:38:23.432 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:38:23.432 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:38:23.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:23.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:23.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:23.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:38:23.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:23.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:23.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:23.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:23.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:23.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:23.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:23.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:23.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:23.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:23.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:23.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:23.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:23.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:23.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:23.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:23.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:23.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:23.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:23.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:23.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:23.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:23.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:23.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:23.437 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:38:23.915 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:38:23.962 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:38:23.964 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:38:23.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:38:23.967 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:38:23.984 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:38:23.984 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:38:23.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:38:23.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:38:23.987 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:38:23.987 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:38:23.987 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:38:23.987 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:38:24.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:38:24.015 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:38:24.016 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:38:24.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:38:24.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:38:24.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:38:24.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:38:24.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:38:24.310 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:38:24.310 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:38:24.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:38:24.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:38:24.311 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:38:24.311 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:38:24.311 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:38:24.311 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:38:24.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:38:24.337 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:38:24.337 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:38:24.346 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:38:24.346 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:38:24.346 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:38:24.346 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:38:24.349 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:38:24.349 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:38:24.349 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:38:24.349 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:38:24.349 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:38:24.349 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:38:24.349 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:38:29.353 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:38:29.353 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:38:29.353 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:38:29.353 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:38:29.353 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:38:29.353 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:38:29.359 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:38:29.360 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:38:29.360 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:38:29.360 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:38:29.360 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:38:29.363 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:38:29.363 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:38:29.363 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:38:29.363 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:38:29.364 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:38:29.364 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:38:29.364 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:38:29.364 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:38:29.364 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:38:29.368 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:38:29.368 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:38:29.368 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:38:29.369 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:38:29.369 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:38:29.369 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:38:29.369 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:38:29.369 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:38:29.369 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:38:29.373 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:38:29.373 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:38:29.373 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:38:29.373 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:38:29.374 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:38:29.374 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:38:29.374 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:38:29.374 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:38:29.374 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:38:29.380 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:38:29.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:38:29.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:38:29.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:38:29.380 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:38:29.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:38:29.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:38:29.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:29.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:38:29.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:38:29.381 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:38:29.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:29.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:29.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:29.381 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:38:29.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:29.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:29.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:29.381 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:38:29.381 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:38:29.381 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:38:29.381 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:38:29.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:29.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:29.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:29.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:38:29.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:29.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:29.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:29.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:29.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:29.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:29.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:29.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:29.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:29.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:29.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:29.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:29.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:29.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:29.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:29.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:29.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:29.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:29.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:29.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:29.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:29.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:29.386 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:38:29.865 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:38:29.918 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:38:29.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:38:29.922 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:38:29.924 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:38:29.948 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:38:29.948 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:38:29.949 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:38:29.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:38:29.957 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:38:29.958 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:38:29.958 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:38:29.958 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:38:30.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:38:30.008 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:38:30.009 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:38:30.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:38:30.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:38:30.337 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:38:30.387 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:38:30.388 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:38:30.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:38:30.389 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:38:30.808 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:38:31.281 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:38:31.389 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:38:31.389 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:38:31.389 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:38:31.390 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:38:31.754 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:38:32.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:38:32.015 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:38:32.015 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:38:32.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:38:32.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:38:32.032 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:38:32.033 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:38:32.033 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:38:32.033 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:38:32.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:38:32.084 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:38:32.084 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:38:32.091 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:38:32.091 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:38:32.091 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:38:32.091 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:38:32.092 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:38:32.092 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:38:32.092 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:38:32.092 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:38:32.092 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:38:32.092 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:38:32.092 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:38:37.101 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:38:37.102 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:38:37.102 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:38:37.102 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:38:37.102 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:38:37.102 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:38:37.115 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:38:37.116 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:38:37.116 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:38:37.117 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:38:37.117 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:38:37.121 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:38:37.121 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:38:37.121 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:38:37.122 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:38:37.122 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:38:37.122 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:38:37.123 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:38:37.123 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:38:37.123 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:38:37.125 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:38:37.125 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:38:37.126 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:38:37.126 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:38:37.126 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:38:37.126 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:38:37.126 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:38:37.126 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:38:37.127 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:38:37.129 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:38:37.130 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:38:37.130 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:38:37.130 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:38:37.131 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:38:37.131 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:38:37.131 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:38:37.131 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:38:37.131 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:38:37.134 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:38:37.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:38:37.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:38:37.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:38:37.135 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:38:37.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:38:37.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:38:37.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:38:37.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:37.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:38:37.135 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:38:37.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:37.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:37.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:37.136 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:38:37.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:37.136 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:38:37.136 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:38:37.136 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:38:37.136 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:38:37.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:37.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:37.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:37.137 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:38:37.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:37.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:37.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:37.137 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:38:37.137 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:38:37.137 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:38:37.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:37.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:37.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:42.140 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:38:42.140 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:38:42.140 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:38:42.140 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:38:42.141 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:38:42.141 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:38:42.143 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:38:42.143 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:38:42.143 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:38:42.144 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:38:42.144 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:38:42.144 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:38:42.144 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:38:42.145 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:38:42.145 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:38:42.145 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:38:42.145 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:38:42.145 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:38:42.145 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:38:42.145 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:38:42.145 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:38:42.145 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:38:42.145 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:38:42.145 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:38:42.145 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:38:42.145 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:38:42.145 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:38:42.145 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:38:42.145 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:38:42.146 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:38:42.146 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:38:42.146 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:38:42.146 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:38:42.146 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:38:42.146 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:38:42.146 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:38:42.146 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:38:42.146 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:38:42.148 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:38:42.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:38:42.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:38:42.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:38:42.148 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:38:42.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:38:42.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:38:42.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:42.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:38:42.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:38:42.148 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:38:42.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:42.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:42.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:42.148 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:38:42.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:42.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:42.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:42.148 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:38:42.148 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:38:42.148 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:38:42.148 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:38:42.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:42.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:42.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:42.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:38:42.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:38:42.149 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:38:42.149 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:38:42.149 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:38:46.932 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.59.20:5700'
2026-03-06 02:38:46.932 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.59.20:5802)
2026-03-06 02:38:46.932 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.59.20:5801)
2026-03-06 02:38:46.932 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.59.22:6700'
2026-03-06 02:38:46.932 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.59.22:6802)
2026-03-06 02:38:46.932 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.59.22:6801)
2026-03-06 02:38:46.932 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.59.20:5700/1'
2026-03-06 02:38:46.932 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.59.20:5804)
2026-03-06 02:38:46.932 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.59.20:5803)
2026-03-06 02:38:46.932 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.59.20:5700/2'
2026-03-06 02:38:46.932 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.59.20:5806)
2026-03-06 02:38:46.932 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.59.20:5805)
2026-03-06 02:38:46.932 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.59.20:5700/3'
2026-03-06 02:38:46.932 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.59.20:5808)
2026-03-06 02:38:46.932 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.59.20:5807)
2026-03-06 02:38:46.932 [INFO] fake_trx.py:429 Init complete
2026-03-06 02:38:46.933 [INFO] fake_trx.py:460 Setting real time process scheduler to SCHED_RR, priority 30
2026-03-06 02:38:47.463 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:38:47.463 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:38:47.463 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:38:47.464 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:38:47.464 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:38:47.464 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:39:04.528 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:39:04.528 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:39:04.528 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:39:04.528 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:39:04.529 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:39:04.529 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:39:09.562 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:39:09.562 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:39:09.562 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:39:09.562 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:39:09.562 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:39:09.562 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:39:14.594 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:39:14.594 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:39:14.595 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:39:14.595 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:39:14.595 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:39:14.595 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:39:19.649 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:39:19.649 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:39:19.649 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:39:19.649 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:39:19.649 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:39:19.649 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:39:24.710 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:39:24.710 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:39:24.711 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:39:24.711 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:39:24.711 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:39:24.711 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:39:29.771 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:39:29.771 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:39:29.771 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:39:29.771 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:39:29.771 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:39:29.771 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:39:34.822 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:39:34.822 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:39:34.823 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:39:34.823 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:39:34.823 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:39:34.823 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:39:39.879 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:39:39.879 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:39:39.879 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:39:39.879 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:39:39.879 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:39:39.879 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:39:44.933 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:39:44.933 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:39:44.933 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:39:44.933 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:39:44.933 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:39:44.934 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:39:49.989 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:39:49.989 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:39:49.989 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:39:49.990 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:39:49.990 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:39:49.990 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:39:50.010 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:39:50.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:39:50.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:39:50.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:39:50.010 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:39:50.010 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:39:50.010 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:39:50.010 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:39:50.010 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:39:50.010 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:39:50.010 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:39:50.010 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:39:50.010 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:39:50.010 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:39:50.010 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 0 -> 1
2026-03-06 02:39:50.010 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:39:50.010 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 0 -> 1
2026-03-06 02:39:50.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:39:50.011 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:39:50.011 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 0 -> 1
2026-03-06 02:39:50.011 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:39:50.011 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:39:50.011 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 0 -> 1
2026-03-06 02:39:50.011 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:39:55.026 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:39:55.026 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:39:55.026 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:39:55.026 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:39:55.026 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:39:55.026 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:40:00.062 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:40:00.062 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:40:00.062 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:40:00.062 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:40:00.062 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:40:00.062 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:40:00.062 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:40:00.062 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:40:00.062 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:40:00.062 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:40:05.097 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:40:05.097 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:40:05.098 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:40:05.098 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:40:05.098 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:40:05.098 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:40:10.139 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:40:10.139 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:40:10.139 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:40:10.139 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:40:10.139 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:40:10.139 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:40:15.166 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:40:15.166 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:40:15.166 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:40:15.166 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:40:15.166 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:40:15.166 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:40:20.202 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:40:20.202 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:40:20.202 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:40:20.202 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:40:20.202 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:40:20.202 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:40:26.339 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.59.20:5700'
2026-03-06 02:40:26.339 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.59.20:5802)
2026-03-06 02:40:26.339 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.59.20:5801)
2026-03-06 02:40:26.339 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.59.22:6700'
2026-03-06 02:40:26.339 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.59.22:6802)
2026-03-06 02:40:26.339 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.59.22:6801)
2026-03-06 02:40:26.339 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.59.20:5700/1'
2026-03-06 02:40:26.339 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.59.20:5804)
2026-03-06 02:40:26.339 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.59.20:5803)
2026-03-06 02:40:26.339 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.59.20:5700/2'
2026-03-06 02:40:26.339 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.59.20:5806)
2026-03-06 02:40:26.339 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.59.20:5805)
2026-03-06 02:40:26.339 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.59.20:5700/3'
2026-03-06 02:40:26.339 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.59.20:5808)
2026-03-06 02:40:26.339 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.59.20:5807)
2026-03-06 02:40:26.339 [INFO] fake_trx.py:429 Init complete
2026-03-06 02:40:26.339 [INFO] fake_trx.py:460 Setting real time process scheduler to SCHED_RR, priority 30
2026-03-06 02:40:26.919 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:40:26.920 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:40:26.920 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:40:26.920 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:40:26.920 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:40:26.920 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:40:30.901 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:40:30.904 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:40:30.904 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:40:30.904 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:40:30.905 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 0 -> 1
2026-03-06 02:40:30.911 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:40:30.912 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:40:30.912 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:40:30.912 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:40:30.913 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:40:30.913 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:40:30.914 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:40:30.914 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 0 -> 1
2026-03-06 02:40:30.914 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:40:30.917 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:40:30.917 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:40:30.918 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:40:30.918 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:40:30.918 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:40:30.918 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:40:30.919 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:40:30.919 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 0 -> 1
2026-03-06 02:40:30.919 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:40:30.922 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:40:30.922 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:40:30.922 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:40:30.922 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:40:30.922 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:40:30.922 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:40:30.922 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:40:30.923 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 0 -> 1
2026-03-06 02:40:30.923 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:40:30.925 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:40:30.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:40:30.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:40:30.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:40:30.925 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:40:30.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:40:30.925 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:40:30.925 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:40:30.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:40:30.925 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:40:30.925 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:40:30.925 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:40:30.926 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:40:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:40:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:40:30.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:40:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:40:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:40:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:40:30.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:40:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:40:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:40:30.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:40:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:40:30.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:40:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:40:30.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:40:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:40:30.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:40:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:40:30.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:30.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:40:30.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:40:30.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:30.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:40:30.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:40:30.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:30.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:40:30.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:40:30.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:40:30.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:40:30.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:40:30.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:40:30.930 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:40:31.405 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:40:31.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:31.468 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:40:31.470 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:40:31.471 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:40:31.483 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:31.483 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:31.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:40:31.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:31.488 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:31.488 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:31.488 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:40:31.488 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:40:31.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:31.677 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:31.678 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:31.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:31.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:31.875 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:40:31.930 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:40:31.930 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:40:31.930 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:40:31.931 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:40:32.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:32.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:32.076 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:32.076 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:32.085 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:32.085 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:32.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:40:32.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:32.086 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:32.086 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:32.086 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:40:32.086 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:40:32.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:32.171 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:32.171 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:32.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:32.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:32.348 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:40:32.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:32.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:32.571 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:32.571 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:32.590 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:32.591 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:32.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:40:32.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:32.592 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:32.593 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:32.593 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:40:32.593 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:40:32.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:32.820 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:40:32.855 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:32.856 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:32.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:32.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:32.931 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:40:32.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:40:32.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:40:32.932 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:40:33.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:33.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:33.259 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:33.260 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:33.276 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:33.276 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:33.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:40:33.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:33.278 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:33.278 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:33.278 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:40:33.278 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:40:33.291 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:40:33.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:33.353 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:33.353 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:33.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:33.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:33.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:33.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:33.748 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:33.749 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:33.758 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:33.758 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:33.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:40:33.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:33.759 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:33.759 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:33.759 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:40:33.759 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:40:33.762 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:40:33.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:33.932 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:40:33.932 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:40:33.932 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:40:33.933 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:40:34.032 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:34.032 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:34.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:34.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:34.233 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:40:34.706 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:40:34.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:34.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:34.768 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:34.769 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:34.787 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:34.787 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:34.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:40:34.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:34.788 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:34.788 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:34.789 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:40:34.789 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:40:34.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:34.934 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:40:34.934 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:40:34.934 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:40:34.934 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:40:34.974 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:40:34.975 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-06 02:40:34.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:34.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:35.179 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:40:35.651 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:40:35.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:35.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:35.796 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:35.796 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:35.796 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:40:35.814 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:35.814 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:35.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:40:35.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:35.816 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:35.816 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:35.816 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:40:35.816 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:40:35.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:35.922 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:40:35.922 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-06 02:40:35.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:35.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:36.125 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:40:36.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:36.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:36.335 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:36.336 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:36.336 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:40:36.353 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:36.353 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:36.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:40:36.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:36.355 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:36.355 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:36.355 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:40:36.355 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:40:36.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:36.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:36.597 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:40:36.633 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:36.634 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:36.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:36.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:37.069 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:40:37.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:37.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:37.361 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:37.361 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:37.379 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:37.379 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:37.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:40:37.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:37.381 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:37.381 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:37.381 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:40:37.381 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:40:37.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:37.540 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:40:37.575 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:37.575 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:37.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:37.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:38.011 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:40:38.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:38.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:38.381 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:38.381 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:38.399 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:38.399 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:38.399 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:40:38.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:38.400 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:38.400 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:38.400 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:40:38.400 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:40:38.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:38.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:38.484 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:40:38.516 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:38.517 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:38.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:38.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:38.957 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:40:39.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:39.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:39.287 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:39.287 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:39.304 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:39.304 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:39.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:40:39.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:39.306 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:39.306 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:39.306 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:40:39.306 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:40:39.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:39.429 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:40:39.464 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:40:39.464 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:40:39.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:39.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:39.902 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:40:40.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:40.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:40.248 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:40.248 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:40.248 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:40:40.261 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:40.261 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:40.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:40:40.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:40.263 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:40.263 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:40.263 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:40:40.263 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:40:40.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:40.375 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:40:40.412 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:40:40.412 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:40:40.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:40.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:40.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:40.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:40.794 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:40.794 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:40.794 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:40:40.810 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:40.810 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:40.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:40:40.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:40.811 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:40.811 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:40.811 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:40:40.811 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:40:40.846 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:40:40.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:40.910 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:40:40.910 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:40:40.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:40.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:41.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:41.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:41.005 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:41.005 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:41.005 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:40:41.021 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:41.021 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:41.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:40:41.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:41.023 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:41.023 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:41.023 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:40:41.023 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:40:41.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:41.118 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:40:41.118 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:40:41.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:41.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:41.318 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:40:41.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:41.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:41.496 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:41.496 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:41.496 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:40:41.515 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:41.515 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:41.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:40:41.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:41.516 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:41.517 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:41.517 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:40:41.517 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:40:41.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:41.616 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:40:41.616 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:40:41.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:41.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:41.789 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:40:41.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:41.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:41.985 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:41.985 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:41.985 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:40:42.003 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:42.003 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:42.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:40:42.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:42.004 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:42.004 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:42.004 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:40:42.004 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:40:42.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:42.086 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:40:42.087 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:40:42.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:42.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:42.262 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:40:42.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:42.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:42.473 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:42.473 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:42.474 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:40:42.483 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:42.483 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:42.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:40:42.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:42.484 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:42.485 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:42.485 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:40:42.485 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:40:42.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:42.558 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:40:42.558 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:40:42.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:42.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:42.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:42.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:42.652 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:42.652 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:42.653 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:40:42.663 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:42.663 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:42.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:40:42.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:42.664 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:42.664 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:42.665 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:40:42.665 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:40:42.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:42.735 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:40:42.771 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:40:42.771 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:40:42.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:42.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:43.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:43.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:43.149 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:43.149 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:43.149 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:40:43.168 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:43.168 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:43.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:40:43.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:43.170 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:43.170 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:43.170 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:40:43.170 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:40:43.206 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:40:43.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:43.269 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:40:43.270 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:40:43.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:43.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:43.633 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:43.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:43.638 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:43.638 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:43.638 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:40:43.647 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:43.647 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:43.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:40:43.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:43.649 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:40:43.649 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:40:43.649 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:40:43.649 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:40:43.678 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:40:43.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:43.740 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:40:43.740 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:40:43.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:43.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:44.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:40:44.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:44.127 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:44.127 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:44.127 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:40:44.133 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:40:44.133 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:40:44.133 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:40:44.133 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:40:44.134 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:40:44.134 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:40:44.134 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:40:44.134 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:40:44.134 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:40:44.134 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:40:44.134 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:40:44.134 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2855 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:40:44.134 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2855 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:40:44.134 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2855 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:40:44.134 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2855 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:40:44.134 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2855 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:40:44.134 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2855 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:40:49.141 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:40:49.141 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:40:49.141 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:40:49.141 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:40:49.141 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:40:49.141 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:40:49.149 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:40:49.151 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:40:49.151 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:40:49.152 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:40:49.152 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:40:49.156 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:40:49.157 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:40:49.157 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:40:49.157 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:40:49.157 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:40:49.157 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:40:49.157 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:40:49.157 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:40:49.158 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:40:49.161 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:40:49.162 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:40:49.162 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:40:49.162 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:40:49.162 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:40:49.162 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:40:49.162 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:40:49.162 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:40:49.163 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:40:49.166 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:40:49.166 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:40:49.166 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:40:49.166 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:40:49.166 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:40:49.167 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:40:49.167 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:40:49.167 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:40:49.167 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:40:49.172 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:40:49.172 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:40:49.172 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:40:49.172 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:40:49.172 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:40:49.172 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:40:49.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:40:49.172 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:40:49.172 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:40:49.172 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:40:49.172 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:40:49.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:40:49.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:40:49.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:40:49.173 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:40:49.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:40:49.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:40:49.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:40:49.173 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:40:49.173 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:40:49.173 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:40:49.173 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:40:49.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:40:49.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:40:49.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:40:49.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:40:49.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:40:49.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:40:49.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:40:49.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:49.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:40:49.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:40:49.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:49.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:40:49.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:40:49.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:40:49.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:49.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:40:49.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:49.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:40:49.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:40:49.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:49.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:40:49.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:49.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:40:49.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:49.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:40:49.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:49.178 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:40:49.657 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:40:49.706 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:40:49.707 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:40:49.709 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:40:49.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.727 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:49.728 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:49.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:40:49.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 02:40:49.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 02:40:49.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:49.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 02:40:50.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 02:40:50.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 02:40:50.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 02:40:50.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 02:40:50.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.122 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:40:50.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 02:40:50.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.178 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:40:50.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.179 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:40:50.179 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:40:50.180 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:40:50.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 02:40:50.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 02:40:50.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 02:40:50.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:50.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 02:40:50.586 [DEBUG] clck_gen.py:113 IND CLOCK 306
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2026-03-06 02:40:51.051 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:40:51.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 02:40:51.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.178 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:40:51.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.180 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:40:51.180 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:40:51.181 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:40:51.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 02:40:51.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 02:40:51.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
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2026-03-06 02:40:51.515 [DEBUG] clck_gen.py:113 IND CLOCK 510
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2026-03-06 02:40:51.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.980 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:40:51.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:51.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:52.175 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:40:52.175 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:40:52.175 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:40:52.175 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:40:52.179 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:40:52.179 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:40:52.179 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:40:52.179 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:40:52.180 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:40:52.180 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:40:52.180 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:40:52.180 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=657 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:40:52.180 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=657 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:40:52.180 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=657 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:40:52.181 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=657 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:40:52.181 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=657 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:40:52.181 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=657 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:40:57.181 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:40:57.181 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:40:57.181 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:40:57.181 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:40:57.181 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:40:57.181 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:40:57.188 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:40:57.189 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:40:57.189 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:40:57.189 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:40:57.190 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:40:57.191 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:40:57.192 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:40:57.192 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:40:57.192 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:40:57.192 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:40:57.193 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:40:57.193 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:40:57.193 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:40:57.193 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:40:57.194 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:40:57.194 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:40:57.194 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:40:57.194 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:40:57.194 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:40:57.194 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:40:57.194 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:40:57.194 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:40:57.194 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:40:57.196 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:40:57.196 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:40:57.196 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:40:57.196 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:40:57.196 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:40:57.196 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:40:57.196 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:40:57.196 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:40:57.196 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:40:57.198 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:40:57.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:40:57.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:40:57.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:40:57.198 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:40:57.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:40:57.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:40:57.199 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:40:57.199 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:40:57.199 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:40:57.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:40:57.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:40:57.203 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:40:57.682 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:40:57.718 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:40:57.719 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:40:57.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:57.721 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:40:57.743 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:40:57.743 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:40:57.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:40:57.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:57.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:40:57.762 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:40:57.763 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:40:57.763 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:40:57.763 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:40:57.767 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:40:57.767 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:40:57.767 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:40:57.767 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:40:57.767 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:40:57.767 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:40:57.767 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:40:57.767 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:40:57.767 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:40:57.767 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:40:57.767 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:40:57.767 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:40:57.767 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:40:57.767 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:40:57.767 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:41:02.770 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:41:02.770 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:41:02.770 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:41:02.770 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:41:02.770 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:41:02.770 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:41:02.781 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:41:02.783 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:41:02.783 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:41:02.783 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:41:02.783 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:41:02.787 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:41:02.787 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:41:02.787 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:41:02.787 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:41:02.787 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:41:02.787 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:41:02.787 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:41:02.788 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:41:02.788 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:41:02.791 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:41:02.791 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:41:02.791 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:41:02.791 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:41:02.791 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:41:02.791 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:41:02.791 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:41:02.791 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:41:02.791 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:41:02.794 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:41:02.794 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:41:02.795 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:41:02.795 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:41:02.795 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:41:02.795 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:41:02.795 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:41:02.795 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:41:02.795 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:41:02.798 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:41:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:41:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:41:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:41:02.798 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:41:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:41:02.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:41:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:41:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:41:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:41:02.798 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:41:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:41:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:41:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:41:02.798 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:41:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:41:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:41:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:41:02.798 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:41:02.798 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:41:02.798 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:41:02.798 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:41:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:41:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:41:02.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:41:02.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:41:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:41:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:41:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:41:02.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:41:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:41:02.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:41:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:41:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:41:02.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:41:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:41:02.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:41:02.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:41:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:41:02.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:02.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:41:02.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:02.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:02.803 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:41:03.281 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:41:03.322 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:41:03.323 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:41:03.324 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:41:03.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:03.340 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:03.340 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:03.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:41:03.359 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:41:03.360 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:41:03.360 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:41:03.360 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:41:03.361 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:41:03.361 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:41:03.361 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:41:03.361 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:41:03.361 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:41:03.361 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:41:03.361 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:41:08.367 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:41:08.367 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:41:08.367 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:41:08.367 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:41:08.367 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:41:08.367 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:41:08.370 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:41:08.370 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:41:08.370 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:41:08.370 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:41:08.370 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:41:08.371 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:41:08.371 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:41:08.372 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:41:08.372 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:41:08.372 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:41:08.372 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:41:08.372 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:41:08.372 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:41:08.372 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:41:08.373 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:41:08.373 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:41:08.373 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:41:08.373 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:41:08.373 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:41:08.373 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:41:08.373 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:41:08.373 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:41:08.373 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:41:08.374 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:41:08.374 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:41:08.374 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:41:08.374 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:41:08.374 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:41:08.374 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:41:08.374 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:41:08.374 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:41:08.374 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:41:08.376 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:41:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:41:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:41:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:41:08.376 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:41:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:41:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:41:08.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:41:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:41:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:41:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:41:08.376 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:41:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:41:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:41:08.376 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:41:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:41:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:41:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:41:08.376 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:41:08.376 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:41:08.376 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:41:08.376 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:41:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:08.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:41:08.381 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:41:08.859 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:41:08.901 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:41:08.903 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:41:08.905 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:41:08.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:08.921 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:08.921 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:08.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:41:08.934 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:08.934 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:08.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:41:08.942 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:08.942 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:08.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:41:08.950 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:08.950 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:08.950 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:41:08.957 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:08.957 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:08.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:41:08.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:08.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:08.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:41:08.972 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:08.972 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:08.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:41:08.979 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:08.979 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:08.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:41:08.986 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:08.986 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:08.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:41:08.993 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:08.993 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:08.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:41:09.000 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:09.000 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:09.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:41:09.007 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:09.007 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:09.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:41:09.014 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:09.014 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:09.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:41:09.018 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:41:09.019 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:41:09.019 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:41:09.019 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:41:09.020 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:41:09.020 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:41:09.021 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:41:09.021 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:41:09.021 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:41:09.021 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:41:09.021 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:41:14.027 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:41:14.027 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:41:14.027 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:41:14.027 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:41:14.027 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:41:14.027 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:41:14.036 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:41:14.037 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:41:14.037 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:41:14.037 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:41:14.037 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:41:14.041 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:41:14.041 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:41:14.042 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:41:14.042 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:41:14.042 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:41:14.042 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:41:14.042 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:41:14.042 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:41:14.042 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:41:14.046 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:41:14.046 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:41:14.046 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:41:14.046 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:41:14.047 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:41:14.047 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:41:14.047 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:41:14.047 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:41:14.047 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:41:14.050 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:41:14.051 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:41:14.051 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:41:14.051 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:41:14.051 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:41:14.051 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:41:14.051 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:41:14.051 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:41:14.051 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:41:14.056 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:41:14.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:41:14.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:41:14.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:41:14.056 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:41:14.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:41:14.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:41:14.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:41:14.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:41:14.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:41:14.057 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:41:14.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:41:14.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:41:14.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:41:14.057 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:41:14.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:41:14.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:41:14.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:41:14.057 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:41:14.057 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:41:14.057 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:41:14.058 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:41:14.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:41:14.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:41:14.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:41:14.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:41:14.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:41:14.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:14.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:41:14.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:41:14.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:14.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:41:14.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:41:14.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:41:14.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:14.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:41:14.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:41:14.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:41:14.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:14.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:41:14.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:41:14.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:41:14.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:14.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:41:14.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:14.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:41:14.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:14.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:14.062 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:41:14.541 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:41:14.589 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:41:14.592 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:41:14.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:14.594 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:41:14.606 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:14.606 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:14.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:41:14.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:14.609 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:41:14.610 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:41:14.610 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:41:14.611 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:41:14.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:14.645 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:41:14.645 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:41:14.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:14.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:14.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:15.013 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:41:15.061 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:41:15.061 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:41:15.062 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:41:15.062 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:41:15.484 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:41:15.957 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:41:16.062 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:41:16.062 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:41:16.063 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:41:16.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:41:16.430 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:41:16.902 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:41:17.062 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:41:17.063 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:41:17.064 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:41:17.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:41:17.373 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:41:17.847 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:41:18.064 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:41:18.064 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:41:18.065 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:41:18.065 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:41:18.319 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:41:18.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:18.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:18.747 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:18.747 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:18.756 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:18.756 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:18.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:41:18.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:18.757 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:41:18.757 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:41:18.757 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:41:18.757 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:41:18.791 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:41:18.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:18.800 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:41:18.800 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:41:18.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:18.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:19.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:19.065 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:41:19.065 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:41:19.066 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:41:19.066 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:41:19.262 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:41:19.735 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:41:20.208 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:41:20.680 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:41:21.151 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:41:21.625 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:41:22.097 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:41:22.569 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:41:23.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:23.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:23.015 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:23.015 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:23.031 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:23.031 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:23.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:41:23.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:23.033 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:41:23.033 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:41:23.033 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:41:23.033 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:41:23.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:23.037 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:41:23.037 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:41:23.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:23.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:23.042 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:41:23.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:23.515 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:41:23.987 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:41:24.458 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:41:24.931 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:41:25.404 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:41:25.876 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:41:26.347 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:41:26.818 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:41:27.291 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:41:27.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:27.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:27.480 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:27.480 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:27.490 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:27.490 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:27.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:41:27.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:27.491 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:41:27.491 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:41:27.491 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:41:27.491 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:41:27.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:27.531 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:41:27.531 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:41:27.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:27.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:27.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:27.763 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:41:28.235 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:41:28.706 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:41:29.180 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:41:29.652 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:41:30.124 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:41:30.598 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:41:31.070 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:41:31.543 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:41:31.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:31.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:31.747 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:31.747 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:31.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:31.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:31.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:41:31.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:31.768 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:41:31.768 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:41:31.768 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:41:31.768 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:41:31.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:31.775 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:41:31.775 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:41:31.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:31.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:32.016 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:41:32.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:32.489 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:41:32.961 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:41:33.435 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:41:33.907 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:41:34.379 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:41:34.853 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 02:41:35.325 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 02:41:35.798 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 02:41:36.271 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 02:41:36.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:36.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:36.360 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:36.360 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:36.377 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:36.377 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:36.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:41:36.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:36.379 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:41:36.379 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:41:36.379 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:41:36.379 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:41:36.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:36.416 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:41:36.416 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-06 02:41:36.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:36.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:36.744 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 02:41:37.217 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 02:41:37.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:37.690 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 02:41:38.163 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 02:41:38.635 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 02:41:39.108 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 02:41:39.581 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 02:41:40.054 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 02:41:40.526 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 02:41:40.999 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 02:41:41.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:41.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:41.243 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:41.243 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:41.244 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:41:41.261 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:41.261 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:41.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:41:41.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:41.262 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:41:41.262 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:41:41.262 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:41:41.262 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:41:41.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:41.285 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:41:41.285 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-06 02:41:41.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:41.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:41.472 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 02:41:41.945 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 02:41:42.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:42.418 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 02:41:42.890 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 02:41:43.363 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 02:41:43.836 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 02:41:44.308 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 02:41:44.781 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 02:41:45.254 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 02:41:45.726 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 02:41:46.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:46.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:46.121 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:46.122 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:46.122 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:41:46.141 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:46.141 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:46.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:41:46.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:46.143 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:41:46.143 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:41:46.143 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:41:46.143 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:41:46.199 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 02:41:46.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:46.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:46.209 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:41:46.209 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:41:46.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:46.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:46.672 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 02:41:46.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:47.145 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 02:41:47.618 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 02:41:48.091 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 02:41:48.563 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 02:41:49.034 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-06 02:41:49.508 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-06 02:41:49.980 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-06 02:41:50.452 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-06 02:41:50.923 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-06 02:41:51.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:51.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:51.005 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:51.005 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:51.024 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:51.024 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:51.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:41:51.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:51.026 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:41:51.026 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:41:51.026 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:41:51.026 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:41:51.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:51.071 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:41:51.072 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:41:51.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:51.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:51.396 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-06 02:41:51.869 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-06 02:41:51.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:52.341 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-06 02:41:52.815 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-06 02:41:53.287 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-06 02:41:53.760 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-06 02:41:54.231 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-06 02:41:54.704 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-06 02:41:55.176 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-06 02:41:55.648 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-06 02:41:55.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:55.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:55.877 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:55.878 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:55.896 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:41:55.896 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:41:55.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:41:55.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:55.897 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:41:55.898 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:41:55.898 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:41:55.898 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:41:55.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:41:55.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:55.939 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:41:55.940 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:41:55.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:55.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:41:56.119 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-06 02:41:56.593 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-06 02:41:56.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:41:57.066 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-06 02:41:57.540 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-06 02:41:58.012 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-06 02:41:58.484 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-06 02:41:58.983 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-06 02:41:59.455 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-06 02:41:59.929 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-06 02:42:00.401 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-06 02:42:00.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:00.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:00.641 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:00.641 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:00.652 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:00.653 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:00.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:42:00.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:00.654 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:00.654 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:00.654 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:42:00.654 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:42:00.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:00.691 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:42:00.691 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:42:00.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:00.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:00.873 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-06 02:42:01.347 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-06 02:42:01.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:01.819 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-06 02:42:02.292 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-06 02:42:02.765 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-06 02:42:03.237 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-06 02:42:03.712 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-06 02:42:04.185 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-06 02:42:04.660 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-06 02:42:05.132 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-06 02:42:05.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:05.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:05.486 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:05.486 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:05.486 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:42:05.504 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:05.505 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:05.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:42:05.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:05.506 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:05.506 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:05.507 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:42:05.507 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:42:05.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:05.561 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:42:05.561 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:42:05.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:05.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:05.603 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-06 02:42:06.077 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-06 02:42:06.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:06.549 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-06 02:42:07.023 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-06 02:42:07.496 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-06 02:42:07.969 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-06 02:42:08.443 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-06 02:42:08.916 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-06 02:42:09.389 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-06 02:42:09.863 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-06 02:42:10.335 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-06 02:42:10.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:10.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:10.369 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:10.369 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:10.369 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:42:10.386 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:10.387 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:10.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:42:10.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:10.388 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:10.388 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:10.389 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:42:10.389 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:42:10.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:10.437 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:42:10.438 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:42:10.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:10.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:10.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:10.807 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-06 02:42:11.281 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-06 02:42:11.753 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-06 02:42:12.227 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-06 02:42:12.699 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-06 02:42:13.171 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-06 02:42:13.643 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-06 02:42:14.116 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-06 02:42:14.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:14.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:14.494 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:14.494 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:14.494 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:42:14.514 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:14.514 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:14.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:42:14.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:14.515 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:14.516 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:14.516 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:42:14.516 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:42:14.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:14.545 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:42:14.545 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:42:14.545 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:14.545 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:14.588 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-06 02:42:14.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:15.062 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-06 02:42:15.534 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-06 02:42:16.006 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-06 02:42:16.480 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-06 02:42:16.952 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-06 02:42:17.424 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-06 02:42:17.898 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-06 02:42:18.371 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-06 02:42:18.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:18.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:18.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:18.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:18.766 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:42:18.781 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:18.781 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:18.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:42:18.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:18.782 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:18.782 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:18.782 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:42:18.782 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:42:18.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:18.789 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:42:18.789 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:42:18.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:18.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:18.842 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-06 02:42:19.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:19.314 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-06 02:42:19.788 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-06 02:42:20.260 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-06 02:42:20.732 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-06 02:42:21.206 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-06 02:42:21.678 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-06 02:42:22.149 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-06 02:42:22.623 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-06 02:42:23.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:23.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:23.040 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:23.040 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:23.040 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:42:23.040 [WARNING] transceiver.py:257 (MS@172.18.59.22:6700) RX TRXD message (fn=14883 tn=1 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:42:23.058 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:23.058 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:23.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:42:23.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:23.059 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:23.059 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:23.059 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:42:23.059 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:42:23.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:23.095 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-06 02:42:23.098 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:42:23.098 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:42:23.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:23.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:23.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:23.567 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-06 02:42:24.040 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-06 02:42:24.513 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-06 02:42:24.986 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-06 02:42:25.459 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-06 02:42:25.932 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-06 02:42:26.403 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-06 02:42:26.876 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-06 02:42:27.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:27.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:27.311 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:27.311 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:27.311 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:42:27.331 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:27.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:27.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:42:27.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:27.332 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:27.333 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:27.333 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:42:27.333 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:42:27.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:27.341 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:42:27.342 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:42:27.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:27.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:27.348 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-06 02:42:27.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:27.820 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-06 02:42:28.292 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-06 02:42:28.766 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-06 02:42:29.238 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-06 02:42:29.712 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-06 02:42:30.183 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-06 02:42:30.655 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-06 02:42:31.129 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-06 02:42:31.601 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-06 02:42:31.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:31.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:31.744 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:31.744 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:31.744 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:42:31.763 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:31.763 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:31.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:42:31.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:31.764 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:31.765 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:31.765 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:42:31.765 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:42:31.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:31.792 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:42:31.792 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:42:31.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:31.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:32.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:32.073 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-06 02:42:32.545 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-06 02:42:33.019 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-06 02:42:33.492 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-06 02:42:33.965 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-06 02:42:34.438 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-06 02:42:34.911 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-06 02:42:35.384 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-06 02:42:35.856 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-06 02:42:36.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:36.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:36.016 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:36.016 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:36.016 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:42:36.034 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:36.035 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:36.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:42:36.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:36.036 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:36.036 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:36.036 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:42:36.036 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:42:36.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:36.101 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:42:36.102 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:42:36.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:36.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:36.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:36.329 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-06 02:42:36.802 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-06 02:42:37.273 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-06 02:42:37.745 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-06 02:42:38.219 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-06 02:42:38.691 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-06 02:42:39.162 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-06 02:42:39.636 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-06 02:42:40.108 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-03-06 02:42:40.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:40.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:40.288 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:40.289 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:40.289 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:42:40.309 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:40.309 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:40.309 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:42:40.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:40.311 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:40.311 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:40.311 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:42:40.311 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:42:40.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:40.353 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:42:40.353 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:42:40.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:40.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:40.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:40.580 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-03-06 02:42:41.054 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-03-06 02:42:41.526 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-03-06 02:42:41.998 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-03-06 02:42:42.471 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-03-06 02:42:42.944 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-03-06 02:42:43.417 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-03-06 02:42:43.890 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-03-06 02:42:44.363 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-03-06 02:42:44.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:44.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:44.560 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:44.560 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:44.560 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:42:44.573 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:42:44.574 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:42:44.574 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:42:44.574 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:42:44.576 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:42:44.576 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:42:44.576 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:42:44.576 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:42:44.576 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:42:44.576 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:42:44.576 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:42:44.576 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19530 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:42:44.576 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19530 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:42:44.576 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19530 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:42:44.576 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19530 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:42:44.576 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19530 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:42:44.576 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19530 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:42:44.576 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19530 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:42:49.580 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:42:49.580 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:42:49.580 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:42:49.580 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:42:49.580 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:42:49.580 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:42:49.590 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:42:49.592 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:42:49.592 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:42:49.593 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:42:49.593 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:42:49.598 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:42:49.598 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:42:49.598 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:42:49.599 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:42:49.599 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:42:49.599 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:42:49.600 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:42:49.600 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:42:49.600 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:42:49.603 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:42:49.603 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:42:49.603 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:42:49.603 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:42:49.603 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:42:49.604 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:42:49.604 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:42:49.604 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:42:49.604 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:42:49.608 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:42:49.608 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:42:49.608 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:42:49.608 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:42:49.608 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:42:49.608 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:42:49.608 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:42:49.608 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:42:49.609 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:42:49.613 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:42:49.613 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:42:49.613 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:42:49.613 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:42:49.613 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:42:49.613 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:42:49.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:42:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:42:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:42:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:42:49.614 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:42:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:42:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:42:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:42:49.614 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:42:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:42:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:42:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:42:49.614 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:42:49.614 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:42:49.614 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:42:49.614 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:42:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:42:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:42:49.614 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:42:49.615 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:42:49.615 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:42:49.615 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:42:49.616 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:42:49.616 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:42:49.616 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:42:49.616 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:42:49.616 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:42:49.616 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:42:49.616 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:42:54.624 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:42:54.624 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:42:54.624 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:42:54.624 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:42:54.624 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:42:54.624 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:42:54.632 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:42:54.633 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:42:54.634 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:42:54.634 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:42:54.634 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:42:54.638 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:42:54.638 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:42:54.639 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:42:54.639 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:42:54.639 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:42:54.640 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:42:54.640 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:42:54.640 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:42:54.641 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:42:54.642 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:42:54.642 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:42:54.642 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:42:54.642 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:42:54.642 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:42:54.642 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:42:54.643 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:42:54.643 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:42:54.643 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:42:54.645 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:42:54.645 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:42:54.645 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:42:54.645 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:42:54.645 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:42:54.645 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:42:54.645 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:42:54.646 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:42:54.646 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:42:54.648 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:42:54.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:42:54.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:42:54.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:42:54.649 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:42:54.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:42:54.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:42:54.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:42:54.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:42:54.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:42:54.649 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:42:54.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:42:54.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:42:54.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:42:54.649 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:42:54.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:42:54.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:42:54.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:42:54.649 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:42:54.649 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:42:54.649 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:42:54.649 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:42:54.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:42:54.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:42:54.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:42:54.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:42:54.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:42:54.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:42:54.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:42:54.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:42:54.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:42:54.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:42:54.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:42:54.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:42:54.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:42:54.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:42:54.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:42:54.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:42:54.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:42:54.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:42:54.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:42:54.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:42:54.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:42:54.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:42:54.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:42:54.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:42:54.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:42:54.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:42:54.654 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:42:55.132 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:42:55.179 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:42:55.181 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:42:55.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:55.184 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:42:55.205 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:55.205 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:55.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:42:55.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:55.213 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:55.213 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:55.213 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:42:55.214 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:42:55.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:55.234 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:55.235 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:55.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:55.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:55.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:55.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:55.338 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:55.338 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:55.356 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:55.356 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:55.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:42:55.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:55.359 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:55.359 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:55.359 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:42:55.359 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:42:55.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:55.408 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:55.409 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:55.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:55.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:55.605 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:42:55.654 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:42:55.654 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:42:55.654 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:42:55.654 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:42:55.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:55.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:55.828 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:55.828 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:55.837 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:55.837 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:55.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:42:55.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:55.839 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:55.839 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:55.839 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:42:55.839 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:42:55.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:55.894 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:55.894 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:55.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:55.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:56.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:56.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:56.044 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:56.045 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:56.063 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:56.063 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:56.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:42:56.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:56.066 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:56.066 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:56.066 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:42:56.067 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:42:56.075 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:42:56.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:56.115 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:56.115 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:56.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:56.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:56.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:56.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:56.533 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:56.534 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:56.543 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:56.543 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:56.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:42:56.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:56.544 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:56.544 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:56.544 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:42:56.544 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:42:56.546 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:42:56.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:56.599 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:56.600 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:56.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:56.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:56.654 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:42:56.655 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:42:56.655 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:42:56.655 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:42:57.018 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:42:57.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:57.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:57.055 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:57.055 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:57.073 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:57.073 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:57.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:42:57.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:57.075 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:57.075 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:57.075 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:42:57.075 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:42:57.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:57.123 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:42:57.123 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-06 02:42:57.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:57.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:57.491 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:42:57.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:57.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:57.595 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:57.595 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:57.595 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:42:57.611 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:57.611 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:57.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:42:57.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:57.615 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:57.615 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:57.615 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:42:57.615 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:42:57.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:57.656 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:42:57.656 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:42:57.656 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:42:57.656 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:42:57.663 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:42:57.663 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-06 02:42:57.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:57.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:57.963 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:42:58.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:58.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:58.141 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:58.141 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:58.141 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:42:58.159 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:58.159 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:58.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:42:58.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:58.161 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:58.161 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:58.161 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:42:58.161 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:42:58.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:42:58.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:58.212 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:58.213 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:58.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:58.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:58.435 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:42:58.657 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:42:58.657 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:42:58.657 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:42:58.657 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:42:58.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:58.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:58.681 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:58.681 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:58.697 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:58.697 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:58.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:42:58.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:58.699 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:58.699 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:58.699 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:42:58.699 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:42:58.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:58.747 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:58.747 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:58.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:58.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:58.906 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:42:59.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:59.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:59.221 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:59.221 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:59.238 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:42:59.238 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:42:59.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:42:59.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:59.240 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:59.241 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:59.241 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:42:59.241 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:42:59.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:42:59.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:42:59.295 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:42:59.296 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:42:59.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:59.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:42:59.377 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:42:59.658 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:42:59.658 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:42:59.658 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:42:59.658 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:42:59.850 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:43:00.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:00.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:00.121 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:00.121 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:00.138 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:00.138 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:00.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:00.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:00.140 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:00.140 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:00.140 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:00.140 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:00.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:00.191 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:43:00.191 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:43:00.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:00.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:00.323 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:43:00.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:00.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:00.607 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:00.607 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:00.607 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:43:00.626 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:00.626 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:00.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:00.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:00.628 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:00.628 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:00.628 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:00.628 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:00.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:00.664 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:43:00.664 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:43:00.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:00.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:00.795 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:43:01.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:01.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:01.147 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:01.147 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:01.147 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:43:01.165 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:01.165 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:01.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:01.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:01.167 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:01.167 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:01.167 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:01.167 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:01.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:01.217 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:43:01.217 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:43:01.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:01.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:01.267 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:43:01.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:01.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:01.424 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:01.424 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:01.424 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:43:01.435 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:01.435 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:01.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:01.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:01.436 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:01.436 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:01.436 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:01.436 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:01.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:01.487 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:43:01.487 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:43:01.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:01.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:01.739 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:43:01.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:01.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:01.914 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:01.914 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:01.914 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:43:01.930 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:01.930 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:01.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:01.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:01.933 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:01.933 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:01.933 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:01.933 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:01.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:01.984 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:43:01.984 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:43:01.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:01.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:02.211 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:43:02.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:02.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:02.409 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:02.409 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:02.409 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:43:02.419 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:02.419 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:02.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:02.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:02.421 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:02.421 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:02.421 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:02.421 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:02.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:02.477 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:43:02.477 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:43:02.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:02.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:02.683 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:43:02.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:02.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:02.896 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:02.896 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:02.896 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:43:02.915 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:02.915 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:02.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:02.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:02.918 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:02.918 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:02.918 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:02.918 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:02.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:02.972 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:43:02.972 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:43:02.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:02.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:03.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:03.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:03.077 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:03.077 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:03.077 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:43:03.095 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:03.095 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:03.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:03.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:03.097 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:03.098 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:03.098 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:03.098 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:03.153 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:43:03.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:03.161 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:43:03.161 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:43:03.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:03.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:03.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:03.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:03.566 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:03.566 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:03.566 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:43:03.576 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:03.576 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:03.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:03.577 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:03.577 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:03.577 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:03.577 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:03.577 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:03.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:03.626 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:43:03.626 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:43:03.626 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:43:03.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:03.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:04.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:04.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:04.055 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:04.055 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:04.055 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:43:04.064 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:04.064 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:04.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:04.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:04.066 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:04.066 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:04.066 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:04.066 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:04.098 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:43:04.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:04.115 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:43:04.116 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:43:04.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:04.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:04.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:04.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:04.544 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:04.544 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:04.544 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:43:04.549 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:43:04.549 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:43:04.549 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:43:04.549 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:43:04.550 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:43:04.550 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:43:04.550 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:43:04.550 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:43:04.550 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:43:04.550 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:43:04.550 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:43:09.557 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:43:09.557 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:43:09.557 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:43:09.557 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:43:09.557 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:43:09.557 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:43:09.565 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:43:09.567 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:43:09.567 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:43:09.567 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:43:09.567 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:43:09.570 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:43:09.570 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:43:09.570 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:43:09.570 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:43:09.571 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:43:09.571 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:43:09.571 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:43:09.571 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:43:09.571 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:43:09.572 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:43:09.572 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:43:09.572 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:43:09.573 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:43:09.573 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:43:09.573 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:43:09.573 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:43:09.573 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:43:09.573 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:43:09.574 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:43:09.575 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:43:09.575 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:43:09.575 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:43:09.575 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:43:09.575 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:43:09.575 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:43:09.575 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:43:09.575 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:43:09.577 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:43:09.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:43:09.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:43:09.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:43:09.577 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:43:09.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:43:09.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:43:09.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:43:09.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:43:09.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:43:09.577 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:43:09.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:43:09.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:43:09.577 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:43:09.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:43:09.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:43:09.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:43:09.577 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:43:09.577 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:43:09.578 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:43:09.578 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:43:09.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:43:09.582 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:43:10.061 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:43:10.099 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:43:10.100 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:43:10.101 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:43:10.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:10.120 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:10.121 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:10.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:10.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:10.129 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:10.129 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:10.129 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:10.129 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:10.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:10.164 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:10.164 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:10.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:10.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:10.533 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:43:10.580 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:43:10.580 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:43:10.580 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:43:10.580 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:43:10.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:10.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:11.004 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:43:11.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:11.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:11.209 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:11.209 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:11.226 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:11.226 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:11.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:11.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:11.229 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:11.229 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:11.229 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:11.229 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:11.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:11.279 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:11.280 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:11.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:11.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:11.478 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:43:11.580 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:43:11.581 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:43:11.581 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:43:11.581 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:43:11.950 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:43:12.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:12.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:12.422 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:43:12.582 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:43:12.582 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:43:12.582 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:43:12.582 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:43:12.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:12.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:12.643 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:12.644 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:12.652 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:12.652 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:12.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:12.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:12.654 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:12.654 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:12.654 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:12.654 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:12.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:12.709 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:12.709 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:12.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:12.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:12.893 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:43:13.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:13.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:13.364 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:43:13.583 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:43:13.584 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:43:13.584 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:43:13.584 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:43:13.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:13.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:13.803 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:13.803 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:13.820 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:13.820 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:13.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:13.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:13.822 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:13.822 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:13.822 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:13.822 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:13.837 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:43:13.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:13.871 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:13.871 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:13.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:13.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:14.310 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:43:14.585 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:43:14.585 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:43:14.585 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:43:14.585 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:43:14.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:14.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:14.782 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:43:15.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:15.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:15.240 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:15.240 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:15.255 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:43:15.257 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:15.257 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:15.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:15.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:15.260 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:15.260 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:15.260 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:15.260 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:15.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:15.315 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:15.316 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:15.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:15.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:15.728 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:43:16.200 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:43:16.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:16.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:16.671 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:43:16.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:16.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:16.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:16.801 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:16.818 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:16.818 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:16.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:16.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:16.820 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:16.820 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:16.821 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:16.821 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:16.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:16.872 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:43:16.872 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-06 02:43:16.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:16.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:17.145 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:43:17.618 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:43:17.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:17.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:18.090 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:43:18.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:18.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:18.307 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:18.307 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:18.307 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:43:18.307 [WARNING] transceiver.py:257 (MS@172.18.59.22:6700) RX TRXD message (fn=1885 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:43:18.325 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:18.325 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:18.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:18.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:18.328 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:18.328 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:18.328 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:18.328 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:18.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:18.379 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:43:18.379 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-06 02:43:18.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:18.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:18.564 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:43:19.036 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:43:19.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:19.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:19.508 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:43:19.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:19.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:19.814 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:19.814 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:19.814 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:43:19.831 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:19.831 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:19.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:19.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:19.833 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:19.833 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:19.833 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:19.833 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:19.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:43:19.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:19.889 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:19.890 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:19.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:19.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:19.981 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:43:20.454 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:43:20.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:20.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:20.926 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:43:21.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:21.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:21.320 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:21.320 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:21.338 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:21.338 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:21.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:21.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:21.340 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:21.340 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:21.341 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:21.341 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:21.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:21.399 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:43:21.405 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:21.405 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:21.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:21.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:21.872 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:43:22.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:22.344 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:43:22.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:22.815 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:43:22.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:22.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:22.824 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:22.824 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:22.841 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:22.841 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:22.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:22.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:22.844 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:22.844 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:22.844 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:22.844 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:22.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:43:22.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:22.897 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:22.898 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:22.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:22.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:23.288 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:43:23.761 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:43:24.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:24.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:24.234 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:43:24.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:24.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:24.692 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:24.692 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:24.707 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:43:24.709 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:24.709 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:24.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:24.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:24.712 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:24.712 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:24.712 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:24.712 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:24.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:24.767 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:43:24.767 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:43:24.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:24.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:25.180 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:43:25.652 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:43:25.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:25.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:26.125 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:43:26.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:26.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:26.139 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:26.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:26.139 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:43:26.158 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:26.158 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:26.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:26.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:26.161 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:26.161 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:26.161 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:26.161 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:26.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:26.212 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:43:26.212 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:43:26.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:26.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:26.597 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:43:27.070 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:43:27.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:27.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:27.544 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:43:27.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:27.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:27.645 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:27.645 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:27.645 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:43:27.664 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:27.664 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:27.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:27.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:27.666 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:27.666 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:27.666 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:27.666 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:27.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:27.715 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:43:27.715 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:43:27.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:27.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:28.017 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:43:28.490 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:43:28.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:28.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:28.963 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:43:29.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:29.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:29.118 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:29.118 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:29.118 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:43:29.127 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:29.127 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:29.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:29.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:29.129 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:29.129 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:29.129 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:29.129 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:29.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:29.180 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:43:29.181 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:43:29.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:29.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:29.435 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:43:29.906 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:43:30.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:30.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:30.379 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 02:43:30.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:30.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:30.554 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:30.554 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:30.555 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:43:30.564 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:30.564 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:30.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:30.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:30.566 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:30.566 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:30.566 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:30.566 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:30.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:30.622 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:43:30.622 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:43:30.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:30.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:30.852 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 02:43:31.325 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 02:43:31.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:31.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:31.798 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 02:43:31.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:31.989 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:31.990 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:31.990 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:31.990 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:43:31.999 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:31.999 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:31.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:32.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:32.001 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:32.001 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:32.001 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:32.001 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:32.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:32.051 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:43:32.051 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:43:32.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:32.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:32.270 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 02:43:32.742 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 02:43:32.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:32.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:33.215 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 02:43:33.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:33.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:33.426 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:33.426 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:33.426 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:43:33.435 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:33.435 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:33.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:33.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:33.436 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:33.437 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:33.437 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:33.437 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:33.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:33.492 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:43:33.492 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:43:33.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:33.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:33.688 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 02:43:34.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:34.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:34.160 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 02:43:34.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:34.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:34.552 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:34.553 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:34.553 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:43:34.553 [WARNING] transceiver.py:257 (MS@172.18.59.22:6700) RX TRXD message (fn=5391 tn=3 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:43:34.572 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:34.572 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:34.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:34.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:34.574 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:34.574 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:34.575 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:34.575 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:34.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:34.632 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 02:43:34.640 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:43:34.640 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:43:34.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:34.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:35.106 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 02:43:35.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:35.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:35.579 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 02:43:35.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:35.990 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:35.991 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:35.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:35.991 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:43:35.999 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:35.999 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:35.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:36.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:36.001 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:36.001 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:36.001 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:36.001 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:36.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:36.052 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 02:43:36.058 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:43:36.058 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:43:36.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:36.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:36.524 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 02:43:36.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:36.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:36.996 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 02:43:37.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:37.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:37.427 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:37.427 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:37.427 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:43:37.436 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:37.436 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:37.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:37.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:37.438 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:37.438 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:37.438 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:37.438 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:37.468 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 02:43:37.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:37.490 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:43:37.490 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:43:37.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:37.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:37.942 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 02:43:38.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:38.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:38.414 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 02:43:38.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:38.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:38.864 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:38.864 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:38.864 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:43:38.874 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:43:38.874 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:43:38.874 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:43:38.874 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:43:38.878 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:43:38.878 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:43:38.878 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:43:38.878 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:43:38.878 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:43:38.878 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:43:38.878 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:43:38.878 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6324 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:43:38.878 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6324 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:43:38.878 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6324 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:43:38.878 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6324 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:43:38.878 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6324 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:43:38.878 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6324 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:43:43.885 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:43:43.885 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:43:43.885 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:43:43.885 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:43:43.885 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:43:43.885 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:43:43.894 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:43:43.895 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:43:43.895 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:43:43.895 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:43:43.895 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:43:43.898 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:43:43.898 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:43:43.898 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:43:43.898 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:43:43.899 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:43:43.899 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:43:43.899 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:43:43.899 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:43:43.899 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:43:43.901 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:43:43.901 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:43:43.901 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:43:43.901 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:43:43.901 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:43:43.901 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:43:43.901 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:43:43.901 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:43:43.901 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:43:43.903 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:43:43.903 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:43:43.903 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:43:43.903 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:43:43.903 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:43:43.903 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:43:43.903 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:43:43.904 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:43:43.904 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:43:43.906 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:43:43.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:43:43.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:43:43.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:43:43.906 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:43:43.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:43:43.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:43:43.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:43:43.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:43:43.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:43:43.907 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:43:43.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:43:43.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:43:43.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:43:43.907 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:43:43.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:43:43.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:43:43.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:43:43.907 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:43:43.907 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:43:43.907 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:43:43.907 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:43:43.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:43:43.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:43:43.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:43:43.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:43:43.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:43:43.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:43:43.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:43:43.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:43:43.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:43:43.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:43:43.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:43:43.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:43:43.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:43:43.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:43:43.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:43:43.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:43:43.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:43:43.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:43:43.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:43:43.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:43:43.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:43:43.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:43:43.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:43:43.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:43:43.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:43:43.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:43:43.912 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:43:44.391 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:43:44.429 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:43:44.430 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:43:44.431 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:43:44.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:44.443 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:44.443 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:44.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:44.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:44.445 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:44.445 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:44.445 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:44.445 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:44.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:44.494 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:44.495 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:44.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:44.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:44.864 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:43:44.909 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:43:44.910 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:43:44.910 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:43:44.911 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:43:45.335 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:43:45.808 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:43:45.910 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:43:45.911 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:43:45.911 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:43:45.911 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:43:46.281 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:43:46.753 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:43:46.911 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:43:46.912 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:43:46.912 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:43:46.912 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:43:47.224 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:43:47.698 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:43:47.913 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:43:47.913 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:43:47.913 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:43:47.913 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:43:48.170 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:43:48.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:48.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:48.375 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:48.375 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:48.391 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:48.391 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:48.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:48.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:48.394 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:48.394 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:48.394 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:48.394 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:48.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:48.446 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:48.446 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:48.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:48.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:48.641 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:43:48.914 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:43:48.914 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:43:48.914 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:43:48.915 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:43:49.113 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:43:49.586 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:43:50.059 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:43:50.531 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:43:51.002 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:43:51.475 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:43:51.948 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:43:52.420 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:43:52.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:52.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:52.642 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:52.642 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:52.660 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:52.660 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:52.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:52.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:52.663 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:52.663 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:52.663 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:52.663 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:52.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:52.712 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:52.713 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:52.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:52.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:52.891 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:43:53.362 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:43:53.835 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:43:54.308 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:43:54.780 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:43:55.254 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:43:55.726 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:43:56.198 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:43:56.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:56.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:56.637 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:56.637 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:56.652 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:43:56.652 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:43:56.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:43:56.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:56.654 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:56.654 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:56.654 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:43:56.654 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:43:56.668 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:43:56.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:43:56.703 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:43:56.704 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:43:56.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:56.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:43:57.140 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:43:57.613 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:43:58.085 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:43:58.557 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:43:59.028 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:43:59.502 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:43:59.975 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:44:00.447 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:44:00.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:00.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:00.905 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:00.905 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:00.917 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:44:00.923 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:00.923 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:00.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:44:00.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:00.926 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:44:00.926 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:44:00.926 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:44:00.926 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:44:00.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:00.975 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:44:00.975 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:44:00.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:00.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:01.389 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:44:01.862 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:44:02.335 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:44:02.807 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:44:03.278 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:44:03.752 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:44:04.224 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:44:04.697 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 02:44:05.170 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 02:44:05.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:05.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:05.574 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:05.574 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:05.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:05.589 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:05.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:44:05.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:05.591 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:44:05.591 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:44:05.591 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:44:05.591 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:44:05.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:05.642 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 02:44:05.645 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:44:05.645 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-06 02:44:05.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:05.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:06.115 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 02:44:06.589 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 02:44:07.062 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 02:44:07.536 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 02:44:08.009 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 02:44:08.482 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 02:44:08.955 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 02:44:09.428 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 02:44:09.901 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 02:44:09.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:09.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:09.980 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:09.980 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:09.980 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:44:09.996 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:09.996 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:09.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:44:09.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:09.999 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:44:09.999 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:44:09.999 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:44:09.999 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:44:10.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:10.047 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:44:10.047 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-06 02:44:10.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:10.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:10.373 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 02:44:10.846 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 02:44:11.318 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 02:44:11.792 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 02:44:12.264 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 02:44:12.736 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 02:44:13.210 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 02:44:13.682 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 02:44:14.154 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 02:44:14.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:14.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:14.377 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:14.377 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:14.377 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:44:14.377 [WARNING] transceiver.py:257 (MS@172.18.59.22:6700) RX TRXD message (fn=6578 tn=6 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:44:14.394 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:14.394 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:14.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:44:14.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:14.396 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:44:14.396 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:44:14.396 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:44:14.396 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:44:14.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:44:14.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:14.448 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:44:14.448 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:44:14.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:14.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:14.626 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 02:44:15.099 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 02:44:15.572 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 02:44:16.044 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 02:44:16.515 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 02:44:16.989 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 02:44:17.461 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 02:44:17.933 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 02:44:18.404 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 02:44:18.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:18.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:18.770 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:18.770 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:18.787 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:18.787 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:18.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:44:18.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:18.789 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:44:18.790 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:44:18.790 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:44:18.790 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:44:18.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:18.840 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:44:18.840 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:44:18.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:18.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:18.877 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-06 02:44:19.350 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-06 02:44:19.822 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-06 02:44:20.293 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-06 02:44:20.764 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-06 02:44:21.235 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-06 02:44:21.705 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-06 02:44:22.179 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-06 02:44:22.651 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-06 02:44:23.124 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-06 02:44:23.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:23.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:23.163 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:23.163 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:23.183 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:23.183 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:23.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:44:23.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:23.187 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:44:23.187 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:44:23.187 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:44:23.187 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:44:23.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:44:23.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:23.236 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:44:23.236 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:44:23.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:23.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:23.597 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-06 02:44:24.070 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-06 02:44:24.542 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-06 02:44:25.016 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-06 02:44:25.489 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-06 02:44:25.962 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-06 02:44:26.435 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-06 02:44:26.909 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-06 02:44:27.381 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-06 02:44:27.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:27.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:27.444 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:27.444 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:27.461 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:27.461 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:27.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:44:27.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:27.464 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:44:27.464 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:44:27.464 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:44:27.464 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:44:27.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:27.515 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:44:27.516 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:44:27.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:27.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:27.854 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-06 02:44:28.324 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-06 02:44:28.798 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-06 02:44:29.270 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-06 02:44:29.743 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-06 02:44:30.217 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-06 02:44:30.690 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-06 02:44:31.163 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-06 02:44:31.636 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-06 02:44:31.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:31.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:31.782 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:31.782 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:31.782 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:44:31.799 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:31.799 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:31.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:44:31.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:31.801 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:44:31.801 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:44:31.802 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:44:31.802 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:44:31.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:31.852 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:44:31.852 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:44:31.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:31.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:32.108 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-06 02:44:32.581 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-06 02:44:33.054 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-06 02:44:33.527 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-06 02:44:34.001 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-06 02:44:34.473 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-06 02:44:34.946 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-06 02:44:35.419 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-06 02:44:35.891 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-06 02:44:36.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:36.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:36.179 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:36.179 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:36.179 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:44:36.198 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:36.198 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:36.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:44:36.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:36.201 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:44:36.201 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:44:36.201 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:44:36.201 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:44:36.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:36.252 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:44:36.252 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:44:36.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:36.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:36.364 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-06 02:44:36.837 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-06 02:44:37.310 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-06 02:44:37.784 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-06 02:44:38.256 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-06 02:44:38.728 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-06 02:44:39.202 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-06 02:44:39.674 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-06 02:44:40.154 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-06 02:44:40.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:40.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:40.312 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:40.312 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:40.312 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:44:40.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:40.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:40.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:44:40.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:40.333 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:44:40.333 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:44:40.333 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:44:40.333 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:44:40.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:40.384 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:44:40.384 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:44:40.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:40.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:40.626 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-06 02:44:41.098 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-06 02:44:41.571 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-06 02:44:42.043 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-06 02:44:42.517 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-06 02:44:42.989 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-06 02:44:43.462 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-06 02:44:43.935 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-06 02:44:44.407 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-06 02:44:44.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:44.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:44.585 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:44.585 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:44.585 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:44:44.603 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:44.603 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:44.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:44:44.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:44.606 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:44:44.606 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:44:44.606 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:44:44.606 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:44:44.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:44.691 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:44:44.691 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:44:44.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:44.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:44.877 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-06 02:44:45.349 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-06 02:44:45.821 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-06 02:44:46.294 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-06 02:44:46.768 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-06 02:44:47.240 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-06 02:44:47.714 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-06 02:44:48.186 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-06 02:44:48.658 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-06 02:44:48.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:48.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:48.854 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:48.854 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:48.854 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:44:48.870 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:48.870 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:48.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:44:48.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:48.872 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:44:48.873 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:44:48.873 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:44:48.873 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:44:48.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:48.925 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:44:48.925 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:44:48.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:48.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:49.131 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-06 02:44:49.605 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-06 02:44:50.077 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-06 02:44:50.551 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-06 02:44:51.023 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-06 02:44:51.496 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-06 02:44:51.969 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-06 02:44:52.442 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-06 02:44:52.913 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-06 02:44:53.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:53.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:53.128 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:53.128 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:53.128 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:44:53.147 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:53.147 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:53.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:44:53.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:53.149 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:44:53.149 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:44:53.150 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:44:53.150 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:44:53.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:53.205 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:44:53.205 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:44:53.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:53.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:53.385 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-06 02:44:53.856 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-06 02:44:54.330 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-06 02:44:54.801 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-06 02:44:55.273 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-06 02:44:55.746 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-06 02:44:56.219 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-06 02:44:56.691 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-06 02:44:57.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:57.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:57.084 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:57.084 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:57.084 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:44:57.103 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:44:57.103 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:44:57.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:44:57.106 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:57.106 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:44:57.106 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:44:57.106 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:44:57.106 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:44:57.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:44:57.164 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-06 02:44:57.168 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:44:57.168 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:44:57.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:57.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:44:57.637 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-06 02:44:58.109 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-06 02:44:58.583 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-06 02:44:59.056 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-06 02:44:59.530 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-06 02:45:00.002 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-06 02:45:00.475 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-06 02:45:00.948 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-06 02:45:01.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:45:01.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:01.361 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:45:01.362 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:45:01.362 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:45:01.380 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:45:01.380 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:45:01.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:45:01.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:01.382 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:45:01.382 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:45:01.383 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:45:01.383 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:45:01.420 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-06 02:45:01.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:45:01.431 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:45:01.432 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:45:01.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:01.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:01.891 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-06 02:45:02.365 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-06 02:45:02.837 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-06 02:45:03.310 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-06 02:45:03.782 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-06 02:45:04.256 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-06 02:45:04.728 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-06 02:45:05.201 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-06 02:45:05.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:45:05.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:05.628 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:45:05.628 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:45:05.628 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:45:05.647 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:45:05.647 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:45:05.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:45:05.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:05.650 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:45:05.650 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:45:05.650 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:45:05.650 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:45:05.674 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-06 02:45:05.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:45:05.700 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:45:05.701 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:45:05.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:05.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:06.146 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-06 02:45:06.620 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-06 02:45:07.093 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-06 02:45:07.564 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-06 02:45:08.036 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-06 02:45:08.509 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-06 02:45:08.981 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-06 02:45:09.454 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-06 02:45:09.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:45:09.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:09.901 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:45:09.901 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:45:09.901 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:45:09.916 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:45:09.917 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:45:09.917 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:45:09.917 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:45:09.918 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:45:09.918 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:45:09.918 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:45:09.918 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:45:09.918 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:45:09.918 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:45:09.918 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:45:09.918 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=18565 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:45:09.918 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=18565 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:45:09.918 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=18565 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:45:09.918 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=18565 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:45:14.928 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:45:14.928 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:45:14.928 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:45:14.928 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:45:14.929 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:45:14.929 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:45:14.941 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:45:14.942 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:45:14.942 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:45:14.942 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:45:14.942 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:45:14.943 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:45:14.944 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:45:14.944 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:45:14.944 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:45:14.944 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:45:14.944 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:45:14.944 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:45:14.944 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:45:14.944 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:45:14.945 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:45:14.945 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:45:14.945 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:45:14.945 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:45:14.945 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:45:14.945 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:45:14.945 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:45:14.945 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:45:14.945 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:45:14.946 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:45:14.947 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:45:14.947 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:45:14.947 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:45:14.947 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:45:14.947 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:45:14.947 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:45:14.947 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:45:14.947 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:45:14.948 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:45:14.949 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:45:14.949 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:45:14.949 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:45:14.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:45:14.950 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:45:14.950 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:45:14.950 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:45:14.950 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:45:14.950 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:45:14.950 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:45:14.950 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:45:19.958 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:45:19.958 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:45:19.958 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:45:19.958 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:45:19.958 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:45:19.958 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:45:19.968 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:45:19.969 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:45:19.969 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:45:19.970 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:45:19.970 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:45:19.973 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:45:19.973 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:45:19.974 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:45:19.974 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:45:19.974 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:45:19.974 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:45:19.975 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:45:19.975 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:45:19.975 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:45:19.976 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:45:19.976 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:45:19.976 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:45:19.976 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:45:19.977 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:45:19.977 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:45:19.977 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:45:19.977 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:45:19.977 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:45:19.979 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:45:19.979 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:45:19.979 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:45:19.979 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:45:19.979 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:45:19.979 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:45:19.979 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:45:19.979 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:45:19.979 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:45:19.982 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:45:19.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:45:19.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:45:19.982 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:45:19.982 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:45:19.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:45:19.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:45:19.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:45:19.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:45:19.982 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:45:19.982 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:45:19.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:45:19.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:45:19.982 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:45:19.982 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:45:19.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:45:19.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:45:19.982 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:45:19.982 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:45:19.982 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:45:19.982 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:45:19.982 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:45:19.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:45:19.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:45:19.982 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:45:19.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:45:19.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:45:19.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:45:19.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:45:19.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:45:19.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:45:19.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:45:19.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:45:19.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:45:19.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:45:19.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:45:19.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:45:19.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:45:19.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:45:19.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:45:19.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:45:19.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:45:19.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:45:19.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:45:19.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:45:19.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:45:19.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:45:19.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:45:19.987 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:45:20.464 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:45:20.508 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:45:20.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:45:20.509 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:45:20.510 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:45:20.525 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:45:20.525 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:45:20.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:45:20.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:20.533 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:45:20.533 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:45:20.533 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:45:20.533 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:45:20.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:45:20.567 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:45:20.567 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:45:20.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:20.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:20.935 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:45:20.984 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:45:20.985 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:45:20.985 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:45:20.985 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:45:21.407 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:45:21.880 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:45:21.985 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:45:21.986 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:45:21.986 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:45:21.986 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:45:22.353 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:45:22.825 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:45:22.986 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:45:22.986 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:45:22.987 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:45:22.987 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:45:23.297 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:45:23.768 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:45:23.988 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:45:23.988 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:45:23.988 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:45:23.988 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:45:24.242 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:45:24.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:45:24.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:24.613 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:45:24.613 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:45:24.628 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:45:24.628 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:45:24.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:45:24.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:24.630 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:45:24.630 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:45:24.630 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:45:24.630 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:45:24.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:45:24.679 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:45:24.680 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:45:24.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:24.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:24.714 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:45:24.988 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:45:24.989 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:45:24.989 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:45:24.989 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:45:25.186 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:45:25.657 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:45:26.131 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:45:26.603 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:45:27.075 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:45:27.546 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:45:28.019 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:45:28.492 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:45:28.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:45:28.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:28.880 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:45:28.880 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:45:28.891 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:45:28.891 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:45:28.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:45:28.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:28.894 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:45:28.894 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:45:28.894 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:45:28.894 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:45:28.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:45:28.944 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:45:28.957 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:45:28.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:28.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:28.964 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:45:29.435 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:45:29.906 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:45:30.377 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:45:30.850 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:45:31.322 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:45:31.795 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:45:32.265 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:45:32.736 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:45:33.210 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:45:33.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:45:33.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:33.346 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:45:33.346 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:45:33.362 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:45:33.363 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:45:33.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:45:33.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:33.365 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:45:33.365 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:45:33.365 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:45:33.365 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:45:33.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:45:33.415 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:45:33.415 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:45:33.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:33.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:33.682 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:45:34.154 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:45:34.625 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:45:35.099 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:45:35.571 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:45:36.043 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:45:36.514 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:45:36.985 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:45:37.458 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:45:37.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:45:37.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:37.612 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:45:37.612 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:45:37.612 [WARNING] transceiver.py:257 (MS@172.18.59.22:6700) RX TRXD message (fn=3810 tn=1 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:45:37.628 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:45:37.628 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:45:37.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:45:37.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:37.631 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:45:37.631 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:45:37.631 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:45:37.631 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:45:37.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:45:37.679 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:45:37.679 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:45:37.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:37.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:37.931 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:45:38.403 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:45:38.877 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:45:39.350 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:45:39.822 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:45:40.293 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:45:40.766 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 02:45:41.238 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 02:45:41.710 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 02:45:42.184 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 02:45:42.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:45:42.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:42.235 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:45:42.235 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:45:42.250 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:45:42.251 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:45:42.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:45:42.253 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:42.253 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:45:42.253 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:45:42.253 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:45:42.253 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:45:42.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:45:42.304 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:45:42.304 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-06 02:45:42.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:42.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:42.656 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 02:45:43.129 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 02:45:43.602 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 02:45:44.075 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 02:45:44.548 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 02:45:45.021 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 02:45:45.494 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 02:45:45.966 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 02:45:46.439 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 02:45:46.911 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 02:45:47.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:45:47.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:47.121 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:45:47.121 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:45:47.121 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:45:47.140 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:45:47.140 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:45:47.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:45:47.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:47.142 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:45:47.142 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:45:47.142 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:45:47.142 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:45:47.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:45:47.202 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:45:47.202 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-06 02:45:47.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:47.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:47.383 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 02:45:47.857 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 02:45:48.329 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 02:45:48.801 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 02:45:49.275 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 02:45:49.748 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 02:45:50.220 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 02:45:50.693 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 02:45:51.166 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 02:45:51.638 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 02:45:51.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:45:51.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:51.997 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:45:51.997 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:45:51.997 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:45:52.014 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:45:52.014 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:45:52.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:45:52.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:52.016 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:45:52.016 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:45:52.017 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:45:52.017 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:45:52.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:45:52.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:45:52.067 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:45:52.067 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:45:52.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:52.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:52.109 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 02:45:52.583 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 02:45:53.056 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 02:45:53.529 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 02:45:54.002 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 02:45:54.474 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 02:45:54.948 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-06 02:45:55.420 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-06 02:45:55.892 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-06 02:45:56.366 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-06 02:45:56.838 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-06 02:45:56.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:45:56.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:56.874 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:45:56.874 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:45:56.891 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:45:56.891 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:45:56.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:45:56.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:56.893 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:45:56.893 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:45:56.893 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:45:56.893 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:45:56.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:45:56.944 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:45:56.944 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:45:56.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:56.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:45:57.311 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-06 02:45:57.782 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-06 02:45:58.256 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-06 02:45:58.728 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-06 02:45:59.199 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-06 02:45:59.673 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-06 02:46:00.145 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-06 02:46:00.619 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-06 02:46:01.091 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-06 02:46:01.563 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-06 02:46:01.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:46:01.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:01.758 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:46:01.758 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:46:01.774 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:46:01.774 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:46:01.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:46:01.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:01.777 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:46:01.777 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:46:01.777 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:46:01.777 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:46:01.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:46:01.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:46:01.828 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:46:01.828 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:46:01.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:01.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:02.035 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-06 02:46:02.508 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-06 02:46:02.981 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-06 02:46:03.455 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-06 02:46:03.927 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-06 02:46:04.398 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-06 02:46:04.872 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-06 02:46:05.345 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-06 02:46:05.817 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-06 02:46:06.291 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-06 02:46:06.763 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-06 02:46:06.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:46:06.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:06.998 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:46:06.998 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:46:07.016 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:46:07.016 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:46:07.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:46:07.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:07.018 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:46:07.018 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:46:07.018 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:46:07.018 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:46:07.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:46:07.067 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:46:07.067 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:46:07.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:07.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:07.234 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-06 02:46:07.707 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-06 02:46:08.180 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-06 02:46:08.652 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-06 02:46:09.124 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-06 02:46:09.594 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-06 02:46:10.067 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-06 02:46:10.540 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-06 02:46:11.012 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-06 02:46:11.485 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-06 02:46:11.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:46:11.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:11.816 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:46:11.816 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:46:11.816 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:46:11.832 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:46:11.832 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:46:11.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:46:11.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:11.834 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:46:11.834 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:46:11.834 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:46:11.834 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:46:11.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:46:11.884 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:46:11.884 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:46:11.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:11.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:11.958 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-06 02:46:12.430 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-06 02:46:12.903 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-06 02:46:13.376 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-06 02:46:13.848 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-06 02:46:14.321 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-06 02:46:14.793 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-06 02:46:15.261 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-06 02:46:15.726 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-06 02:46:16.189 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-06 02:46:16.655 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-06 02:46:16.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:46:16.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:16.689 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:46:16.689 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:46:16.689 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:46:16.695 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:46:16.695 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:46:16.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:46:16.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:16.697 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:46:16.697 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:46:16.697 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:46:16.697 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:46:16.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:46:16.744 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:46:16.744 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:46:16.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:16.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:17.118 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-06 02:46:17.582 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-06 02:46:18.045 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-06 02:46:18.509 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-06 02:46:18.973 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-06 02:46:19.437 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-06 02:46:19.900 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-06 02:46:20.364 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-06 02:46:20.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:46:20.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:20.736 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:46:20.736 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:46:20.736 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:46:20.745 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:46:20.745 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:46:20.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:46:20.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:20.749 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:46:20.749 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:46:20.749 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:46:20.749 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:46:20.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:46:20.799 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:46:20.799 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:46:20.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:20.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:20.828 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-06 02:46:21.292 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-06 02:46:21.756 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-06 02:46:22.220 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-06 02:46:22.683 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-06 02:46:23.147 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-06 02:46:23.611 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-06 02:46:24.074 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-06 02:46:24.537 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-06 02:46:24.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:46:24.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:24.927 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:46:24.927 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:46:24.927 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:46:24.933 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:46:24.933 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:46:24.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:46:24.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:24.935 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:46:24.935 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:46:24.935 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:46:24.935 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:46:24.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:46:24.979 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:46:24.979 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:46:24.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:24.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:25.000 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-06 02:46:25.463 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-06 02:46:25.941 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-06 02:46:26.404 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-06 02:46:26.867 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-06 02:46:27.330 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-06 02:46:27.795 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-06 02:46:28.258 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-06 02:46:28.723 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-06 02:46:29.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:46:29.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:29.133 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:46:29.133 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:46:29.133 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:46:29.139 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:46:29.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:46:29.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:46:29.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:29.140 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:46:29.140 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:46:29.140 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:46:29.140 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:46:29.186 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-06 02:46:29.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:46:29.189 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:46:29.189 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:46:29.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:29.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:29.650 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-06 02:46:30.114 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-06 02:46:30.579 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-06 02:46:31.045 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-06 02:46:31.513 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-06 02:46:31.983 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-06 02:46:32.454 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-06 02:46:32.925 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-06 02:46:33.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:46:33.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:33.328 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:46:33.328 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:46:33.328 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:46:33.348 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:46:33.396 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-06 02:46:33.436 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:46:33.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:46:33.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:33.443 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:46:33.444 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:46:33.444 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:46:33.444 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:46:33.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:46:33.516 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:46:33.516 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:46:33.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:33.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:33.908 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-06 02:46:34.381 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-06 02:46:34.853 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-06 02:46:35.326 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-06 02:46:35.839 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-06 02:46:36.311 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-06 02:46:37.043 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-06 02:46:37.514 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-06 02:46:37.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:46:37.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:37.773 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:46:37.773 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:46:37.773 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:46:37.792 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:46:37.792 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:46:37.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:46:37.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:37.794 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:46:37.794 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:46:37.795 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:46:37.795 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:46:37.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:46:37.849 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:46:37.849 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:46:37.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:37.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:37.980 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-06 02:46:38.448 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-06 02:46:38.983 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-06 02:46:39.653 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-06 02:46:40.118 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-06 02:46:40.584 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-06 02:46:41.049 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-06 02:46:41.513 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-06 02:46:41.980 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-06 02:46:42.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:46:42.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:42.194 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:46:42.194 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:46:42.194 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:46:42.209 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:46:42.209 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:46:42.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:46:42.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:42.212 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:46:42.212 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:46:42.212 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:46:42.212 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:46:42.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:46:42.262 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:46:42.262 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:46:42.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:42.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:42.444 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-06 02:46:42.909 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-06 02:46:43.374 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-06 02:46:43.840 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-06 02:46:44.304 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-06 02:46:44.768 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-06 02:46:45.234 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-06 02:46:45.698 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-06 02:46:46.162 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-03-06 02:46:46.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:46:46.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:46.340 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:46:46.340 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:46:46.340 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:46:46.355 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:46:46.355 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:46:46.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:46:46.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:46.357 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:46:46.357 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:46:46.357 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:46:46.357 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:46:46.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:46:46.404 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:46:46.404 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:46:46.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:46.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:46.627 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-03-06 02:46:47.092 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-03-06 02:46:47.557 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-03-06 02:46:48.026 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-03-06 02:46:48.493 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-03-06 02:46:48.957 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-03-06 02:46:49.421 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-03-06 02:46:49.888 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-03-06 02:46:50.354 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-03-06 02:46:50.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:46:50.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:46:50.541 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:46:50.541 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:46:50.541 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:46:50.553 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:46:50.553 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:46:50.553 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:46:50.553 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:46:50.558 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:46:50.559 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:46:50.559 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:46:50.559 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:46:50.559 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:46:50.559 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:46:50.559 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:46:50.559 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19528 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:46:50.560 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19528 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:46:50.560 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19528 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:46:50.560 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19528 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:46:50.560 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19528 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:46:50.560 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19528 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:46:50.560 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19529 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:46:50.560 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19529 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:46:50.560 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19529 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:46:50.560 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19529 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:46:50.560 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19529 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:46:50.561 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19529 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:46:50.561 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19529 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:46:50.561 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=19529 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:46:55.563 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:46:55.563 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:46:55.563 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:46:55.563 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:46:55.564 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:46:55.564 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:46:55.571 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:46:55.571 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:46:55.571 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:46:55.572 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:46:55.572 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:46:55.573 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:46:55.573 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:46:55.573 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:46:55.573 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:46:55.573 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:46:55.573 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:46:55.573 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:46:55.573 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:46:55.573 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:46:55.576 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:46:55.576 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:46:55.576 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:46:55.576 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:46:55.576 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:46:55.576 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:46:55.576 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:46:55.576 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:46:55.576 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:46:55.578 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:46:55.578 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:46:55.578 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:46:55.578 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:46:55.578 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:46:55.578 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:46:55.578 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:46:55.578 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:46:55.578 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:46:55.582 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:46:55.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:46:55.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:46:55.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:46:55.582 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:46:55.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:46:55.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:46:55.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:46:55.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:46:55.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:46:55.582 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:46:55.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:46:55.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:46:55.582 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:46:55.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:46:55.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:46:55.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:46:55.583 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:46:55.583 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:46:55.583 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:46:55.583 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:46:55.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:46:55.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:46:55.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:46:55.584 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:46:55.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:46:55.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:46:55.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:46:55.584 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:46:55.584 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:46:55.584 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:46:55.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:46:55.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:46:55.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:47:00.594 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:47:00.594 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:47:00.594 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:47:00.595 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:47:00.595 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:47:00.595 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:47:00.603 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:47:00.605 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:47:00.605 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:47:00.606 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:47:00.606 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:47:00.611 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:47:00.612 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:47:00.612 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:47:00.613 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:47:00.613 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:47:00.614 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:47:00.614 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:47:00.614 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:47:00.615 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:47:00.616 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:47:00.616 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:47:00.617 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:47:00.617 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:47:00.617 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:47:00.617 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:47:00.618 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:47:00.618 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:47:00.618 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:47:00.620 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:47:00.621 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:47:00.621 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:47:00.621 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:47:00.621 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:47:00.621 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:47:00.621 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:47:00.621 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:47:00.621 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:47:00.622 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:47:00.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:47:00.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:47:00.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:47:00.622 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:47:00.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:47:00.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:47:00.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:47:00.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:47:00.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:47:00.622 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:47:00.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:47:00.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:47:00.623 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:47:00.623 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:47:00.623 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:47:00.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:47:00.627 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:47:01.102 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:47:01.625 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:47:01.753 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:47:01.753 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:47:01.753 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:47:01.763 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:47:01.764 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:47:01.765 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:47:01.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:01.778 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:01.778 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:01.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:01.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:01.782 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:01.782 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:01.782 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:01.782 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:01.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:01.820 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:01.820 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:01.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:01.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:02.223 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:47:02.691 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:47:02.754 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:47:02.755 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:47:02.755 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:47:02.755 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:47:02.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:02.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:02.898 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:02.898 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:02.899 [WARNING] transceiver.py:257 (MS@172.18.59.22:6700) RX TRXD message (fn=353 tn=3 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:47:02.911 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:02.911 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:02.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:02.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:02.922 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:02.922 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:02.922 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:02.922 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:02.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:02.981 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:02.981 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:02.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:02.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:03.158 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:47:03.624 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:47:03.756 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:47:03.759 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:47:03.760 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:47:03.760 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:47:04.090 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:47:04.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:04.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:04.311 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:04.311 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:04.335 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:04.335 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:04.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:04.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:04.337 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:04.337 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:04.337 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:04.337 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:04.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:04.391 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:04.392 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:04.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:04.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:04.568 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:47:04.761 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:47:04.761 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:47:04.761 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:47:04.761 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:47:05.034 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:47:05.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:05.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:05.469 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:05.469 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:05.475 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:05.475 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:05.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:05.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:05.477 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:05.477 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:05.477 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:05.477 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:05.498 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:47:05.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:05.525 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:05.525 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:05.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:05.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:05.762 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:47:05.762 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:47:05.762 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:47:05.762 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:47:05.966 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:47:06.438 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:47:06.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:06.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:06.898 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:06.898 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:06.907 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:47:06.913 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:06.913 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:06.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:06.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:06.916 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:06.916 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:06.916 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:06.916 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:06.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:06.967 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:06.967 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:06.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:06.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:07.372 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:47:07.839 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:47:07.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:07.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:07.957 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:07.957 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:07.972 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:07.972 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:07.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:07.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:07.974 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:07.974 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:07.974 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:07.974 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:08.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:08.033 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:47:08.033 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-06 02:47:08.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:08.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:08.305 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:47:08.771 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:47:08.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:08.970 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:08.970 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:08.970 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:08.970 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:47:08.983 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:08.984 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:08.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:08.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:08.995 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:08.995 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:08.995 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:08.995 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:09.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:09.038 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:47:09.038 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-06 02:47:09.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:09.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:09.237 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:47:09.702 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:47:09.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:09.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:09.980 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:09.980 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:09.980 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:47:09.998 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:09.998 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:09.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:10.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:10.001 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:10.001 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:10.001 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:10.001 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:10.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:47:10.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:10.055 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:10.055 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:10.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:10.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:10.166 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:47:10.632 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:47:10.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:10.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:10.986 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:10.986 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:11.004 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:11.004 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:11.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:11.006 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:11.006 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:11.006 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:11.006 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:11.006 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:11.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:11.055 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:11.055 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:11.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:11.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:11.105 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:47:11.571 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:47:11.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:11.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:11.997 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:11.997 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:12.002 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:12.002 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:12.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:12.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:12.004 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:12.004 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:12.005 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:12.005 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:12.036 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:47:12.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:47:12.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:12.134 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:12.154 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:12.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:12.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:12.597 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:47:13.064 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:47:13.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:13.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:13.466 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:13.466 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:13.478 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:13.478 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:13.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:13.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:13.480 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:13.480 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:13.481 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:13.481 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:13.529 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:47:13.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:13.533 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:47:13.533 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:47:13.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:13.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:13.995 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:47:14.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:14.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:14.412 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:14.412 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:14.412 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:47:14.426 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:14.426 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:14.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:14.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:14.429 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:14.429 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:14.429 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:14.429 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:14.458 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:47:14.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:14.476 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:47:14.476 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:47:14.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:14.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:14.925 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:47:15.391 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:47:15.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:15.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:15.417 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:15.417 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:15.417 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:47:15.429 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:15.429 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:15.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:15.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:15.432 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:15.432 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:15.432 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:15.432 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:15.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:15.493 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:47:15.493 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:47:15.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:15.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:15.859 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:47:16.325 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:47:16.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:16.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:16.482 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:16.482 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:16.482 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:47:16.495 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:16.495 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:16.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:16.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:16.497 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:16.497 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:16.497 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:16.497 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:16.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:16.545 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:47:16.546 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:47:16.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:16.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:16.789 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:47:17.255 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:47:17.720 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:47:17.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:17.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:17.893 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:17.893 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:17.893 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:47:17.910 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:17.910 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:17.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:17.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:17.912 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:17.912 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:17.912 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:17.912 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:17.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:17.963 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:47:17.963 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:47:17.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:17.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:18.185 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:47:18.653 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:47:19.121 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:47:19.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:19.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:19.317 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:19.317 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:19.317 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:47:19.335 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:19.335 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:19.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:19.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:19.338 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:19.338 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:19.338 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:19.338 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:19.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:19.381 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:47:19.381 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:47:19.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:19.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:19.586 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:47:20.057 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:47:20.526 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:47:20.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:20.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:20.737 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:20.737 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:20.737 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:47:20.756 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:20.757 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:20.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:20.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:20.759 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:20.759 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:20.759 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:20.759 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:20.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:20.810 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:47:20.810 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:47:20.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:20.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:20.990 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:47:21.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:21.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:21.386 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:21.386 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:21.386 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:47:21.402 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:21.402 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:21.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:21.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:21.404 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:21.404 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:21.404 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:21.404 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:21.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:21.456 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:47:21.458 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:47:21.458 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:47:21.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:21.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:21.923 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 02:47:22.391 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 02:47:22.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:22.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:22.800 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:22.800 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:22.800 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:47:22.820 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:22.820 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:22.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:22.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:22.824 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:22.825 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:22.825 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:22.825 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:22.856 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 02:47:22.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:22.869 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:47:22.869 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:47:22.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:22.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:23.321 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 02:47:23.787 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 02:47:24.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:24.211 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:24.211 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:24.211 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:24.211 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:47:24.217 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:24.217 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:24.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:24.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:24.219 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:24.219 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:24.219 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:24.219 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:24.252 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 02:47:24.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:24.279 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:47:24.279 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:47:24.279 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:24.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:24.722 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 02:47:25.189 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 02:47:25.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:25.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:25.635 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:25.635 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:25.635 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:47:25.648 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:47:25.648 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:47:25.648 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:47:25.648 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:47:25.649 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:47:25.649 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:47:25.649 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:47:25.649 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:47:25.649 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:47:25.649 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:47:25.649 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:47:30.659 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:47:30.659 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:47:30.659 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:47:30.659 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:47:30.659 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:47:30.659 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:47:30.667 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:47:30.668 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:47:30.668 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:47:30.669 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:47:30.669 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:47:30.672 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:47:30.672 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:47:30.673 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:47:30.673 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:47:30.673 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:47:30.673 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:47:30.673 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:47:30.673 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:47:30.673 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:47:30.678 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:47:30.678 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:47:30.678 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:47:30.678 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:47:30.678 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:47:30.679 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:47:30.679 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:47:30.679 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:47:30.679 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:47:30.683 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:47:30.683 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:47:30.683 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:47:30.683 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:47:30.683 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:47:30.684 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:47:30.684 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:47:30.684 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:47:30.684 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:47:30.687 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:47:30.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:47:30.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:47:30.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:47:30.687 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:47:30.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:47:30.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:47:30.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:47:30.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:47:30.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:47:30.687 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:47:30.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:47:30.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:47:30.687 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:47:30.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:47:30.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:47:30.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:47:30.687 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:47:30.687 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:47:30.688 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:47:30.688 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:47:30.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:47:30.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:47:30.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:47:30.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:47:30.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:47:30.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:47:30.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:47:30.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:47:30.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:47:30.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:47:30.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:47:30.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:47:30.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:47:30.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:47:30.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:47:30.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:47:30.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:47:30.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:47:30.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:47:30.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:47:30.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:47:30.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:47:30.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:47:30.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:47:30.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:47:30.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:47:30.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:47:30.692 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:47:31.161 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:47:31.210 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:47:31.211 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:47:31.213 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:47:31.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:31.237 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:31.237 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:31.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:31.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:31.245 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:31.246 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:31.246 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:31.246 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:31.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:47:31.261 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:31.261 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:31.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:31.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:31.626 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:47:31.690 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:47:31.691 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:47:31.691 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:47:31.691 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:47:32.091 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:47:32.559 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:47:32.692 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:47:32.692 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:47:32.692 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:47:32.692 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:47:33.027 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:47:33.497 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:47:33.692 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:47:33.693 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:47:33.693 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:47:33.693 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:47:33.964 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:47:34.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:34.431 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:47:34.694 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:47:34.694 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:47:34.694 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:47:34.694 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:47:34.896 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:47:34.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:34.971 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:34.971 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:34.971 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:34.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:34.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:34.973 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:34.973 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:34.974 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:34.974 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:34.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:47:34.987 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:34.987 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:34.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:34.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:35.362 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:47:35.694 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:47:35.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:47:35.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:47:35.695 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:47:35.829 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:47:36.296 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:47:36.762 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:47:37.229 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:47:37.696 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:47:37.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:38.161 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:47:38.627 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:47:38.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:38.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:38.769 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:38.769 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:38.775 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:38.775 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:38.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:38.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:38.776 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:38.776 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:38.776 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:38.776 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:38.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:47:38.825 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:47:38.825 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:47:38.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:38.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:39.091 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:47:39.555 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:47:40.020 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:47:40.485 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:47:40.951 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:47:41.416 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:47:41.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:41.882 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:47:42.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:42.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:42.327 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:42.327 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:42.327 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:47:42.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:42.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:42.328 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:42.328 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:42.328 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:42.328 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:42.346 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:47:42.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:47:42.348 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:47:42.348 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:47:42.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:42.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:42.812 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:47:43.277 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:47:43.741 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:47:44.204 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:47:44.669 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:47:45.133 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:47:45.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:45.599 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:47:46.064 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:47:46.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:46.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:46.117 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:46.117 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:46.117 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:47:46.129 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:46.129 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:46.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:46.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:46.131 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:46.131 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:46.131 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:46.131 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:46.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:47:46.177 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:46.177 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:46.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:46.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:46.528 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:47:46.991 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:47:47.458 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:47:47.924 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:47:48.393 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:47:48.857 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:47:49.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:49.323 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:47:49.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:49.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:49.765 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:49.765 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:49.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:49.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:49.767 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:49.767 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:49.767 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:49.767 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:49.789 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:47:49.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:47:49.793 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:49.793 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:49.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:49.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:50.255 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:47:50.722 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:47:51.185 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 02:47:51.651 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 02:47:52.116 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 02:47:52.583 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 02:47:52.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:53.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:53.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:53.017 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:53.017 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:53.028 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:53.028 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:53.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:53.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:53.031 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:53.031 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:53.031 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:53.031 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:53.048 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 02:47:53.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:47:53.073 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:47:53.073 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:47:53.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:53.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:53.513 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 02:47:53.983 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 02:47:54.447 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 02:47:54.912 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 02:47:55.379 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 02:47:55.844 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 02:47:56.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:56.308 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 02:47:56.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:47:56.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:56.700 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:47:56.701 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:47:56.701 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:47:56.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:47:56.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:56.701 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:47:56.701 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:47:56.702 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:47:56.702 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:47:56.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:47:56.729 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:47:56.729 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:47:56.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:56.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:47:56.773 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 02:47:57.237 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 02:47:57.704 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 02:47:58.169 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 02:47:58.637 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 02:47:59.103 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 02:47:59.571 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 02:47:59.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:00.036 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 02:48:00.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:00.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:00.424 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:48:00.424 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:48:00.424 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:48:00.427 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:48:00.427 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:48:00.427 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:48:00.427 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:48:00.428 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:48:00.428 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:48:00.428 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:48:00.428 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:48:00.428 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:48:00.428 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:48:00.428 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:48:00.428 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6513 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:48:00.428 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6513 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:48:00.428 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6513 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:48:00.428 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6513 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:48:00.428 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6513 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:48:00.428 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6513 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:48:05.433 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:48:05.433 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:48:05.433 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:48:05.433 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:48:05.433 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:48:05.433 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:48:05.437 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:48:05.437 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:48:05.437 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:48:05.437 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:48:05.437 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:48:05.438 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:48:05.438 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:48:05.438 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:48:05.438 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:48:05.438 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:48:05.438 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:48:05.438 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:48:05.438 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:48:05.438 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:48:05.439 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:48:05.439 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:48:05.440 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:48:05.440 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:48:05.440 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:48:05.440 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:48:05.440 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:48:05.440 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:48:05.440 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:48:05.441 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:48:05.441 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:48:05.441 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:48:05.441 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:48:05.441 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:48:05.441 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:48:05.441 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:48:05.441 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:48:05.441 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:48:05.443 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:48:05.443 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:48:05.443 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:48:05.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:48:05.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:48:05.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:48:05.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:48:05.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:48:05.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:48:05.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:48:05.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:48:05.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:48:05.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:48:05.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:48:05.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:48:05.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:48:05.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:48:05.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:48:05.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:48:05.448 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:48:05.911 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:48:05.954 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:48:05.955 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:48:05.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:05.956 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:48:05.961 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:48:05.962 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:48:05.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:48:05.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:05.964 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:48:05.964 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:48:05.964 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:48:05.964 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:48:06.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:48:06.093 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:48:06.093 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:48:06.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:06.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:06.378 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:48:06.445 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:48:06.445 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:48:06.445 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:48:06.445 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:48:06.845 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:48:07.312 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:48:07.446 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:48:07.446 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:48:07.446 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:48:07.446 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:48:07.778 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:48:08.242 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:48:08.447 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:48:08.447 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:48:08.447 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:48:08.447 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:48:08.708 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:48:09.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:09.176 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:48:09.448 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:48:09.448 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:48:09.448 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:48:09.448 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:48:09.645 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:48:09.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:09.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:09.711 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:48:09.711 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:48:09.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:48:09.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:09.711 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:48:09.711 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:48:09.711 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:48:09.711 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:48:09.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:48:09.730 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:48:09.730 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:48:09.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:09.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:10.112 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:48:10.448 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:48:10.449 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:48:10.449 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:48:10.449 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:48:10.576 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:48:11.044 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:48:11.510 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:48:11.974 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:48:12.442 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:48:12.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:12.908 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:48:13.372 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:48:13.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:13.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:13.537 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:48:13.537 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:48:13.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:48:13.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:13.538 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:48:13.538 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:48:13.538 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:48:13.538 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:48:13.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:48:13.556 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:48:13.556 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:48:13.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:13.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:13.840 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:48:14.309 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:48:14.779 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:48:15.244 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:48:15.711 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:48:16.180 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:48:16.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:16.645 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:48:17.112 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:48:17.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:17.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:17.326 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:48:17.326 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:48:17.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:48:17.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:17.326 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:48:17.326 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:48:17.326 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:48:17.326 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:48:17.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:48:17.341 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:48:17.341 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:48:17.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:17.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:17.577 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:48:17.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:18.043 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:48:18.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:18.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:18.394 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:48:18.394 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:48:18.401 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:48:18.401 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:48:18.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:48:18.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:18.403 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:48:18.403 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:48:18.403 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:48:18.403 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:48:18.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:48:18.449 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:48:18.449 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:48:18.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:18.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:18.507 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:48:18.970 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:48:19.434 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:48:19.898 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:48:20.363 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:48:20.833 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:48:21.300 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:48:21.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:21.764 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:48:21.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:21.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:21.833 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:48:21.834 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:48:21.834 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:48:21.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:48:21.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:21.834 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:48:21.834 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:48:21.834 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:48:21.834 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:48:21.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:48:21.854 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:48:21.855 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:48:21.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:21.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:22.230 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:48:22.698 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:48:23.162 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:48:23.625 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:48:24.088 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:48:24.554 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:48:24.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:25.017 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:48:25.482 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:48:25.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:25.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:25.625 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:48:25.625 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:48:25.625 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:48:25.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:48:25.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:25.626 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:48:25.626 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:48:25.626 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:48:25.626 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:48:25.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:48:25.663 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:48:25.663 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:48:25.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:25.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:25.946 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 02:48:26.410 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 02:48:26.872 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 02:48:27.337 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 02:48:27.800 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 02:48:28.264 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 02:48:28.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:28.727 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 02:48:29.190 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 02:48:29.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:29.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:29.406 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:48:29.406 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:48:29.406 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:48:29.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:48:29.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:29.406 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:48:29.406 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:48:29.406 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:48:29.406 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:48:29.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:48:29.420 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:48:29.420 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:48:29.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:29.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:29.653 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 02:48:29.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:30.116 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 02:48:30.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:30.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:30.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:48:30.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:48:30.352 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:48:30.358 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:48:30.358 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:48:30.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:48:30.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:30.360 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:48:30.360 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:48:30.360 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:48:30.361 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:48:30.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:48:30.405 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:48:30.405 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:48:30.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:30.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:30.579 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 02:48:31.041 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 02:48:31.504 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 02:48:31.967 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 02:48:32.431 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 02:48:32.893 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 02:48:33.356 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 02:48:33.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:33.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:33.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:33.790 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:48:33.790 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:48:33.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:48:33.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:33.790 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:48:33.790 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:48:33.791 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:48:33.791 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:48:33.819 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 02:48:33.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:48:33.821 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:48:33.821 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:48:33.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:33.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:34.283 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 02:48:34.746 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 02:48:35.209 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 02:48:35.672 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 02:48:36.135 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 02:48:36.598 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 02:48:37.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:37.061 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 02:48:37.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:37.496 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:37.496 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:48:37.496 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:48:37.496 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:48:37.496 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:37.496 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:48:37.496 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:48:37.496 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:48:37.496 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:48:37.524 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 02:48:37.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:48:37.526 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:48:37.526 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:48:37.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:37.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:37.987 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 02:48:38.450 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 02:48:38.912 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 02:48:39.376 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 02:48:39.838 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-06 02:48:40.303 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-06 02:48:40.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:40.767 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-06 02:48:41.231 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-06 02:48:41.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:41.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:41.295 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:48:41.295 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:48:41.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:48:41.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:41.295 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:48:41.295 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:48:41.295 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:48:41.295 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:48:41.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:48:41.318 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:48:41.318 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:48:41.318 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:41.318 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:41.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:41.696 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-06 02:48:42.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:42.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:42.136 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:48:42.136 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:48:42.146 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:48:42.146 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:48:42.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:48:42.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:42.148 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:48:42.148 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:48:42.148 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:48:42.148 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:48:42.163 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-06 02:48:42.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:48:42.201 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:48:42.201 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:48:42.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:42.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:42.632 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-06 02:48:43.101 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-06 02:48:43.570 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-06 02:48:44.120 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-06 02:48:44.582 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-06 02:48:45.045 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-06 02:48:45.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:45.509 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-06 02:48:45.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:45.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:45.899 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:48:45.899 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:48:45.899 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:48:45.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:48:45.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:45.899 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:48:45.899 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:48:45.900 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:48:45.900 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:48:45.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:48:45.927 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:48:45.927 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:48:45.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:45.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:45.973 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-06 02:48:46.438 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-06 02:48:46.903 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-06 02:48:47.368 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-06 02:48:47.831 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-06 02:48:48.294 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-06 02:48:48.758 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-06 02:48:49.221 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-06 02:48:49.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:49.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:49.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:49.613 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:48:49.613 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:48:49.613 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:48:49.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:48:49.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:49.614 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:48:49.614 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:48:49.614 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:48:49.614 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:48:49.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:48:49.643 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:48:49.643 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:48:49.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:49.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:49.686 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-06 02:48:50.151 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-06 02:48:50.614 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-06 02:48:51.077 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-06 02:48:51.543 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-06 02:48:52.007 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-06 02:48:52.472 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-06 02:48:52.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:52.935 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-06 02:48:53.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:53.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:53.325 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:48:53.325 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:48:53.325 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:48:53.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:48:53.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:53.326 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:48:53.326 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:48:53.326 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:48:53.326 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:48:53.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:48:53.353 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:48:53.353 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:48:53.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:53.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:53.400 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-06 02:48:53.866 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-06 02:48:54.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:54.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:48:54.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:48:54.254 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:48:54.254 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:48:54.254 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:48:54.259 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:48:54.259 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:48:54.259 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:48:54.259 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:48:54.260 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:48:54.260 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:48:54.261 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:48:54.261 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:48:54.261 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:48:54.261 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:48:54.261 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:48:54.261 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=10696 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:48:54.261 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=10696 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:48:54.261 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=10696 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:48:54.261 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=10696 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:48:54.261 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=10696 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:48:54.261 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=10696 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:48:59.263 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:48:59.263 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:48:59.263 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:48:59.263 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:48:59.263 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:48:59.264 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:48:59.273 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:48:59.273 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:48:59.273 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:48:59.273 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:48:59.273 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:48:59.276 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:48:59.276 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:48:59.276 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:48:59.276 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:48:59.276 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:48:59.276 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:48:59.276 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:48:59.276 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:48:59.276 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:48:59.279 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:48:59.279 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:48:59.279 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:48:59.279 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:48:59.280 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:48:59.280 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:48:59.280 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:48:59.280 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:48:59.280 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:48:59.281 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:48:59.281 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:48:59.282 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:48:59.282 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:48:59.282 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:48:59.282 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:48:59.282 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:48:59.282 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:48:59.282 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:48:59.285 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:48:59.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:48:59.285 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:48:59.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:48:59.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:48:59.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:48:59.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:48:59.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:48:59.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:48:59.286 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:48:59.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:48:59.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:48:59.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:48:59.286 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:48:59.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:48:59.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:48:59.286 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:48:59.286 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:48:59.286 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:48:59.286 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:48:59.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:48:59.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:48:59.288 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:48:59.288 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:48:59.288 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:48:59.288 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:48:59.288 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:48:59.288 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:48:59.288 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:48:59.288 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:48:59.288 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:48:59.288 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:04.291 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:49:04.291 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:49:04.291 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:49:04.291 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:49:04.291 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:49:04.291 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:49:04.300 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:49:04.300 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:49:04.300 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:49:04.300 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:49:04.300 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:49:04.302 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:49:04.302 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:49:04.303 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:49:04.303 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:49:04.303 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:49:04.303 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:49:04.303 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:49:04.303 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:49:04.303 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:04.305 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:49:04.305 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:49:04.306 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:49:04.306 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:49:04.306 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:49:04.306 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:49:04.306 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:49:04.306 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:49:04.306 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:04.308 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:49:04.308 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:49:04.309 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:49:04.309 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:49:04.309 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:49:04.309 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:49:04.309 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:49:04.309 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:49:04.309 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:04.313 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:49:04.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:49:04.313 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:49:04.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:49:04.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:49:04.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:49:04.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:49:04.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:49:04.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:04.313 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:49:04.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:04.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:49:04.313 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:04.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:04.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:04.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:04.313 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:49:04.313 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:49:04.313 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:49:04.313 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:49:04.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:04.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:04.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:04.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:49:04.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:04.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:04.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:04.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:04.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:04.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:04.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:04.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:04.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:04.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:04.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:04.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:04.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:04.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:04.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:04.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:04.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:04.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:04.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:04.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:04.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:04.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:04.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:04.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:04.318 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:49:04.783 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:49:05.248 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:49:05.316 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:05.317 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:05.322 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:05.323 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:05.713 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:49:05.802 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:49:05.803 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:49:05.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:49:05.804 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:49:05.807 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:49:05.807 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:49:05.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:49:05.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:49:05.808 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:49:05.808 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:49:05.808 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:49:05.808 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:49:06.233 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:49:06.316 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:06.318 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:06.322 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:06.324 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:06.697 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:49:07.162 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:49:07.317 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:07.318 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:07.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:07.324 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:07.628 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:49:08.093 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:49:08.317 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:08.318 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:08.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:08.324 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:08.559 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:49:09.025 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:49:09.318 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:09.319 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:09.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:09.325 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:09.490 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:49:09.956 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:49:10.421 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:49:10.885 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:49:11.351 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:49:11.816 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:49:12.281 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:49:12.747 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:49:13.212 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:49:13.677 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:49:14.142 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:49:14.606 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:49:14.917 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:49:14.917 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:49:14.919 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:14.919 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:14.919 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:14.919 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:14.920 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:49:14.920 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:49:14.920 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:49:14.920 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:49:14.920 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:49:14.920 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:49:14.920 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:49:14.920 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2314 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:49:14.920 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2314 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:49:14.920 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2314 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:49:14.920 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2314 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:49:14.920 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2314 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:49:14.920 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2314 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:49:19.922 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:49:19.922 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:49:19.922 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:49:19.922 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:49:19.922 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:49:19.922 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:49:19.931 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:49:19.931 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:49:19.931 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:49:19.931 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:49:19.931 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:49:19.933 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:49:19.933 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:49:19.933 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:49:19.934 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:49:19.934 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:49:19.934 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:49:19.934 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:49:19.934 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:49:19.934 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:19.936 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:49:19.936 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:49:19.936 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:49:19.936 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:49:19.936 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:49:19.936 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:49:19.936 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:49:19.936 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:49:19.936 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:19.938 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:49:19.938 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:49:19.938 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:49:19.938 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:49:19.938 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:49:19.938 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:49:19.938 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:49:19.938 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:49:19.938 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:19.942 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:49:19.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:49:19.943 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:49:19.943 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:49:19.943 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:49:19.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:49:19.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:49:19.943 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:49:19.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:19.943 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:49:19.943 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:19.943 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:49:19.943 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:19.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:19.943 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:19.943 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:19.943 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:49:19.943 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:49:19.943 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:49:19.943 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:49:19.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:19.943 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:19.943 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:19.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:49:19.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:19.944 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:19.944 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:19.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:19.944 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:19.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:19.944 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:19.944 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:19.944 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:19.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:19.944 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:19.944 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:19.944 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:19.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:19.944 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:19.944 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:19.944 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:19.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:19.944 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:19.944 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:19.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:19.944 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:19.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:19.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:19.948 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:49:20.413 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:49:20.468 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:49:20.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:49:20.610 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:49:20.611 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:49:20.613 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:49:20.613 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:49:20.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:49:20.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:49:20.613 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:49:20.613 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:49:20.614 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:49:20.614 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:49:20.878 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:49:20.946 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:20.948 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:20.949 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:20.953 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:21.343 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:49:21.808 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:49:21.947 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:21.948 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:21.949 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:21.954 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:22.274 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:49:22.837 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:49:22.948 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:22.949 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:22.950 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:22.955 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:23.301 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:49:23.766 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:49:23.948 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:23.950 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:23.950 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:23.955 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:24.231 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:49:24.696 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:49:24.949 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:24.950 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:24.950 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:24.956 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:25.162 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:49:25.627 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:49:26.092 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:49:26.557 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:49:27.023 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:49:27.489 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:49:27.955 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:49:28.420 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:49:28.884 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:49:29.349 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:49:29.891 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:49:30.286 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:49:30.286 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:49:30.287 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:30.287 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:30.287 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:30.287 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:30.288 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:49:30.288 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:49:30.289 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:49:30.289 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:49:30.289 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:49:30.289 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:49:30.289 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:49:30.289 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2230 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:49:30.289 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2230 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:49:30.289 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2230 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:49:30.289 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2230 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:49:30.289 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2230 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:49:30.289 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2230 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:49:35.291 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:49:35.291 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:49:35.291 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:49:35.292 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:49:35.292 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:49:35.292 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:49:35.299 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:49:35.299 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:49:35.300 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:49:35.300 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:49:35.300 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:49:35.302 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:49:35.302 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:49:35.302 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:49:35.302 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:49:35.302 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:49:35.302 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:49:35.302 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:49:35.302 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:49:35.302 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:35.304 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:49:35.304 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:49:35.304 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:49:35.304 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:49:35.304 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:49:35.304 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:49:35.304 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:49:35.304 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:49:35.304 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:35.305 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:49:35.305 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:49:35.305 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:49:35.305 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:49:35.305 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:49:35.305 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:49:35.305 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:49:35.305 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:49:35.306 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:35.308 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:49:35.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:49:35.308 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:49:35.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:49:35.309 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:49:35.309 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:49:35.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:49:35.309 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:49:35.309 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:35.309 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:49:35.309 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:49:35.309 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:35.309 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:35.309 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:35.309 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:35.309 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:35.309 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:35.309 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:49:35.309 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:49:35.309 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:49:35.309 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:49:35.309 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:35.309 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:35.309 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:35.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:49:35.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:35.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:35.310 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:35.310 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:35.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:35.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:35.310 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:35.310 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:35.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:35.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:35.310 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:35.310 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:35.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:35.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:35.310 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:35.310 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:35.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:35.310 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:35.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:35.310 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:35.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:35.310 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:35.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:35.314 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:49:35.779 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:49:35.829 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:49:35.830 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:49:35.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:49:35.831 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:49:35.833 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:49:35.833 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:49:35.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:49:36.243 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:49:36.313 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:36.313 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:36.314 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:36.318 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:36.708 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:49:36.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:49:36.833 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:49:36.833 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:49:36.834 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:49:36.834 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:49:37.172 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:49:37.313 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:37.314 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:37.315 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:37.319 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:37.636 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:49:38.100 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:49:38.314 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:38.314 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:38.315 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:38.319 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:38.565 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:49:39.029 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:49:39.314 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:39.314 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:39.316 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:39.320 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:39.493 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:49:39.957 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:49:40.315 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:40.315 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:40.316 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:40.320 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:40.420 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:49:40.884 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:49:41.347 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:49:41.811 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:49:42.273 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:49:42.736 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:49:43.199 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:49:43.663 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:49:44.128 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:49:44.592 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:49:45.056 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:49:45.520 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:49:45.985 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:49:46.449 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:49:46.914 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:49:47.379 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:49:47.844 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:49:48.308 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:49:48.773 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:49:48.938 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:49:48.938 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:49:48.940 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:48.940 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:48.940 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:48.940 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:48.941 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:49:48.941 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:49:48.941 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:49:48.941 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:49:48.941 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:49:48.941 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:49:48.941 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:49:53.943 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:49:53.943 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:49:53.943 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:49:53.943 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:49:53.943 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:49:53.943 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:49:53.951 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:49:53.952 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:49:53.952 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:49:53.952 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:49:53.952 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:49:53.954 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:49:53.954 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:49:53.954 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:49:53.954 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:49:53.954 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:49:53.955 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:49:53.955 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:49:53.955 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:49:53.955 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:53.958 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:49:53.958 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:49:53.958 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:49:53.958 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:49:53.958 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:49:53.958 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:49:53.958 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:49:53.958 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:49:53.958 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:53.960 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:49:53.961 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:49:53.961 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:49:53.961 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:49:53.961 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:49:53.961 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:49:53.961 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:49:53.961 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:49:53.961 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:53.965 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:49:53.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:49:53.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:49:53.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:49:53.965 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:49:53.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:49:53.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:49:53.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:53.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:49:53.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:49:53.965 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:49:53.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:53.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:53.966 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:53.966 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:53.966 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:53.966 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:53.966 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:49:53.966 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:49:53.966 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:49:53.966 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:49:53.966 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:53.966 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:53.966 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:53.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:49:53.966 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:53.966 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:53.966 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:53.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:53.966 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:53.966 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:53.966 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:53.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:53.966 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:53.966 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:53.966 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:53.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:53.967 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:49:53.967 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:53.967 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:53.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:53.967 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:53.967 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:49:53.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:53.967 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:49:53.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:53.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:53.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:49:53.970 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:49:54.435 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:49:54.490 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:49:54.491 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:49:54.492 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:49:54.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:49:54.494 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:49:54.494 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:49:54.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:49:54.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:49:54.494 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:49:54.494 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:49:54.494 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:49:54.494 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:49:54.900 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:49:54.969 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:54.969 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:54.971 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:54.975 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:55.365 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:49:55.524 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:49:55.829 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:49:55.970 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:55.970 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:55.971 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:55.975 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:56.030 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:49:56.295 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:49:56.537 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:49:56.759 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:49:56.970 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:56.970 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:56.972 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:56.976 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:57.223 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:49:57.688 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:49:57.971 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:57.971 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:57.972 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:57.977 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:58.153 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:49:58.548 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:49:58.618 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:49:58.971 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:49:58.971 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:49:58.972 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:49:58.977 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:49:59.054 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:49:59.250 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:49:59.561 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:49:59.715 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:50:00.069 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:50:00.180 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:50:00.644 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:50:01.109 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:50:01.574 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:50:02.039 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:50:02.113 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:50:02.505 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:50:02.970 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:50:03.435 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:50:03.899 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:50:04.119 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:04.119 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:04.121 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:04.121 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:04.121 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:04.121 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:04.122 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:50:04.122 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:50:04.122 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:50:04.122 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:50:04.122 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:50:04.122 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:50:04.122 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:50:09.124 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:50:09.125 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:50:09.125 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:50:09.125 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:50:09.125 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:50:09.125 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:50:09.132 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:50:09.132 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:50:09.132 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:09.132 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:50:09.132 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:50:09.134 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:50:09.135 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:50:09.135 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:50:09.135 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:09.135 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:50:09.135 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:50:09.135 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:50:09.135 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:50:09.135 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:09.138 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:50:09.138 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:50:09.138 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:50:09.138 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:09.138 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:50:09.138 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:50:09.138 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:50:09.138 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:50:09.138 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:09.141 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:50:09.141 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:50:09.141 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:50:09.141 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:09.141 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:50:09.141 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:50:09.141 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:50:09.141 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:50:09.142 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:09.145 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:50:09.146 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:50:09.146 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:50:09.146 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:50:09.146 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:50:09.146 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:50:09.146 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:50:09.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:50:09.146 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:09.146 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:50:09.146 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:50:09.146 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:09.146 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:09.146 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:09.146 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:09.146 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:09.146 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:09.146 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:09.146 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:50:09.146 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:50:09.146 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:50:09.146 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:50:09.146 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:09.146 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:09.146 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:09.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:50:09.147 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:09.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:09.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:09.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:09.147 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:09.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:09.147 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:09.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:09.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:09.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:09.147 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:09.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:09.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:09.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:09.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:09.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:09.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:09.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:09.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:09.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:09.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:09.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:09.151 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:50:09.616 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:50:09.673 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:50:09.674 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:50:09.675 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:50:09.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:09.688 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:09.688 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:09.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:50:09.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:09.691 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:09.691 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:09.691 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:50:09.691 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:50:09.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:50:09.712 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:09.712 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:09.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:09.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:09.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:09.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:09.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:09.782 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:09.782 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:09.795 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:09.795 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:09.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:50:09.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:09.798 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:09.798 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:09.798 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:50:09.798 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:50:09.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:50:09.853 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:09.853 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:09.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:09.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:10.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:10.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.036 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:10.036 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:10.048 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:10.048 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:10.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:50:10.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.051 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:10.051 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:10.051 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:50:10.052 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:50:10.081 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:50:10.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:50:10.088 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:10.088 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:10.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.150 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:10.150 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:10.152 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:10.156 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:10.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:10.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:10.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.290 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:10.290 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:10.303 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:10.303 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:10.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:50:10.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.306 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:10.306 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:10.306 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:50:10.306 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:50:10.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:50:10.315 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:10.316 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:10.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:10.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:10.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.322 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:10.322 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:10.335 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:10.335 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:10.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:50:10.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.339 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:10.339 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:10.339 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:50:10.339 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:50:10.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:50:10.360 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:10.361 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:10.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:10.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:10.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.368 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:10.368 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:10.382 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:10.382 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:10.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:50:10.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.385 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:10.385 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:10.385 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:50:10.385 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:50:10.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:50:10.407 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:50:10.407 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-06 02:50:10.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:10.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:10.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.414 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:10.414 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:10.414 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:50:10.426 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:10.426 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:10.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:50:10.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.429 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:10.429 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:10.429 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:50:10.429 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:50:10.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:50:10.453 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:50:10.453 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-06 02:50:10.454 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.454 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:10.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:10.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.470 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:10.470 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:10.470 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:50:10.483 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:10.483 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:10.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:50:10.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.485 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:10.486 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:10.486 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:50:10.486 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:50:10.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:10.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:50:10.500 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:10.500 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:10.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:10.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:10.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.511 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:10.511 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:10.523 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:10.523 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:10.523 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:50:10.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.526 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:10.526 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:10.526 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:50:10.526 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:50:10.545 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:50:10.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:50:10.551 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:10.551 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:10.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:10.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:10.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.558 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:10.558 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:10.570 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:10.571 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:10.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:50:10.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.573 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:10.573 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:10.573 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:50:10.573 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:50:10.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:10.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:50:10.593 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:10.593 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:10.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:10.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:10.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.599 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:10.599 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:10.612 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:10.612 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:10.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:50:10.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.615 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:10.615 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:10.615 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:50:10.615 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:50:10.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:50:10.639 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:50:10.639 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:50:10.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:10.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:10.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.645 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:10.645 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:10.645 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:50:10.658 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:10.658 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:10.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:50:10.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.662 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:10.662 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:10.662 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:50:10.662 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:50:10.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:50:10.684 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:50:10.684 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:50:10.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:10.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:10.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.691 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:10.691 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:10.691 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:50:10.701 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:10.701 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:10.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:50:10.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.703 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:10.703 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:10.703 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:50:10.703 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:50:10.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:50:10.731 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:50:10.731 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:50:10.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:10.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:10.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.849 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:10.849 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:10.849 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:50:10.861 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:10.861 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:10.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:50:10.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.864 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:10.864 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:10.864 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:50:10.864 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:50:10.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:50:10.874 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:50:10.874 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:50:10.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:10.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:11.010 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:50:11.151 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:11.151 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:11.152 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:11.157 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:11.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:11.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:11.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:11.324 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:11.324 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:11.324 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:50:11.336 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:11.336 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:11.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:50:11.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:11.339 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:11.339 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:11.339 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:50:11.339 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:50:11.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:50:11.382 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:50:11.382 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:50:11.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:11.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:11.474 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:50:11.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:11.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:11.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:11.581 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:11.581 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:11.581 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:50:11.593 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:11.594 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:11.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:50:11.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:11.596 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:11.596 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:11.597 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:50:11.597 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:50:11.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:50:11.612 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:50:11.612 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:50:11.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:11.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:11.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:11.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:11.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:11.827 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:11.827 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:11.827 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:50:11.839 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:11.839 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:11.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:50:11.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:11.842 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:11.842 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:11.842 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:50:11.842 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:50:11.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:50:11.894 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:50:11.894 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:50:11.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:11.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:11.939 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:50:12.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:12.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:12.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:12.076 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:12.076 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:12.076 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:50:12.089 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:12.089 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:12.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:50:12.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:12.092 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:12.092 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:12.092 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:50:12.092 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:50:12.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:50:12.125 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:50:12.125 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:50:12.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:12.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:12.151 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:12.151 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:12.152 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:12.158 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:12.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:12.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:12.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:12.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:12.330 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:12.330 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:50:12.343 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:12.343 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:12.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:50:12.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:12.346 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:12.346 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:12.346 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:50:12.346 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:50:12.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:50:12.361 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:50:12.361 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:50:12.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:12.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:12.403 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:50:12.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:12.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:12.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:12.583 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:12.583 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:12.583 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:50:12.596 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:12.596 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:12.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:50:12.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:12.599 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:12.599 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:12.599 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:50:12.599 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:50:12.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:50:12.636 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:50:12.636 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:50:12.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:12.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:12.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:12.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:12.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:12.828 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:12.828 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:12.828 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:50:12.833 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:12.833 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:12.833 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:12.833 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:12.834 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:50:12.834 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:50:12.834 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:50:12.834 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:50:12.834 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:50:12.834 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:50:12.834 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:50:12.834 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=810 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:50:12.834 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=810 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:50:12.834 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=810 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:50:12.834 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=810 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:50:12.834 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=810 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:50:12.834 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=810 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:50:17.836 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:50:17.836 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:50:17.836 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:50:17.836 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:50:17.836 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:50:17.836 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:50:17.845 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:50:17.845 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:50:17.845 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:17.845 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:50:17.845 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:50:17.848 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:50:17.848 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:50:17.848 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:50:17.848 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:17.848 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:50:17.848 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:50:17.848 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:50:17.848 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:50:17.848 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:17.851 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:50:17.851 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:50:17.851 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:50:17.851 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:17.851 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:50:17.851 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:50:17.851 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:50:17.851 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:50:17.852 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:17.855 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:50:17.855 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:50:17.855 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:50:17.855 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:17.855 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:50:17.855 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:50:17.855 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:50:17.855 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:50:17.855 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:17.859 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:50:17.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:50:17.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:50:17.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:50:17.859 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:50:17.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:50:17.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:50:17.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:50:17.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:50:17.860 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:50:17.860 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:50:17.860 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:17.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:17.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:17.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:17.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:17.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:17.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:17.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:17.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:17.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:17.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:17.865 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:50:18.329 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:50:18.380 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:50:18.381 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:50:18.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:18.382 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:50:18.395 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:18.395 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:18.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:50:18.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:18.398 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:18.398 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:18.398 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:50:18.398 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:50:18.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 02:50:18.425 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:18.425 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:18.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:18.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:18.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:18.793 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:50:18.863 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:18.863 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:18.863 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:18.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:19.258 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:50:19.722 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:50:19.864 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:19.864 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:19.864 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:19.865 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:20.187 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:50:20.470 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:20.470 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:20.471 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:20.471 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:20.471 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:20.471 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:20.473 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:50:20.473 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:50:20.473 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:50:20.473 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:50:20.473 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:50:20.473 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:50:20.473 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:50:20.473 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=574 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:50:20.473 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=574 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:50:20.473 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=574 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:50:20.473 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=574 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:50:20.473 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=574 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:50:25.474 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:50:25.474 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:50:25.474 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:50:25.474 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:50:25.474 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:50:25.474 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:50:25.483 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:50:25.483 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:50:25.483 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:25.483 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:50:25.483 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:50:25.485 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:50:25.485 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:50:25.485 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:50:25.485 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:25.485 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:50:25.486 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:50:25.486 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:50:25.486 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:50:25.486 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:25.488 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:50:25.488 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:50:25.488 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:50:25.488 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:25.489 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:50:25.489 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:50:25.489 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:50:25.489 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:50:25.489 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:25.491 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:50:25.491 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:50:25.491 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:50:25.491 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:25.491 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:50:25.491 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:50:25.491 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:50:25.491 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:50:25.491 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:25.495 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:50:25.495 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:50:25.495 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:50:25.495 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:50:25.495 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:50:25.495 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:50:25.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:50:25.495 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:50:25.495 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:25.496 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:50:25.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:25.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:50:25.496 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:25.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:25.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:25.496 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:50:25.496 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:50:25.496 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:50:25.496 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:50:25.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:25.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:25.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:25.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:50:25.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:25.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:50:25.497 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:50:25.497 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:50:25.497 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:50:25.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:30.500 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:50:30.500 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:50:30.500 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:50:30.500 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:50:30.500 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:50:30.500 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:50:30.508 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:50:30.509 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:50:30.509 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:30.509 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:50:30.509 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:50:30.511 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:50:30.511 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:50:30.511 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:50:30.511 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:30.511 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:50:30.511 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:50:30.511 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:50:30.511 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:50:30.511 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:30.513 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:50:30.513 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:50:30.514 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:50:30.514 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:30.514 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:50:30.514 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:50:30.514 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:50:30.514 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:50:30.514 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:30.516 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:50:30.516 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:50:30.516 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:50:30.516 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:30.516 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:50:30.516 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:50:30.516 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:50:30.516 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:50:30.516 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:30.518 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:50:30.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:50:30.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:50:30.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:50:30.518 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:50:30.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:50:30.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:50:30.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:30.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:50:30.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:50:30.519 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:50:30.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:30.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:30.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:30.519 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:30.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:30.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:30.519 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:50:30.519 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:50:30.519 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:50:30.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:30.519 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:50:30.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:30.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:30.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:50:30.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:30.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:30.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:30.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:30.520 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:30.520 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:30.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:30.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:30.520 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:30.520 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:30.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:30.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:30.520 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:30.520 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:30.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:30.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:30.520 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:30.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:30.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:30.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:30.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:30.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:30.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:30.524 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:50:30.988 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:50:31.043 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:50:31.044 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:50:31.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:31.045 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:50:31.453 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:50:31.523 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:31.523 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:31.524 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:31.529 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:31.917 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:50:32.382 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:50:32.523 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:32.523 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:32.524 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:32.530 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:32.846 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:50:33.310 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:50:33.524 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:33.524 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:33.525 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:33.530 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:33.775 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:50:34.239 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:50:34.524 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:34.524 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:34.525 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:34.531 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:34.703 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:50:35.168 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:50:35.525 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:35.525 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:35.527 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:35.531 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:35.632 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:50:36.097 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:50:36.561 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:50:36.604 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:36.604 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:36.604 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:36.604 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:36.605 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:50:36.605 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:50:36.605 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:50:36.605 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:50:36.605 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:50:36.605 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:50:36.606 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:50:36.606 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1338 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:50:36.606 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1338 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:50:36.606 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1338 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:50:36.606 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1338 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:50:36.606 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1338 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:50:36.606 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1338 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:50:41.608 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:50:41.608 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:50:41.608 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:50:41.608 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:50:41.608 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:50:41.608 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:50:41.617 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:50:41.617 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:50:41.617 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:41.617 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:50:41.617 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:50:41.620 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:50:41.620 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:50:41.620 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:50:41.620 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:41.620 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:50:41.620 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:50:41.620 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:50:41.620 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:50:41.620 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:41.623 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:50:41.623 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:50:41.623 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:50:41.623 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:41.623 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:50:41.623 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:50:41.623 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:50:41.623 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:50:41.623 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:41.626 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:50:41.626 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:50:41.626 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:50:41.626 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:41.626 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:50:41.626 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:50:41.626 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:50:41.626 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:50:41.626 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:41.630 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:50:41.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:50:41.631 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:50:41.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:50:41.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:50:41.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:50:41.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:50:41.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:50:41.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:41.631 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:50:41.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:41.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:50:41.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:41.631 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:41.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:41.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:41.631 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:50:41.631 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:50:41.631 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:50:41.631 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:50:41.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:41.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:41.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:41.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:41.636 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:50:42.101 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:50:42.158 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:50:42.159 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:50:42.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:42.160 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:50:42.565 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:50:42.636 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:42.636 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:42.637 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:42.642 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:43.029 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:50:43.494 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:50:43.636 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:43.637 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:43.638 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:43.643 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:43.959 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:50:44.423 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:50:44.637 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:44.637 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:44.638 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:44.643 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:44.888 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:50:45.352 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:50:45.637 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:45.638 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:45.639 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:45.644 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:45.817 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:50:46.281 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:50:46.638 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:46.638 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:46.639 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:46.645 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:46.745 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:50:47.166 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:47.166 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:47.166 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:47.166 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:47.167 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:50:47.167 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:50:47.167 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:50:47.167 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:50:47.167 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:50:47.167 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:50:47.167 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:50:52.169 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:50:52.169 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:50:52.169 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:50:52.169 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:50:52.169 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:50:52.169 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:50:52.178 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:50:52.178 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:50:52.179 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:52.179 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:50:52.179 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:50:52.181 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:50:52.182 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:50:52.182 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:50:52.182 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:52.182 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:50:52.182 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:50:52.182 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:50:52.182 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:50:52.182 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:52.185 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:50:52.185 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:50:52.185 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:50:52.185 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:52.185 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:50:52.185 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:50:52.185 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:50:52.185 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:50:52.185 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:52.188 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:50:52.188 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:50:52.188 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:50:52.188 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:52.188 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:50:52.188 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:50:52.188 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:50:52.188 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:50:52.189 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:52.193 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:50:52.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:50:52.193 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:50:52.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:50:52.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:50:52.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:50:52.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:50:52.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:50:52.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:52.193 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:50:52.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:52.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:50:52.193 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:52.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:52.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:52.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:52.194 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:50:52.194 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:50:52.194 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:50:52.194 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:50:52.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:52.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:52.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:52.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:50:52.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:52.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:52.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:52.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:50:52.196 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:50:52.196 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:50:52.196 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:50:57.200 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:50:57.200 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:50:57.200 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:50:57.200 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:50:57.200 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:50:57.200 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:50:57.209 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:50:57.210 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:50:57.210 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:57.210 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:50:57.210 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:50:57.213 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:50:57.213 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:50:57.213 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:50:57.213 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:57.213 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:50:57.213 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:50:57.213 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:50:57.213 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:50:57.213 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:57.216 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:50:57.216 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:50:57.216 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:50:57.216 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:57.216 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:50:57.216 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:50:57.217 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:50:57.217 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:50:57.217 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:57.219 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:50:57.219 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:50:57.219 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:50:57.219 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:50:57.219 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:50:57.219 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:50:57.220 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:50:57.220 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:50:57.220 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:57.224 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:50:57.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:50:57.224 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:50:57.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:50:57.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:50:57.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:50:57.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:50:57.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:50:57.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:57.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:50:57.224 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:50:57.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:57.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:57.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:57.224 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:57.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:57.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:57.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:57.224 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:50:57.224 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:50:57.224 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:50:57.224 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:50:57.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:57.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:57.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:57.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:50:57.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:57.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:57.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:57.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:57.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:57.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:57.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:57.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:57.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:57.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:57.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:50:57.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:57.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:57.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:57.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:57.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:57.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:57.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:50:57.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:57.226 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:50:57.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:57.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:50:57.229 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:50:57.694 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:50:57.752 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:50:57.754 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:50:57.755 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:50:57.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:50:57.757 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:50:57.757 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:50:57.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:50:58.159 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:50:58.228 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:58.229 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:58.230 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:58.235 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:58.624 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:50:58.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:50:58.758 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:50:58.758 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:50:58.758 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:50:58.758 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:50:59.089 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:50:59.229 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:50:59.230 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:50:59.231 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:50:59.236 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:50:59.554 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:51:00.019 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:51:00.229 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:00.230 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:00.232 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:00.236 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:00.484 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:51:00.949 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:51:01.230 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:01.231 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:01.232 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:01.237 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:01.414 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:51:01.878 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:51:02.231 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:02.231 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:02.233 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:02.237 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:02.343 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:51:02.808 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:51:03.273 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:51:03.738 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:51:04.203 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:51:04.668 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:51:05.133 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:51:05.599 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:51:06.064 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:51:06.529 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:51:06.994 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:51:07.459 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:51:07.924 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:51:08.390 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:51:08.855 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:51:09.319 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:51:09.784 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:51:10.248 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:51:10.713 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:51:11.177 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:51:11.640 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:51:12.103 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:51:12.567 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:51:13.004 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:51:13.004 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:51:13.007 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:13.007 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:13.007 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:13.007 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:13.008 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:51:13.008 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:51:13.008 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:51:13.008 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:51:13.008 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:51:13.008 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:51:13.008 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:51:13.008 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3464 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:51:13.008 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3464 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:51:13.008 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3464 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:51:13.008 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3464 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:51:13.008 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3464 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:51:13.008 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3464 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:51:13.008 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3464 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:51:18.010 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:51:18.010 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:51:18.010 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:51:18.010 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:51:18.010 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:51:18.010 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:51:18.014 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:51:18.014 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:51:18.014 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:51:18.014 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:51:18.014 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:51:18.016 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:51:18.016 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:51:18.016 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:51:18.016 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:51:18.016 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:51:18.016 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:51:18.016 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:51:18.016 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:51:18.016 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:18.017 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:51:18.017 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:51:18.017 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:51:18.018 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:51:18.018 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:51:18.018 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:51:18.018 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:51:18.018 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:51:18.018 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:18.019 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:51:18.019 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:51:18.019 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:51:18.019 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:51:18.019 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:51:18.019 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:51:18.019 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:51:18.019 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:51:18.019 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:18.021 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:51:18.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:51:18.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:51:18.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:51:18.021 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:51:18.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:51:18.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:51:18.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:51:18.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:18.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:51:18.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:18.021 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:51:18.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:18.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:18.021 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:18.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:51:18.022 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:51:18.022 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:51:18.022 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:18.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:18.026 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:51:18.489 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:51:18.537 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:51:18.537 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:51:18.538 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:51:18.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:51:18.547 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:51:18.547 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:51:18.547 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:51:18.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:51:18.550 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:51:18.550 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:51:18.550 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:51:18.550 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:51:18.579 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:51:18.581 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:51:18.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:51:18.588 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:51:18.588 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:51:18.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:51:18.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:51:18.953 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:51:19.025 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:19.025 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:19.025 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:19.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:19.417 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:51:19.882 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:51:20.025 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:20.025 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:20.025 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:20.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:20.346 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:51:20.809 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:51:21.026 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:21.026 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:21.026 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:21.026 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:21.273 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:51:21.737 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:51:22.026 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:22.026 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:22.026 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:22.026 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:22.201 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:51:22.665 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:51:23.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:23.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:23.027 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:23.027 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:23.128 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:51:23.591 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:51:24.055 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:51:24.519 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:51:24.983 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:51:25.447 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:51:25.910 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:51:26.374 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:51:26.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:51:26.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:51:26.590 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:51:26.590 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:51:26.592 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:26.592 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:26.592 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:26.593 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:26.594 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:51:26.594 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:51:26.594 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:51:26.594 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:51:26.594 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:51:26.594 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:51:26.594 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:51:26.594 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1886 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:51:26.594 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1886 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:51:26.594 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1886 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:51:26.594 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1886 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:51:26.594 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1886 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:51:31.596 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:51:31.596 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:51:31.596 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:51:31.596 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:51:31.596 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:51:31.596 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:51:31.605 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:51:31.606 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:51:31.606 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:51:31.606 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:51:31.606 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:51:31.608 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:51:31.608 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:51:31.609 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:51:31.609 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:51:31.609 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:51:31.609 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:51:31.609 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:51:31.609 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:51:31.609 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:31.611 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:51:31.612 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:51:31.612 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:51:31.612 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:51:31.612 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:51:31.612 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:51:31.612 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:51:31.612 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:51:31.612 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:31.615 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:51:31.615 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:51:31.615 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:51:31.615 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:51:31.615 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:51:31.615 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:51:31.615 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:51:31.615 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:51:31.615 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:31.619 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:51:31.619 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:51:31.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:51:31.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:51:31.619 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:51:31.619 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:51:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:51:31.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:51:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:51:31.620 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:51:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:31.620 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:31.620 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:51:31.620 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:51:31.620 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:51:31.620 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:51:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:31.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:51:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:31.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:31.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:31.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:31.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:31.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:31.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:31.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:31.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:31.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:31.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:31.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:31.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:31.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:31.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:31.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:31.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:31.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:31.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:31.625 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:51:32.090 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:51:32.141 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:51:32.141 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:51:32.142 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:51:32.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:51:32.148 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:51:32.148 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:51:32.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:51:32.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:51:32.151 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:51:32.151 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:51:32.151 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:51:32.151 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:51:32.179 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:51:32.179 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:51:32.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:51:32.184 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:51:32.184 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:51:32.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:51:32.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:51:32.553 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:51:32.624 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:32.624 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:32.625 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:32.630 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:33.018 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:51:33.482 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:51:33.624 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:33.624 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:33.625 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:33.630 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:33.945 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:51:34.410 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:51:34.625 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:34.625 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:34.626 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:34.631 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:34.874 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:51:35.339 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:51:35.626 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:35.626 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:35.627 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:35.631 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:35.805 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:51:36.271 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:51:36.627 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:36.627 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:36.627 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:36.632 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:36.736 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:51:37.202 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:51:37.667 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:51:38.131 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:51:38.595 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:51:39.058 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:51:39.521 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:51:39.984 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:51:40.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:51:40.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:51:40.186 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:51:40.186 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:51:40.189 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:40.189 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:40.189 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:40.189 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:40.190 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:51:40.190 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:51:40.190 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:51:40.190 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:51:40.190 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:51:40.190 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:51:40.190 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:51:40.190 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1883 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:51:40.190 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1883 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:51:40.190 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1883 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:51:40.190 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1883 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:51:40.190 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1883 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:51:40.191 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1883 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:51:45.193 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:51:45.193 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:51:45.193 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:51:45.193 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:51:45.193 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:51:45.193 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:51:45.200 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:51:45.201 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:51:45.201 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:51:45.201 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:51:45.201 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:51:45.203 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:51:45.203 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:51:45.203 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:51:45.203 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:51:45.203 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:51:45.203 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:51:45.203 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:51:45.203 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:51:45.203 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:45.205 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:51:45.206 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:51:45.206 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:51:45.206 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:51:45.206 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:51:45.206 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:51:45.206 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:51:45.206 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:51:45.206 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:45.208 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:51:45.208 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:51:45.208 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:51:45.208 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:51:45.208 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:51:45.208 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:51:45.208 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:51:45.208 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:51:45.209 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:45.212 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:51:45.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:51:45.212 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:51:45.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:51:45.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:51:45.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:51:45.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:51:45.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:51:45.213 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:51:45.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:45.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:51:45.213 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:45.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:45.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:45.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:45.213 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:51:45.213 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:51:45.213 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:51:45.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:45.213 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:51:45.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:45.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:45.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:51:45.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:45.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:45.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:45.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:45.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:45.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:45.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:45.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:45.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:45.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:45.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:45.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:45.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:45.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:45.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:45.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:45.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:45.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:45.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:45.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:45.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:45.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:45.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:45.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:45.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:45.218 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:51:45.681 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:51:45.732 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:51:45.733 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:51:45.734 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:51:45.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:51:45.741 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:51:45.741 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:51:45.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:51:45.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:51:45.744 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:51:45.744 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:51:45.744 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:51:45.744 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:51:45.771 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:51:45.772 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:51:45.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:51:45.777 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:51:45.777 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:51:45.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:51:45.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:51:46.146 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:51:46.217 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:46.217 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:46.218 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:46.222 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:46.332 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:51:46.333 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:51:46.333 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:51:46.334 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:46.334 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:46.334 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:46.334 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:46.335 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:51:46.335 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:51:46.336 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:51:46.336 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:51:46.336 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:51:46.336 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:51:46.336 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:51:51.338 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:51:51.338 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:51:51.339 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:51:51.339 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:51:51.339 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:51:51.339 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:51:51.344 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:51:51.345 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:51:51.345 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:51:51.345 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:51:51.345 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:51:51.347 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:51:51.347 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:51:51.347 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:51:51.348 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:51:51.348 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:51:51.348 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:51:51.348 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:51:51.348 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:51:51.348 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:51.350 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:51:51.351 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:51:51.351 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:51:51.351 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:51:51.351 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:51:51.351 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:51:51.351 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:51:51.351 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:51:51.351 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:51.353 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:51:51.353 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:51:51.354 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:51:51.354 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:51:51.354 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:51:51.354 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:51:51.354 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:51:51.354 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:51:51.354 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:51.358 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:51:51.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:51:51.358 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:51:51.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:51:51.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:51:51.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:51:51.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:51:51.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:51:51.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:51:51.358 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:51:51.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:51.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:51.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:51.358 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:51.359 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:51:51.359 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:51:51.359 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:51:51.359 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:51:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:51.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:51:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:51.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:51.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:51.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:51.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:51.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:51.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:51.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:51.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:51.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:51.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:51.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:51.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:51.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:51.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:51.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:51.363 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:51:51.830 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:51:51.884 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:51:51.885 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:51:51.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:51:51.886 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:51:51.899 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:51:51.900 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:51:51.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:51:51.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:51:51.904 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:51:51.904 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:51:51.904 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:51:51.904 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:51:51.921 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:51:51.924 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:51:51.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:51:51.934 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:51:51.934 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:51:51.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:51:51.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:51:52.296 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:51:52.363 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:52.364 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:52.364 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:52.365 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:52.481 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:51:52.481 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:51:52.481 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:51:52.483 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:52.483 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:52.483 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:52.483 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:52.485 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:51:52.485 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:51:52.485 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:51:52.485 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:51:52.485 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:51:52.485 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:51:52.485 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:51:57.486 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:51:57.486 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:51:57.486 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:51:57.486 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:51:57.486 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:51:57.486 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:51:57.489 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:51:57.490 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:51:57.490 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:51:57.490 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:51:57.490 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:51:57.491 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:51:57.491 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:51:57.491 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:51:57.491 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:51:57.491 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:51:57.491 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:51:57.491 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:51:57.491 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:51:57.491 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:57.492 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:51:57.492 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:51:57.492 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:51:57.492 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:51:57.492 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:51:57.492 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:51:57.492 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:51:57.492 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:51:57.492 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:57.493 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:51:57.493 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:51:57.493 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:51:57.493 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:51:57.494 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:51:57.494 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:51:57.494 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:51:57.494 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:51:57.494 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:57.495 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:51:57.495 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:51:57.495 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:51:57.495 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:51:57.495 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:51:57.495 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:51:57.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:51:57.495 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:51:57.495 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:51:57.496 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:51:57.496 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:51:57.496 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:51:57.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:57.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:51:57.500 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:51:57.964 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:51:58.016 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:51:58.018 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:51:58.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:51:58.019 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:51:58.037 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:51:58.037 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:51:58.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:51:58.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:51:58.042 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:51:58.042 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:51:58.042 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:51:58.042 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:51:58.054 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:51:58.055 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:51:58.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:51:58.066 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:51:58.067 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:51:58.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:51:58.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:51:58.430 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:51:58.499 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:58.499 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:58.500 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:58.501 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:58.615 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:51:58.615 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:51:58.616 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:51:58.617 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:51:58.617 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:51:58.617 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:51:58.617 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:51:58.618 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:51:58.619 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:51:58.619 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:51:58.619 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:51:58.619 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:51:58.619 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:51:58.619 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:52:03.623 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:52:03.998 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:52:03.999 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:52:03.999 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:52:03.999 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:52:03.999 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:52:04.002 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:52:04.004 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:52:04.004 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:52:04.004 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:52:04.004 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:52:04.006 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:52:04.006 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:52:04.006 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:52:04.006 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:52:04.006 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:52:04.006 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:52:04.006 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:52:04.006 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:52:04.006 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:52:04.009 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:52:04.009 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:52:04.010 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:52:04.010 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:52:04.010 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:52:04.010 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:52:04.011 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:52:04.011 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:52:04.011 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:52:04.014 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:52:04.015 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:52:04.015 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:52:04.015 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:52:04.015 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:52:04.015 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:52:04.015 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:52:04.015 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:52:04.015 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:52:04.019 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:52:04.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:52:04.019 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:52:04.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:52:04.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:52:04.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:52:04.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:52:04.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:52:04.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:52:04.020 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:52:04.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:52:04.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:52:04.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:52:04.020 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:52:04.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:52:04.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:52:04.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:52:04.020 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:52:04.020 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:52:04.020 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:52:04.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:52:04.020 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:52:04.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:52:04.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:52:04.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:52:04.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:52:04.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:52:04.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:52:04.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:52:04.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:52:04.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:52:04.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:52:04.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:52:04.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:52:04.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:52:04.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:52:04.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:52:04.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:52:04.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:52:04.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:52:04.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:52:04.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:52:04.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:52:04.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:52:04.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:52:04.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:52:04.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:52:04.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:52:04.025 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:52:04.489 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:52:04.541 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:52:04.542 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:52:04.542 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:52:04.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:52:04.549 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:52:04.549 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:52:04.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:52:04.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:04.551 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:52:04.551 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:52:04.551 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:52:04.551 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:52:04.579 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:52:04.580 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:52:04.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:52:04.587 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:52:04.587 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:52:04.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:04.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:04.953 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:52:05.024 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:52:05.024 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:52:05.024 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:52:05.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:52:05.417 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:52:05.881 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:52:06.024 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:52:06.024 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:52:06.024 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:52:06.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:52:06.344 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:52:06.807 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:52:07.025 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:52:07.025 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:52:07.025 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:52:07.026 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:52:07.271 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:52:07.734 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:52:08.025 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:52:08.025 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:52:08.025 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:52:08.026 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:52:08.197 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:52:08.661 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:52:09.025 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:52:09.025 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:52:09.025 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:52:09.027 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:52:09.124 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:52:09.587 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:52:10.051 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:52:10.515 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:52:10.979 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:52:11.442 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:52:11.906 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:52:12.369 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:52:12.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:52:12.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:12.591 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:52:12.591 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:52:12.604 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:52:12.604 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:52:12.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:52:12.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:12.606 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:52:12.606 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:52:12.606 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:52:12.606 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:52:12.647 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:52:12.648 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:52:12.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:52:12.656 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:52:12.656 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-06 02:52:12.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:12.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:12.833 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:52:13.296 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:52:13.529 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:52:13.530 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:52:13.530 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:52:13.535 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:52:13.535 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:52:13.535 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:52:13.536 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:52:13.537 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:52:13.537 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:52:13.537 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:52:13.537 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:52:13.537 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:52:13.538 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:52:13.538 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:52:13.538 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2094 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:52:13.538 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2094 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:52:13.538 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2094 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:52:13.538 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2094 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:52:13.538 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2094 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:52:13.538 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2094 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:52:18.538 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:52:18.538 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:52:18.538 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:52:18.538 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:52:18.538 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:52:18.538 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:52:18.542 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:52:18.543 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:52:18.543 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:52:18.543 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:52:18.543 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:52:18.544 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:52:18.544 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:52:18.544 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:52:18.544 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:52:18.544 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:52:18.544 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:52:18.544 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:52:18.544 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:52:18.544 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:52:18.545 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:52:18.545 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:52:18.545 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:52:18.545 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:52:18.546 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:52:18.546 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:52:18.546 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:52:18.546 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:52:18.546 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:52:18.547 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:52:18.547 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:52:18.547 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:52:18.547 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:52:18.547 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:52:18.547 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:52:18.547 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:52:18.547 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:52:18.547 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:52:18.549 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:52:18.549 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:52:18.549 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:52:18.549 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:52:18.549 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:52:18.549 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:52:18.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:52:18.549 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:52:18.549 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:52:18.549 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:52:18.549 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:52:18.549 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:52:18.549 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:52:18.550 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:52:18.550 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:52:18.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:52:18.554 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:52:19.019 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:52:19.067 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:52:19.068 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:52:19.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:52:19.069 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:52:19.076 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:52:19.076 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:52:19.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:52:19.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:19.078 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:52:19.078 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:52:19.078 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:52:19.078 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:52:19.108 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:52:19.109 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:52:19.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:52:19.113 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:52:19.113 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:52:19.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:19.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:19.483 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:52:19.553 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:52:19.553 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:52:19.554 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:52:19.558 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:52:19.669 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:52:19.669 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:52:19.669 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:52:19.669 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:52:19.670 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:52:19.670 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:52:19.670 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:52:19.670 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:52:19.670 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:52:19.670 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:52:19.670 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:52:19.671 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:52:19.671 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:52:19.671 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:52:19.671 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=247 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:52:19.671 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=247 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:52:19.671 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=247 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:52:19.671 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=247 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:52:19.671 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=247 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:52:19.671 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=247 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:52:24.679 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:52:24.679 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:52:24.679 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:52:24.679 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:52:24.679 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:52:24.679 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:52:24.686 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:52:24.686 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:52:24.686 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:52:24.686 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:52:24.686 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:52:24.687 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:52:24.687 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:52:24.687 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:52:24.687 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:52:24.687 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:52:24.687 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:52:24.687 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:52:24.687 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:52:24.687 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:52:24.688 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:52:24.688 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:52:24.688 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:52:24.688 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:52:24.689 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:52:24.689 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:52:24.689 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:52:24.689 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:52:24.689 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:52:24.691 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:52:24.691 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:52:24.691 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:52:24.691 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:52:24.691 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:52:24.691 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:52:24.691 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:52:24.691 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:52:24.691 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:52:24.693 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:52:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:52:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:52:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:52:24.693 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:52:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:52:24.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:52:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:52:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:52:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:52:24.693 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:52:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:52:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:52:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:52:24.693 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:52:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:52:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:52:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:52:24.693 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:52:24.693 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:52:24.693 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:52:24.693 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:52:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:52:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:52:24.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:52:24.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:52:24.694 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:52:24.694 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:52:24.694 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:52:24.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:52:24.694 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:52:24.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:52:24.694 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:52:24.694 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:52:24.694 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:52:24.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:52:24.694 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:52:24.694 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:52:24.694 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:52:24.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:52:24.694 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:52:24.694 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:52:24.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:52:24.694 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:52:24.694 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:52:24.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:52:24.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:52:24.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:52:24.698 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:52:25.164 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:52:25.627 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:52:25.630 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:52:25.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:52:25.631 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:52:25.636 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:52:25.661 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:52:25.661 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:52:25.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:52:25.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:25.670 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:52:25.671 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:52:25.671 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:52:25.671 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:52:25.682 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:52:25.685 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:52:25.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:52:25.693 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:52:25.693 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:52:25.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:25.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:25.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:52:25.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:52:25.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:52:25.695 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:52:26.102 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:52:26.571 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:52:26.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:52:26.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:52:26.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:52:26.696 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:52:27.039 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:52:27.502 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:52:27.697 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:52:27.697 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:52:27.697 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:52:27.697 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:52:27.966 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:52:28.429 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:52:28.697 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:52:28.697 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:52:28.697 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:52:28.697 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:52:28.892 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:52:29.354 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:52:29.698 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:52:29.698 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:52:29.698 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:52:29.698 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:52:29.817 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:52:30.280 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:52:30.743 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:52:31.206 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:52:31.669 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:52:32.132 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:52:32.595 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:52:33.057 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:52:33.520 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:52:33.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:52:33.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:33.694 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:52:33.694 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:52:33.700 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:52:33.700 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:52:33.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:52:33.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:33.702 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:52:33.702 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:52:33.702 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:52:33.702 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:52:33.750 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:52:33.751 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:52:33.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:52:33.754 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:52:33.754 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:52:33.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:33.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:33.983 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:52:34.447 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:52:34.910 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:52:35.373 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:52:35.835 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:52:36.298 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:52:36.762 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:52:37.226 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:52:37.691 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:52:38.158 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:52:38.625 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:52:39.090 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:52:39.555 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:52:40.021 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:52:40.486 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:52:40.950 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:52:41.420 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:52:41.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:52:41.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:41.758 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:52:41.758 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:52:41.771 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:52:41.772 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:52:41.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:52:41.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:41.773 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:52:41.773 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:52:41.773 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:52:41.773 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:52:41.790 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:52:41.791 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:52:41.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:52:41.795 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:52:41.795 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:52:41.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:41.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:41.886 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:52:42.353 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:52:42.818 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:52:43.283 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:52:43.748 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:52:44.213 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:52:44.683 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:52:45.151 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 02:52:45.615 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 02:52:46.082 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 02:52:46.547 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 02:52:47.010 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 02:52:47.479 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 02:52:47.946 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 02:52:48.413 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 02:52:48.878 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 02:52:49.346 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 02:52:49.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:52:49.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:49.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:52:49.801 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:52:49.813 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 02:52:49.814 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:52:49.814 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:52:49.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:52:49.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:49.815 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:52:49.815 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:52:49.815 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:52:49.815 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:52:49.856 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:52:49.860 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:52:49.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:52:49.871 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:52:49.871 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:52:49.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:49.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:50.280 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 02:52:50.744 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 02:52:51.210 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 02:52:51.680 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 02:52:52.144 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 02:52:52.613 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 02:52:53.082 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 02:52:53.550 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 02:52:54.021 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 02:52:54.486 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 02:52:54.957 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 02:52:55.421 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 02:52:55.887 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 02:52:56.353 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 02:52:56.817 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 02:52:57.280 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 02:52:57.746 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 02:52:57.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:52:57.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:52:57.878 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:52:57.878 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:52:57.888 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:52:57.889 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:52:57.889 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:52:57.889 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:52:57.893 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:52:57.893 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:52:57.893 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:52:57.893 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:52:57.893 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:52:57.894 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:52:57.894 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:52:57.894 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7276 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:52:57.894 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7276 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:52:57.894 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7276 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:52:57.894 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7276 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:52:57.895 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7276 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:52:57.895 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7276 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:53:02.890 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:53:02.890 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:53:02.891 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:53:02.891 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:53:02.891 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:53:02.891 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:53:02.894 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:53:02.894 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:53:02.894 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:53:02.894 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:53:02.894 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:53:02.896 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:53:02.896 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:53:02.896 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:53:02.896 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:53:02.896 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:53:02.896 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:53:02.896 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:53:02.896 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:53:02.896 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:02.897 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:53:02.897 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:53:02.897 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:53:02.897 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:53:02.897 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:53:02.897 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:53:02.897 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:53:02.897 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:53:02.898 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:02.898 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:53:02.899 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:53:02.899 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:53:02.899 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:53:02.899 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:53:02.899 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:53:02.899 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:53:02.899 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:53:02.899 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:02.900 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:53:02.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:53:02.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:53:02.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:53:02.900 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:53:02.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:53:02.901 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:53:02.901 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:53:02.901 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:02.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:02.905 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:53:03.371 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:53:03.413 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:53:03.413 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:53:03.414 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:53:03.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:53:03.421 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:53:03.421 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:53:03.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:53:03.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:53:03.423 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:53:03.423 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:53:03.423 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:53:03.423 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:53:03.460 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:53:03.461 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:53:03.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:53:03.467 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:53:03.467 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:53:03.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:53:03.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:53:03.839 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:53:03.903 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:03.903 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:03.903 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:03.903 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:04.306 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:53:04.772 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:53:04.904 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:04.904 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:04.904 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:04.904 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:04.999 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:53:05.000 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:53:05.000 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:53:05.004 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:05.005 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:05.005 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:05.005 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:05.005 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:53:05.006 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:53:05.006 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:53:05.006 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:53:05.006 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:53:05.006 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:53:05.006 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:53:05.006 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=461 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:53:05.006 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=461 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:53:05.006 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=461 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:53:05.006 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=461 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:53:05.006 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=461 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:53:05.006 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=461 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:53:05.006 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=461 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:53:05.006 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=461 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:53:10.011 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:53:10.011 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:53:10.011 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:53:10.011 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:53:10.011 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:53:10.011 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:53:10.020 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:53:10.021 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:53:10.021 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:53:10.021 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:53:10.021 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:53:10.025 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:53:10.025 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:53:10.025 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:53:10.026 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:53:10.026 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:53:10.026 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:53:10.026 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:53:10.026 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:53:10.026 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:10.029 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:53:10.029 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:53:10.029 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:53:10.029 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:53:10.029 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:53:10.029 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:53:10.029 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:53:10.029 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:53:10.029 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:10.031 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:53:10.031 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:53:10.031 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:53:10.031 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:53:10.032 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:53:10.032 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:53:10.032 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:53:10.032 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:53:10.032 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:10.035 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:53:10.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:53:10.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:53:10.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:53:10.035 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:53:10.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:53:10.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:53:10.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:10.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:53:10.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:53:10.035 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:53:10.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:10.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:10.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:10.035 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:10.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:10.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:10.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:10.035 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:53:10.035 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:53:10.035 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:53:10.035 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:53:10.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:10.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:10.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:10.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:53:10.036 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:10.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:10.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:10.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:10.036 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:10.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:10.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:10.036 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:10.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:10.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:10.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:10.036 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:10.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:10.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:10.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:10.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:10.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:10.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:10.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:10.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:10.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:10.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:10.040 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:53:10.508 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:53:10.559 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:53:10.560 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:53:10.561 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:53:10.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:53:10.575 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:53:10.575 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:53:10.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:53:10.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:53:10.582 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:53:10.582 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:53:10.582 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:53:10.582 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:53:10.599 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:53:10.603 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:53:10.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:53:10.619 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:53:10.619 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:53:10.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:53:10.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:53:10.972 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:53:11.038 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:11.038 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:11.039 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:11.039 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:11.166 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:53:11.166 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:53:11.166 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:53:11.171 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:11.171 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:11.171 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:11.171 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:11.172 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:53:11.172 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:53:11.172 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:53:11.172 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:53:11.172 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:53:11.172 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:53:11.172 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:53:16.178 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:53:16.178 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:53:16.178 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:53:16.178 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:53:16.178 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:53:16.178 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:53:16.187 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:53:16.190 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:53:16.190 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:53:16.190 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:53:16.191 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:53:16.196 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:53:16.196 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:53:16.196 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:53:16.197 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:53:16.197 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:53:16.197 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:53:16.197 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:53:16.197 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:53:16.197 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:16.200 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:53:16.201 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:53:16.201 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:53:16.201 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:53:16.201 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:53:16.201 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:53:16.201 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:53:16.201 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:53:16.201 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:16.204 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:53:16.204 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:53:16.204 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:53:16.204 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:53:16.204 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:53:16.204 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:53:16.204 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:53:16.204 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:53:16.204 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:16.207 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:53:16.207 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:53:16.207 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:53:16.207 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:53:16.207 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:53:16.207 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:53:16.207 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:53:16.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:53:16.207 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:16.207 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:53:16.207 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:53:16.207 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:16.207 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:16.207 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:16.207 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:16.207 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:16.207 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:16.207 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:16.207 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:53:16.207 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:53:16.207 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:53:16.207 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:53:16.207 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:16.207 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:16.207 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:16.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:53:16.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:16.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:16.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:16.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:16.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:16.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:16.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:16.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:16.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:16.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:16.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:16.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:16.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:16.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:16.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:16.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:16.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:16.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:16.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:16.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:16.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:16.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:16.212 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:53:16.677 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:53:16.727 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:53:16.728 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:53:16.729 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:53:16.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:53:16.741 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:53:16.741 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:53:16.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:53:16.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:53:16.744 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:53:16.744 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:53:16.744 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:53:16.744 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:53:16.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:53:16.782 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:53:16.782 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:53:16.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:53:16.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:53:17.143 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:53:17.209 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:17.210 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:17.210 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:17.210 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:17.610 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:53:18.076 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:53:18.210 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:18.210 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:18.211 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:18.211 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:18.542 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:53:19.006 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:53:19.211 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:19.211 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:19.211 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:19.212 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:19.470 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:53:19.936 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:53:20.212 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:20.212 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:20.212 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:20.213 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:20.400 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:53:20.868 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:53:21.213 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:21.213 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:21.213 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:21.214 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:21.334 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:53:21.800 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:53:22.265 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:53:22.734 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:53:23.201 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:53:23.665 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:53:24.130 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:53:24.594 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:53:24.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:53:24.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:53:24.791 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:53:24.791 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:53:24.808 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:24.808 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:24.808 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:24.809 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:24.812 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:53:24.813 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:53:24.813 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:53:24.813 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:53:24.813 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:53:24.813 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:53:24.813 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:53:24.814 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1885 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:53:24.814 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1885 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:53:24.814 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1885 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:53:24.814 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1885 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:53:24.814 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1885 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:53:24.814 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1885 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:53:29.814 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:53:29.814 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:53:29.815 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:53:29.815 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:53:29.815 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:53:29.815 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:53:29.822 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:53:29.822 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:53:29.822 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:53:29.822 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:53:29.822 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:53:29.824 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:53:29.824 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:53:29.824 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:53:29.824 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:53:29.824 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:53:29.824 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:53:29.824 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:53:29.824 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:53:29.824 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:29.825 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:53:29.825 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:53:29.825 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:53:29.825 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:53:29.825 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:53:29.825 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:53:29.825 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:53:29.825 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:53:29.825 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:29.826 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:53:29.826 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:53:29.826 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:53:29.826 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:53:29.826 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:53:29.826 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:53:29.827 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:53:29.827 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:53:29.827 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:29.828 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:53:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:53:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:53:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:53:29.828 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:53:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:53:29.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:53:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:53:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:53:29.828 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:53:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:29.828 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:53:29.829 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:53:29.829 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:53:29.829 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:29.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:29.833 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:53:30.298 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:53:30.341 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:53:30.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:53:30.342 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:53:30.342 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:53:30.349 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:53:30.349 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:53:30.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:53:30.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:53:30.350 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:53:30.350 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:53:30.350 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:53:30.350 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:53:30.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:53:30.405 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:53:30.405 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:53:30.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:53:30.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:53:30.764 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:53:30.831 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:30.831 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:30.831 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:30.832 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:31.227 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:53:31.691 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:53:31.832 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:31.832 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:31.832 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:31.832 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:32.155 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:53:32.618 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:53:32.833 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:32.833 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:32.833 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:32.833 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:33.082 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:53:33.548 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:53:33.833 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:33.833 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:33.833 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:33.833 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:34.013 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:53:34.477 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:53:34.834 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:34.834 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:34.834 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:34.834 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:34.942 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:53:35.406 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:53:35.869 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:53:36.333 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:53:36.797 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:53:37.260 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:53:37.724 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:53:38.189 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:53:38.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:53:38.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:53:38.408 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:53:38.408 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:53:38.408 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:53:38.414 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:38.414 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:38.414 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:38.414 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:38.415 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:53:38.415 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:53:38.415 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:53:38.415 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:53:38.415 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:53:38.415 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:53:38.415 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:53:43.418 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:53:43.418 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:53:43.419 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:53:43.419 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:53:43.419 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:53:43.419 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:53:43.425 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:53:43.425 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:53:43.426 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:53:43.426 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:53:43.426 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:53:43.427 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:53:43.427 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:53:43.427 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:53:43.427 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:53:43.427 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:53:43.427 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:53:43.427 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:53:43.427 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:53:43.428 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:43.429 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:53:43.429 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:53:43.429 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:53:43.429 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:53:43.429 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:53:43.429 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:53:43.430 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:53:43.430 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:53:43.430 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:43.431 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:53:43.431 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:53:43.432 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:53:43.432 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:53:43.432 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:53:43.432 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:53:43.432 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:53:43.432 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:53:43.432 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:43.435 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:53:43.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:53:43.435 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:53:43.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:53:43.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:53:43.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:53:43.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:53:43.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:53:43.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:43.435 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:53:43.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:43.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:53:43.435 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:43.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:43.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:43.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:43.435 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:53:43.435 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:53:43.435 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:53:43.435 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:53:43.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:43.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:43.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:43.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:53:43.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:43.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:43.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:43.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:43.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:43.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:43.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:43.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:43.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:43.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:43.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:43.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:43.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:43.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:43.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:43.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:43.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:43.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:43.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:43.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:43.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:43.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:43.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:43.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:43.440 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:53:43.904 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:53:43.957 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:53:43.957 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:53:43.958 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:53:43.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:53:43.963 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:53:43.963 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:53:43.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:53:43.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:53:43.965 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:53:43.965 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:53:43.965 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:53:43.965 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:53:44.367 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:53:44.439 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:44.439 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:44.441 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:44.446 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:44.830 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:53:45.293 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:53:45.440 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:45.440 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:45.441 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:45.447 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:45.757 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:53:46.221 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:53:46.440 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:46.440 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:46.442 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:46.447 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:46.685 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:53:47.148 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:53:47.441 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:47.441 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:47.442 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:47.448 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:47.612 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:53:48.076 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:53:48.441 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:48.441 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:48.442 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:48.449 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:48.540 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:53:49.003 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:53:49.467 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:53:49.929 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:53:50.393 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:53:50.553 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:53:50.553 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:53:50.555 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:50.555 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:50.555 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:50.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:50.556 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:53:50.556 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:53:50.556 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:53:50.556 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:53:50.556 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:53:50.556 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:53:50.556 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:53:55.557 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:53:55.558 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:53:55.558 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:53:55.558 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:53:55.558 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:53:55.558 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:53:55.562 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:53:55.562 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:53:55.562 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:53:55.563 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:53:55.563 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:53:55.563 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:53:55.564 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:53:55.564 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:53:55.564 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:53:55.564 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:53:55.564 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:53:55.564 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:53:55.564 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:53:55.564 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:55.565 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:53:55.565 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:53:55.565 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:53:55.565 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:53:55.565 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:53:55.565 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:53:55.565 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:53:55.565 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:53:55.565 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:55.566 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:53:55.566 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:53:55.566 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:53:55.566 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:53:55.566 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:53:55.566 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:53:55.566 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:53:55.566 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:53:55.566 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:55.568 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:53:55.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:53:55.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:53:55.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:53:55.568 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:53:55.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:53:55.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:53:55.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:55.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:53:55.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:53:55.568 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:53:55.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:55.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:55.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:55.568 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:55.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:55.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:55.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:55.568 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:53:55.568 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:53:55.568 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:53:55.568 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:53:55.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:55.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:55.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:55.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:53:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:55.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:55.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:55.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:55.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:55.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:53:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:55.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:55.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:53:55.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:53:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:53:55.573 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:53:56.043 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:53:56.137 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:53:56.139 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:53:56.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:53:56.139 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:53:56.153 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:53:56.153 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:53:56.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:53:56.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:53:56.156 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:53:56.156 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:53:56.157 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:53:56.157 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:53:56.510 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:53:56.571 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:56.571 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:56.571 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:56.571 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:56.982 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:53:57.446 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:53:57.571 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:57.572 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:57.572 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:57.572 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:57.911 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:53:58.376 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:53:58.572 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:58.572 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:58.572 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:58.572 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:58.843 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:53:59.312 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:53:59.573 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:53:59.573 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:53:59.574 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:53:59.574 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:53:59.777 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:54:00.243 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:54:00.575 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:00.575 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:54:00.575 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:54:00.575 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:54:00.710 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:54:00.737 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:00.737 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:54:00.737 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:54:00.737 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:54:00.740 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:54:00.740 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:54:00.741 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:54:00.741 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:54:00.741 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:54:00.741 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:54:00.741 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1130 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:54:00.741 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1130 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:54:00.741 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1130 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:54:00.741 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1130 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:54:00.741 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1130 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:54:00.741 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1130 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:54:01.174 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:54:01.639 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:54:02.103 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:54:02.568 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:54:03.032 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:54:03.500 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:54:03.967 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:54:04.431 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:54:04.894 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:54:05.358 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:54:05.738 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:54:05.738 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:54:05.738 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:54:05.738 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:54:05.738 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:54:05.738 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:54:05.742 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:54:05.742 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:54:05.742 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:54:05.742 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:54:05.742 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:54:05.743 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:54:05.743 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:54:05.743 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:54:05.743 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:54:05.743 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:54:05.743 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:54:05.743 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:54:05.743 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:54:05.743 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:54:05.744 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:54:05.744 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:54:05.744 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:54:05.745 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:54:05.745 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:54:05.745 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:54:05.745 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:54:05.745 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:54:05.745 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:54:05.745 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:54:05.745 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:54:05.745 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:54:05.747 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:54:05.747 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:54:05.747 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:54:05.747 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:54:05.747 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:54:05.747 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:54:05.747 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:54:05.747 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:54:05.747 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:54:05.751 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:54:05.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:54:05.751 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:54:05.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:54:05.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:54:05.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:54:05.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:54:05.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:54:05.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:05.751 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:54:05.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:05.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:54:05.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:05.751 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:05.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:05.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:05.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:05.751 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:54:05.751 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:54:05.751 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:54:05.752 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:54:05.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:05.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:05.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:05.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:54:05.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:05.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:05.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:05.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:05.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:05.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:05.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:05.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:05.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:05.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:05.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:05.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:05.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:05.753 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:54:05.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:05.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:05.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:05.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:05.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:05.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:05.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:05.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:05.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:05.753 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:54:05.753 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:54:05.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:05.753 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:54:05.753 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:54:05.753 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:54:05.753 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:54:10.755 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:54:10.755 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:54:10.755 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:54:10.755 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:54:10.755 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:54:10.755 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:54:10.758 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:54:10.759 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:54:10.759 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:54:10.759 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:54:10.759 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:54:10.760 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:54:10.760 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:54:10.760 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:54:10.760 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:54:10.760 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:54:10.760 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:54:10.760 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:54:10.760 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:54:10.760 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:54:10.761 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:54:10.761 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:54:10.761 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:54:10.761 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:54:10.761 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:54:10.761 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:54:10.761 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:54:10.761 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:54:10.761 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:54:10.762 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:54:10.762 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:54:10.762 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:54:10.762 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:54:10.763 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:54:10.763 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:54:10.763 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:54:10.763 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:54:10.763 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:54:10.764 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:54:10.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:54:10.764 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:54:10.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:54:10.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:54:10.765 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:54:10.765 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:54:10.765 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:10.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:10.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:10.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:10.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:10.770 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:54:11.233 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:54:11.277 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:54:11.278 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:54:11.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:54:11.278 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:54:11.285 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:54:11.285 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:54:11.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:54:11.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:54:11.287 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:54:11.288 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:54:11.288 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:54:11.288 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:54:11.696 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:54:11.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:11.768 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:54:11.768 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:54:11.771 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:54:12.159 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:54:12.624 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:54:12.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:12.769 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:54:12.769 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:54:12.771 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:54:13.088 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:54:13.551 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:54:13.769 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:13.770 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:54:13.770 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:54:13.772 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:54:14.016 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:54:14.479 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:54:14.771 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:14.771 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:54:14.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:54:14.772 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:54:14.943 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:54:15.407 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:54:15.771 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:15.771 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:54:15.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:54:15.772 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:54:15.871 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:54:16.335 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:54:16.798 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:54:16.883 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:17.261 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:54:17.725 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:54:17.884 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:18.188 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:54:18.652 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:54:18.885 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:19.115 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:54:19.579 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:54:19.885 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:20.041 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:54:20.505 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:54:20.886 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:20.886 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:54:20.967 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:54:21.430 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:54:21.894 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:54:22.357 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:54:22.820 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:54:23.282 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:54:23.747 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:54:24.210 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:54:24.673 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:54:24.884 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:54:25.136 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:54:25.599 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:54:25.884 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:26.061 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:54:26.524 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:54:26.885 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:26.987 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:54:27.451 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:54:27.885 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:27.914 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:54:28.379 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:54:28.843 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:54:28.886 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:29.169 [ERROR] udp_link.py:55 (L:0.0.0.0:6702 <-> R:172.18.59.22:6802) BlockingIOError: dropping Tx data
2026-03-06 02:54:29.169 [ERROR] udp_link.py:55 (L:0.0.0.0:6702 <-> R:172.18.59.22:6802) BlockingIOError: dropping Tx data
2026-03-06 02:54:29.169 [ERROR] udp_link.py:55 (L:0.0.0.0:6702 <-> R:172.18.59.22:6802) BlockingIOError: dropping Tx data
2026-03-06 02:54:29.169 [ERROR] udp_link.py:55 (L:0.0.0.0:6702 <-> R:172.18.59.22:6802) BlockingIOError: dropping Tx data
2026-03-06 02:54:29.169 [ERROR] udp_link.py:55 (L:0.0.0.0:6702 <-> R:172.18.59.22:6802) BlockingIOError: dropping Tx data
2026-03-06 02:54:29.169 [ERROR] udp_link.py:55 (L:0.0.0.0:6702 <-> R:172.18.59.22:6802) BlockingIOError: dropping Tx data
2026-03-06 02:54:29.169 [ERROR] udp_link.py:55 (L:0.0.0.0:6702 <-> R:172.18.59.22:6802) BlockingIOError: dropping Tx data
2026-03-06 02:54:29.169 [ERROR] udp_link.py:55 (L:0.0.0.0:6702 <-> R:172.18.59.22:6802) BlockingIOError: dropping Tx data
2026-03-06 02:54:29.629 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:54:30.093 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:54:30.164 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:30.557 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:54:31.022 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:54:31.488 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 02:54:31.952 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 02:54:32.341 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:54:32.341 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:54:32.344 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:32.345 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:54:32.345 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:54:32.345 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:54:32.345 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:54:32.345 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:54:32.345 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:54:32.345 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:54:32.345 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:54:32.345 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:54:32.345 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:54:37.347 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:54:37.347 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:54:37.347 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:54:37.347 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:54:37.347 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:54:37.347 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:54:37.350 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:54:37.351 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:54:37.351 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:54:37.351 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:54:37.351 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:54:37.352 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:54:37.352 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:54:37.352 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:54:37.352 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:54:37.352 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:54:37.352 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:54:37.352 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:54:37.352 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:54:37.352 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:54:37.353 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:54:37.353 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:54:37.353 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:54:37.353 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:54:37.353 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:54:37.353 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:54:37.353 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:54:37.353 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:54:37.353 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:54:37.354 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:54:37.354 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:54:37.354 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:54:37.354 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:54:37.354 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:54:37.354 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:54:37.354 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:54:37.354 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:54:37.354 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:54:37.356 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:54:37.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:54:37.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:54:37.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:54:37.356 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:54:37.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:54:37.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:54:37.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:37.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:54:37.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:54:37.356 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:54:37.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:37.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:37.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:37.356 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:37.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:37.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:37.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:37.356 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:54:37.356 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:54:37.356 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:54:37.357 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:37.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:37.361 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:54:37.825 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:54:37.868 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:54:37.868 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:54:37.868 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:54:37.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:54:37.874 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:54:37.874 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:54:37.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:54:37.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:54:37.876 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:54:37.876 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:54:37.876 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:54:37.876 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:54:37.914 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:54:37.914 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:54:37.916 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 02:54:37.918 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:54:37.918 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:54:37.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:54:37.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:54:38.288 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:54:38.359 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:38.359 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:54:38.359 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:54:38.360 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:54:38.750 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:54:39.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 02:54:39.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:54:39.185 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:54:39.185 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:54:39.188 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:39.188 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:54:39.188 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:54:39.188 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:54:39.188 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:54:39.188 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:54:39.188 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:54:39.188 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:54:39.188 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:54:39.188 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:54:39.189 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:54:44.190 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:54:44.191 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:54:44.191 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:54:44.191 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:54:44.191 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:54:44.191 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:54:44.193 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:54:44.194 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:54:44.194 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:54:44.194 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:54:44.194 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:54:44.196 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:54:44.196 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:54:44.196 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:54:44.196 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:54:44.196 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:54:44.196 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:54:44.196 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:54:44.196 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:54:44.196 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:54:44.198 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:54:44.198 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:54:44.198 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:54:44.198 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:54:44.198 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:54:44.198 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:54:44.198 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:54:44.198 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:54:44.198 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:54:44.200 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:54:44.200 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:54:44.200 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:54:44.200 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:54:44.200 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:54:44.200 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:54:44.200 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:54:44.200 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:54:44.200 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:54:44.203 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:54:44.204 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:54:44.204 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:54:44.204 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:44.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:44.205 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:44.205 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:44.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:44.205 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:44.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:44.205 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:44.205 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:44.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:44.205 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:44.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:44.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:44.209 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:54:44.672 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:54:44.719 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:54:44.719 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:54:44.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:54:44.720 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:54:44.725 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:54:44.726 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:54:44.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:54:44.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:54:44.727 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:54:44.727 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:54:44.727 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:54:44.727 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:54:44.761 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:54:44.761 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:54:44.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 02:54:44.766 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:54:44.766 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:54:44.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:54:44.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:54:45.134 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:54:45.207 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:45.207 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:54:45.207 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:54:45.207 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:54:45.597 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:54:46.031 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 02:54:46.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:54:46.032 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:54:46.032 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:54:46.034 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:46.034 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:54:46.034 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:54:46.034 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:54:46.035 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:54:46.035 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:54:46.035 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:54:46.035 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:54:46.035 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:54:46.035 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:54:46.035 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:54:51.045 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:54:51.045 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:54:51.046 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:54:51.046 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:54:51.046 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:54:51.046 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:54:51.060 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:54:51.061 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:54:51.061 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:54:51.061 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:54:51.061 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:54:51.064 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:54:51.064 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:54:51.064 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:54:51.064 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:54:51.064 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:54:51.064 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:54:51.065 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:54:51.065 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:54:51.065 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:54:51.066 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:54:51.066 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:54:51.066 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:54:51.066 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:54:51.066 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:54:51.066 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:54:51.066 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:54:51.066 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:54:51.066 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:54:51.067 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:54:51.067 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:54:51.068 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:54:51.068 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:54:51.068 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:54:51.068 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:54:51.068 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:54:51.068 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:54:51.068 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:54:51.070 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:54:51.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:54:51.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:54:51.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:54:51.070 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:54:51.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:54:51.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:54:51.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:54:51.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:51.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:54:51.070 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:54:51.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:51.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:51.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:51.070 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:51.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:51.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:51.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:51.070 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:54:51.070 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:54:51.071 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:54:51.071 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:54:51.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:54:51.075 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:54:51.542 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:54:51.592 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:54:51.593 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:54:51.593 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:54:51.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:54:51.599 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:54:51.599 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:54:51.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:54:51.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:54:51.600 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:54:51.600 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:54:51.600 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:54:51.600 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:54:51.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:54:51.634 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:54:51.634 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:54:51.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:54:51.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:54:52.005 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:54:52.073 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:52.073 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:54:52.073 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:54:52.073 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:54:52.468 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:54:52.933 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:54:53.073 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:53.073 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:54:53.073 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:54:53.073 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:54:53.398 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:54:53.939 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:54:54.074 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:54.105 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:54:54.105 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:54:54.105 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:54:54.406 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:54:55.064 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:54:55.106 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:55.106 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:54:55.106 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:54:55.106 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:54:55.527 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:54:55.991 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:54:56.106 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:54:56.107 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:54:56.107 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:54:56.107 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:54:56.455 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:54:56.919 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:54:57.383 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:54:57.850 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:54:58.319 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:54:58.876 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:54:59.340 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:54:59.804 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:55:00.269 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:55:00.734 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:55:01.198 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:55:01.662 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:55:02.126 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:55:02.593 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:55:03.058 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:55:03.523 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:55:03.988 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:55:04.457 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:55:04.924 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:55:05.389 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:55:05.857 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:55:06.326 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:55:06.789 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:55:07.256 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:55:07.721 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:55:08.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:55:08.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:55:08.038 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:55:08.038 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:55:08.039 [WARNING] transceiver.py:257 (MS@172.18.59.22:6700) RX TRXD message (fn=3641 tn=3 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:55:08.052 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:55:08.052 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:55:08.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:55:08.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:55:08.054 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:55:08.054 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:55:08.054 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:55:08.054 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:55:08.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:55:08.103 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:55:08.103 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-06 02:55:08.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:55:08.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:55:08.186 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:55:08.654 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:55:09.119 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:55:09.584 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:55:10.051 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:55:10.515 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:55:10.983 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:55:11.450 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:55:11.916 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 02:55:12.381 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 02:55:12.846 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 02:55:13.312 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 02:55:13.776 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 02:55:14.240 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 02:55:14.713 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 02:55:15.180 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 02:55:15.645 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 02:55:16.109 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 02:55:16.576 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 02:55:17.040 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 02:55:17.506 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 02:55:17.972 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 02:55:18.443 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 02:55:18.912 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 02:55:19.377 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 02:55:19.843 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 02:55:20.312 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 02:55:20.783 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 02:55:21.256 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 02:55:21.730 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 02:55:22.203 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 02:55:22.676 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 02:55:23.149 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 02:55:23.622 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 02:55:23.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:55:23.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:55:23.831 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:55:23.831 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:55:23.831 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:55:23.844 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:55:23.844 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:55:23.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:55:23.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:55:23.846 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:55:23.846 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:55:23.846 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:55:23.846 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:55:23.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:55:23.851 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:55:23.851 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-06 02:55:23.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:55:23.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:55:24.094 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 02:55:24.565 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 02:55:25.033 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 02:55:25.498 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 02:55:25.964 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-06 02:55:26.430 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-06 02:55:26.893 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-06 02:55:27.358 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-06 02:55:27.824 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-06 02:55:28.290 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-06 02:55:28.757 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-06 02:55:29.227 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-06 02:55:29.693 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-06 02:55:30.157 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-06 02:55:30.622 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-06 02:55:31.089 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-06 02:55:31.557 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-06 02:55:32.020 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-06 02:55:32.485 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-06 02:55:32.950 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-06 02:55:33.414 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-06 02:55:33.878 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-06 02:55:34.346 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-06 02:55:34.810 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-06 02:55:35.277 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-06 02:55:35.743 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-06 02:55:36.206 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-06 02:55:36.671 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-06 02:55:37.137 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-06 02:55:37.603 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-06 02:55:38.068 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-06 02:55:38.536 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-06 02:55:39.002 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-06 02:55:39.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:55:39.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:55:39.087 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:55:39.087 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:55:39.087 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:55:39.094 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:55:39.094 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:55:39.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:55:39.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:55:39.096 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:55:39.096 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:55:39.096 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:55:39.096 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:55:39.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:55:39.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:55:39.135 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:55:39.135 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:55:39.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:55:39.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:55:39.467 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-06 02:55:39.935 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-06 02:55:40.402 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-06 02:55:40.867 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-06 02:55:41.333 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-06 02:55:41.800 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-06 02:55:42.264 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-06 02:55:42.731 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-06 02:55:43.196 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-06 02:55:43.662 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-06 02:55:44.127 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-06 02:55:44.594 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-06 02:55:45.057 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-06 02:55:45.520 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-06 02:55:45.983 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-06 02:55:46.447 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-06 02:55:46.911 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-06 02:55:47.376 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-06 02:55:47.841 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-06 02:55:48.306 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-06 02:55:48.771 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-06 02:55:49.236 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-06 02:55:49.700 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-06 02:55:50.165 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-06 02:55:50.630 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-06 02:55:51.095 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-06 02:55:51.560 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-06 02:55:52.025 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-06 02:55:52.608 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-06 02:55:53.072 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-06 02:55:53.535 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-06 02:55:53.999 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-06 02:55:54.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:55:54.444 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:55:54.444 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:55:54.444 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:55:54.446 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:55:54.447 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:55:54.447 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:55:54.447 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:55:54.448 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:55:54.448 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:55:54.448 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:55:54.448 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:55:54.448 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:55:54.448 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:55:54.448 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:55:59.453 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:55:59.453 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:55:59.453 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:55:59.453 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:55:59.453 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:55:59.453 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:55:59.460 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:55:59.461 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:55:59.461 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:55:59.461 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:55:59.461 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:55:59.464 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:55:59.464 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:55:59.464 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:55:59.464 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:55:59.465 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:55:59.465 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:55:59.465 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:55:59.465 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:55:59.465 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:55:59.466 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:55:59.466 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:55:59.466 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:55:59.466 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:55:59.466 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:55:59.467 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:55:59.467 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:55:59.467 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:55:59.467 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:55:59.468 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:55:59.468 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:55:59.468 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:55:59.468 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:55:59.469 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:55:59.469 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:55:59.469 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:55:59.469 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:55:59.469 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:55:59.471 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:55:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:55:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:55:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:55:59.471 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:55:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:55:59.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:55:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:55:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:55:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:55:59.471 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:55:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:55:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:55:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:55:59.471 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:55:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:55:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:55:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:55:59.471 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:55:59.471 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:55:59.471 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:55:59.471 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:55:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:55:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:55:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:55:59.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:55:59.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:55:59.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:55:59.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:55:59.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:55:59.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:55:59.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:55:59.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:55:59.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:55:59.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:55:59.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:55:59.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:55:59.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:55:59.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:55:59.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:55:59.472 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:55:59.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:55:59.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:55:59.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:55:59.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:55:59.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:55:59.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:55:59.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:55:59.473 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:55:59.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:55:59.473 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:55:59.473 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:55:59.473 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:55:59.473 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:55:59.473 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:56:04.477 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:56:04.477 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:56:04.477 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:56:04.477 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:56:04.477 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:56:04.477 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:56:04.482 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:56:04.483 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:56:04.483 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:56:04.483 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:56:04.483 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:56:04.485 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:56:04.486 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:56:04.486 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:56:04.486 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:56:04.486 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:56:04.486 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:56:04.486 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:56:04.486 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:56:04.486 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:56:04.488 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:56:04.488 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:56:04.488 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:56:04.488 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:56:04.488 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:56:04.488 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:56:04.488 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:56:04.488 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:56:04.488 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:56:04.490 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:56:04.490 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:56:04.490 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:56:04.490 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:56:04.490 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:56:04.491 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:56:04.491 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:56:04.491 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:56:04.491 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:56:04.493 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:56:04.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:56:04.493 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:56:04.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:56:04.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:56:04.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:56:04.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:56:04.494 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:56:04.494 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:56:04.494 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:56:04.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:56:04.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:56:04.495 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:56:04.495 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:56:04.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:56:04.495 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:56:04.495 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:56:04.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:56:04.495 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:56:04.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:56:04.495 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:56:04.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:56:04.495 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:56:04.495 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:56:04.499 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:56:04.962 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:56:05.008 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:56:05.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:56:05.008 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:56:05.009 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:56:05.019 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:56:05.019 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:56:05.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:56:05.021 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:56:05.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:56:05.022 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:56:05.022 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:56:05.022 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:56:05.022 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:56:05.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:56:05.058 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:56:05.058 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:56:05.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:56:05.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:56:05.426 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:56:05.497 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:56:05.497 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:56:05.498 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:56:05.500 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:56:05.889 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:56:06.352 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:56:06.498 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:56:06.498 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:56:06.499 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:56:06.500 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:56:06.815 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:56:07.279 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:56:07.498 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:56:07.498 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:56:07.499 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:56:07.501 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:56:07.742 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:56:08.206 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:56:08.499 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:56:08.499 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:56:08.500 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:56:08.501 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:56:08.670 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:56:09.134 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:56:09.499 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:56:09.500 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:56:09.501 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:56:09.502 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:56:09.599 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:56:10.062 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:56:10.527 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:56:10.991 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:56:11.455 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:56:11.920 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:56:12.384 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:56:12.848 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:56:13.312 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:56:13.777 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:56:14.241 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:56:14.705 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:56:15.170 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:56:15.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:56:15.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:56:15.432 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:56:15.432 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:56:15.437 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:56:15.437 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:56:15.437 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:56:15.437 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:56:15.438 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:56:15.438 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:56:15.438 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:56:15.438 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:56:15.438 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:56:15.438 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:56:15.438 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:56:20.443 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:56:20.443 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:56:20.443 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:56:20.443 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:56:20.443 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:56:20.443 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:56:20.450 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:56:20.451 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:56:20.451 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:56:20.451 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:56:20.451 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:56:20.453 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:56:20.454 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:56:20.454 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:56:20.454 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:56:20.454 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:56:20.454 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:56:20.454 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:56:20.454 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:56:20.455 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:56:20.457 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:56:20.457 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:56:20.457 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:56:20.457 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:56:20.457 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:56:20.458 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:56:20.458 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:56:20.458 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:56:20.458 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:56:20.460 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:56:20.461 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:56:20.461 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:56:20.461 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:56:20.461 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:56:20.461 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:56:20.462 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:56:20.462 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:56:20.462 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:56:20.472 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:56:20.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:56:20.472 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:56:20.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:56:20.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:56:20.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:56:20.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:56:20.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:56:20.473 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:56:20.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:56:20.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:56:20.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:56:20.473 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:56:20.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:56:20.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:56:20.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:56:20.473 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:56:20.473 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:56:20.473 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:56:20.473 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:56:20.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:56:20.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:56:20.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:56:20.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:56:20.478 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:56:20.949 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:56:21.030 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:56:21.032 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:56:21.033 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:56:21.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:56:21.082 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:56:21.082 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:56:21.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:56:21.095 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:56:21.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:56:21.100 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:56:21.100 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:56:21.100 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:56:21.100 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:56:21.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:56:21.147 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:56:21.148 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:56:21.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:56:21.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:56:21.420 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:56:21.480 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:56:21.484 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:56:21.494 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:56:21.495 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:56:21.891 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:56:22.362 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:56:22.481 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:56:22.486 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:56:22.496 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:56:22.496 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:56:22.833 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:56:23.304 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:56:23.482 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:56:23.487 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:56:23.497 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:56:23.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:56:23.774 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:56:24.245 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:56:24.483 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:56:24.489 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:56:24.498 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:56:24.498 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:56:24.716 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:56:25.187 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:56:25.484 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:56:25.491 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:56:25.499 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:56:25.499 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:56:25.658 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:56:26.129 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:56:26.599 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:56:27.070 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:56:27.540 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:56:28.011 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:56:28.481 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:56:28.951 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:56:29.421 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:56:29.886 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:56:30.351 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:56:30.817 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:56:31.282 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:56:31.747 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:56:31.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:56:31.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:56:31.910 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:56:31.910 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:56:31.916 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:56:31.916 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:56:31.916 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:56:31.916 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:56:31.917 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:56:31.917 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:56:31.917 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:56:31.917 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:56:31.917 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:56:31.917 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:56:31.917 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:56:36.919 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:56:36.919 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:56:36.919 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:56:36.919 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:56:36.919 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:56:36.919 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:56:36.929 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:56:36.930 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:56:36.930 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:56:36.930 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:56:36.930 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:56:36.932 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:56:36.932 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:56:36.933 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:56:36.933 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:56:36.933 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:56:36.933 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:56:36.933 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:56:36.933 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:56:36.933 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:56:36.936 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:56:36.936 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:56:36.936 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:56:36.936 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:56:36.936 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:56:36.936 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:56:36.936 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:56:36.936 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:56:36.936 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:56:36.939 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:56:36.939 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:56:36.939 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:56:36.939 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:56:36.939 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:56:36.939 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:56:36.939 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:56:36.939 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:56:36.940 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:56:36.944 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:56:36.944 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:56:36.944 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:56:36.944 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:56:36.944 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:56:36.944 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:56:36.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:56:36.944 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:56:36.944 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:56:36.944 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:56:36.945 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:56:36.945 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:56:36.945 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:56:36.945 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:56:36.945 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:56:36.945 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:56:36.945 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:56:36.945 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:56:36.945 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:56:36.945 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:56:36.945 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:56:36.945 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:56:36.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:56:36.945 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:56:36.945 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:56:36.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:56:36.945 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:56:36.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:56:36.945 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:56:36.945 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:56:36.945 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:56:36.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:56:36.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:56:36.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:56:36.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:56:36.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:56:36.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:56:36.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:56:36.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:56:36.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:56:36.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:56:36.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:56:36.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:56:36.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:56:36.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:56:36.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:56:36.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:56:36.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:56:36.950 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:56:37.416 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:56:37.471 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:56:37.472 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:56:37.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:56:37.473 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:56:37.490 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:56:37.490 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:56:37.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:56:37.496 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:56:37.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:56:37.499 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:56:37.499 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:56:37.499 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:56:37.499 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:56:37.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:56:37.513 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:56:37.513 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:56:37.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:56:37.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:56:37.881 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:56:37.949 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:56:37.949 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:56:37.950 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:56:37.956 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:56:38.347 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:56:38.358 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:56:38.812 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:56:38.950 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:56:38.950 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:56:38.951 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:56:38.956 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:56:39.278 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:56:39.744 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:56:39.950 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:56:39.950 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:56:39.951 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:56:39.957 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:56:40.210 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:56:40.675 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:56:40.951 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:56:40.951 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:56:40.951 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:56:40.957 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:56:41.141 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:56:41.606 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:56:41.952 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:56:41.952 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:56:41.952 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:56:41.958 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:56:42.072 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:56:42.537 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:56:43.003 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:56:43.468 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:56:43.934 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:56:44.399 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:56:44.865 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:56:45.331 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:56:45.796 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:56:46.262 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:56:46.728 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:56:47.194 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:56:47.660 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:56:48.125 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:56:48.590 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:56:49.056 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:56:49.521 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:56:50.171 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:56:50.636 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:56:51.102 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:56:51.568 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:56:52.034 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:56:52.500 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:56:52.966 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:56:53.432 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:56:53.897 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:56:54.363 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:56:54.829 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:56:55.295 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:56:55.761 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:56:56.227 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:56:56.693 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:56:57.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:56:57.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:56:57.090 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:56:57.090 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:56:57.096 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:56:57.096 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:56:57.097 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:56:57.097 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:56:57.098 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:56:57.098 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:56:57.098 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:56:57.098 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:56:57.098 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:56:57.098 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:56:57.098 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:57:02.101 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:57:02.102 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:57:02.102 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:57:02.102 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:57:02.102 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:57:02.102 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:57:02.110 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:57:02.110 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:57:02.110 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:57:02.110 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:57:02.110 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:57:02.113 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:57:02.113 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:57:02.113 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:57:02.113 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:57:02.113 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:57:02.114 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:57:02.114 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:57:02.114 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:57:02.114 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:57:02.116 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:57:02.116 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:57:02.117 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:57:02.117 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:57:02.117 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:57:02.117 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:57:02.117 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:57:02.117 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:57:02.117 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:57:02.119 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:57:02.119 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:57:02.119 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:57:02.119 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:57:02.119 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:57:02.120 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:57:02.120 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:57:02.120 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:57:02.120 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:57:02.124 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:57:02.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:57:02.124 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:57:02.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:57:02.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:57:02.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:57:02.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:57:02.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:57:02.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:02.124 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:57:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:57:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:02.125 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:57:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:02.125 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:57:02.125 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:57:02.125 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:57:02.125 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:57:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:02.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:57:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:02.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:02.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:02.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:02.126 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:02.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:02.126 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:02.126 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:02.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:02.126 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:02.126 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:02.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:02.126 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:02.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:02.126 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:02.126 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:02.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:02.126 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:02.130 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:57:02.597 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:57:02.658 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:57:02.660 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:57:02.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:57:02.661 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:57:02.683 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:57:02.684 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:57:02.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:57:02.689 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:57:02.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:57:02.692 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:57:02.693 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:57:02.693 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:57:02.693 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:57:02.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:57:02.743 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:57:02.743 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:57:02.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:57:02.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:57:03.066 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:57:03.130 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:57:03.130 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:57:03.131 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:57:03.136 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:57:03.533 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:57:03.998 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:57:04.019 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:57:04.130 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:57:04.130 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:57:04.132 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:57:04.137 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:57:04.464 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:57:04.930 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:57:04.979 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:57:05.131 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:57:05.131 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:57:05.134 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:57:05.138 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:57:05.416 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:57:05.882 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:57:05.939 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:57:06.132 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:57:06.132 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:57:06.135 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:57:06.139 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:57:06.348 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:57:06.813 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:57:06.890 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:57:07.133 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:57:07.133 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:57:07.136 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:57:07.140 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:57:07.279 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:57:07.744 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:57:07.841 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:57:08.210 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:57:08.675 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:57:08.787 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:57:09.140 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:57:09.606 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:57:09.738 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:57:10.072 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:57:10.538 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:57:10.688 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:57:11.003 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:57:11.469 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:57:11.639 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:57:11.933 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:57:12.399 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:57:12.585 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:57:12.865 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:57:13.332 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:57:13.541 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:57:13.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:57:13.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:57:13.551 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:57:13.551 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:57:13.568 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:57:13.568 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:57:13.568 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:57:13.568 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:57:13.569 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:57:13.569 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:57:13.569 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:57:13.569 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:57:13.569 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:57:13.570 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:57:13.570 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:57:18.571 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:57:18.571 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:57:18.571 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:57:18.572 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:57:18.572 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:57:18.572 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:57:18.580 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:57:18.581 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:57:18.581 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:57:18.581 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:57:18.581 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:57:18.583 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:57:18.583 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:57:18.583 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:57:18.584 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:57:18.584 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:57:18.584 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:57:18.584 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:57:18.584 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:57:18.584 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:57:18.586 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:57:18.586 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:57:18.586 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:57:18.586 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:57:18.586 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:57:18.587 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:57:18.587 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:57:18.587 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:57:18.587 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:57:18.588 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:57:18.589 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:57:18.589 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:57:18.589 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:57:18.589 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:57:18.589 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:57:18.589 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:57:18.589 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:57:18.589 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:57:18.592 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:57:18.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:57:18.592 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:57:18.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:57:18.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:57:18.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:57:18.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:57:18.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:57:18.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:18.593 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:57:18.593 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:18.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:57:18.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:18.593 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:57:18.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:18.593 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:18.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:18.593 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:57:18.593 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:57:18.593 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:57:18.593 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:57:18.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:18.593 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:18.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:18.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:57:18.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:18.593 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:18.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:18.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:18.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:18.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:18.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:18.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:18.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:18.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:18.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:18.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:18.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:18.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:18.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:18.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:18.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:18.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:18.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:18.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:18.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:18.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:18.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:18.598 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:57:19.064 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:57:19.118 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:57:19.120 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:57:19.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:57:19.121 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:57:19.137 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:57:19.137 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:57:19.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:57:19.140 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:57:19.142 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:57:19.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:57:19.144 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:57:19.144 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:57:19.144 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:57:19.144 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:57:19.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:57:19.163 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:57:19.163 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:57:19.163 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:57:19.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:57:19.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:57:19.529 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:57:19.597 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:57:19.597 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:57:19.598 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:57:19.602 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:57:19.995 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:57:20.007 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:57:20.461 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:57:20.598 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:57:20.598 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:57:20.599 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:57:20.602 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:57:20.927 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:57:21.392 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:57:21.598 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:57:21.598 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:57:21.600 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:57:21.603 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:57:21.858 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:57:22.324 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:57:22.599 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:57:22.599 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:57:22.600 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:57:22.603 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:57:22.789 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:57:23.255 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:57:23.599 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:57:23.599 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:57:23.600 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:57:23.604 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:57:23.720 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:57:24.186 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:57:24.651 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:57:25.117 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:57:25.582 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:57:26.048 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:57:26.513 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:57:26.979 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:57:27.445 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:57:27.911 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:57:28.376 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:57:28.842 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:57:29.307 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:57:29.506 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:57:29.772 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:57:30.238 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:57:30.703 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:57:31.168 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:57:31.633 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:57:32.098 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:57:32.564 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:57:33.030 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:57:33.495 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:57:33.961 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:57:34.426 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:57:34.892 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:57:35.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:57:35.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:57:35.206 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:57:35.206 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:57:35.213 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:57:35.213 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:57:35.213 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:57:35.213 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:57:35.214 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:57:35.214 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:57:35.214 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:57:35.214 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:57:35.214 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:57:35.214 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:57:35.214 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:57:35.214 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3642 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:57:35.215 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3642 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:57:35.215 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3642 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:57:35.215 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3642 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:57:35.215 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3642 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:57:35.215 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3642 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:57:40.217 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:57:40.217 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:57:40.217 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:57:40.217 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:57:40.217 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:57:40.217 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:57:40.223 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:57:40.224 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:57:40.224 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:57:40.224 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:57:40.224 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:57:40.226 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:57:40.226 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:57:40.226 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:57:40.227 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:57:40.227 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:57:40.227 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:57:40.227 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:57:40.227 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:57:40.227 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:57:40.229 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:57:40.230 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:57:40.230 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:57:40.230 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:57:40.230 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:57:40.230 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:57:40.230 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:57:40.230 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:57:40.230 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:57:40.233 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:57:40.233 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:57:40.233 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:57:40.233 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:57:40.233 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:57:40.233 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:57:40.233 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:57:40.233 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:57:40.233 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:57:40.237 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:57:40.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:57:40.238 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:57:40.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:57:40.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:57:40.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:57:40.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:57:40.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:57:40.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:40.238 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:57:40.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:40.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:57:40.238 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:57:40.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:40.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:40.238 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:57:40.238 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:57:40.238 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:57:40.238 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:57:40.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:40.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:40.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:40.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:57:40.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:40.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:40.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:40.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:40.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:40.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:40.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:40.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:40.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:40.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:40.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:40.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:40.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:40.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:40.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:40.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:40.240 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:57:40.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:40.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:40.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:40.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:40.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:40.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:40.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:40.240 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:57:40.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:40.240 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:57:40.240 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:57:40.240 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:57:40.240 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:57:40.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:45.245 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:57:45.245 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:57:45.245 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:57:45.245 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:57:45.245 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:57:45.245 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:57:45.252 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:57:45.252 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:57:45.252 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:57:45.253 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:57:45.253 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:57:45.255 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:57:45.255 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:57:45.255 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:57:45.255 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:57:45.255 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:57:45.256 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:57:45.256 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:57:45.256 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:57:45.256 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:57:45.258 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:57:45.258 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:57:45.258 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:57:45.258 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:57:45.259 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:57:45.259 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:57:45.259 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:57:45.259 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:57:45.259 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:57:45.261 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:57:45.262 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:57:45.262 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:57:45.262 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:57:45.262 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:57:45.262 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:57:45.262 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:57:45.262 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:57:45.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:57:45.272 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:57:45.273 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:57:45.273 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:57:45.273 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:57:45.273 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:57:45.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:57:45.273 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:57:45.273 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:57:45.273 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:57:45.273 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:45.273 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:45.273 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:57:45.273 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:57:45.273 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:45.273 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:45.273 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:57:45.273 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:57:45.273 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:57:45.274 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:57:45.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:45.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:45.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:45.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:57:45.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:45.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:45.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:45.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:45.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:45.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:45.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:45.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:45.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:45.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:45.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:45.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:45.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:45.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:45.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:57:45.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:45.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:45.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:45.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:45.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:45.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:57:45.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:57:45.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:45.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:45.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:57:45.278 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:57:45.745 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:57:45.813 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:57:45.814 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:57:45.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:57:45.815 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:57:45.833 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:57:45.833 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:57:45.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:57:45.839 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:57:45.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:57:45.842 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:57:45.842 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:57:45.842 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:57:45.842 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:57:45.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:57:45.890 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:57:45.890 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:57:45.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:57:45.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:57:46.211 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:57:46.281 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:57:46.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:57:46.287 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:57:46.296 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:57:46.677 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:57:47.142 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:57:47.163 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:57:47.282 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:57:47.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:57:47.287 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:57:47.297 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:57:47.608 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:57:48.073 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:57:48.283 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:57:48.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:57:48.288 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:57:48.298 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:57:48.539 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:57:49.004 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:57:49.283 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:57:49.285 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:57:49.288 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:57:49.298 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:57:49.469 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:57:49.935 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:57:50.284 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:57:50.285 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:57:50.288 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:57:50.299 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:57:50.400 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:57:50.866 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:57:51.331 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:57:51.797 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:57:52.262 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:57:52.728 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:57:53.193 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:57:53.659 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:57:54.124 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:57:54.590 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:57:55.055 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:57:55.521 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:57:55.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:57:55.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:57:55.894 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:57:55.894 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:57:55.900 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:57:55.900 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:57:55.900 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:57:55.900 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:57:55.902 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:57:55.902 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:57:55.902 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:57:55.902 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:57:55.902 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:57:55.902 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:57:55.902 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:58:00.903 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:58:00.903 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:58:00.903 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:58:00.903 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:58:00.903 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:58:00.903 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:58:00.913 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:58:00.913 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:58:00.913 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:58:00.914 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:58:00.914 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:58:00.916 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:58:00.916 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:58:00.916 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:58:00.916 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:58:00.916 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:58:00.916 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:58:00.916 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:58:00.916 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:58:00.916 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:00.919 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:58:00.919 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:58:00.919 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:58:00.919 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:58:00.919 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:58:00.919 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:58:00.919 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:58:00.919 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:58:00.919 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:00.922 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:58:00.922 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:58:00.922 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:58:00.922 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:58:00.922 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:58:00.922 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:58:00.922 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:58:00.922 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:58:00.923 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:00.927 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:58:00.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:58:00.927 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:58:00.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:58:00.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:58:00.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:58:00.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:58:00.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:58:00.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:00.927 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:58:00.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:00.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:58:00.927 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:00.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:00.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:00.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:00.927 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:58:00.927 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:58:00.927 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:58:00.927 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:58:00.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:00.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:00.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:00.932 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:58:01.397 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:58:01.452 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:58:01.453 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:58:01.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:01.455 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:58:01.468 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:58:01.468 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:58:01.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:58:01.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:01.471 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:58:01.471 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:58:01.471 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:58:01.471 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:58:01.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:01.495 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:58:01.495 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:58:01.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:01.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:01.864 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:58:01.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:01.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:01.869 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:58:01.869 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:58:01.884 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:58:01.884 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:58:01.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:58:01.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:01.887 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:58:01.887 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:58:01.887 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:58:01.887 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:58:01.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:01.910 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:58:01.910 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:58:01.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:01.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:01.932 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:01.932 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:01.933 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:01.937 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:02.330 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:58:02.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:02.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:02.588 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:58:02.588 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:58:02.588 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:58:02.796 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:58:02.932 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:02.932 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:02.933 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:02.938 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:03.260 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:58:03.565 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:58:03.565 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:58:03.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:58:03.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:03.568 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:58:03.568 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:58:03.568 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:58:03.568 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:58:03.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:03.589 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:58:03.589 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:58:03.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:03.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:03.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:03.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:03.695 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:58:03.696 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:58:03.707 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:58:03.707 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:58:03.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:58:03.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:03.710 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:58:03.710 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:58:03.710 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:58:03.710 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:58:03.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:03.732 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:58:03.732 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:58:03.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:03.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:03.933 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:03.933 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:03.934 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:03.939 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:04.019 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:58:04.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:04.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:04.411 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:58:04.411 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:58:04.411 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:58:04.415 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:04.415 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:04.415 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:04.415 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:04.416 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:58:04.416 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:58:04.416 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:58:04.416 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:58:04.416 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:58:04.416 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:58:04.416 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:58:04.416 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=700 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:58:04.416 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=700 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:58:04.416 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=700 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:58:04.416 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=700 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:58:04.416 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=700 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:58:04.416 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=700 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:58:04.416 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=700 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:58:04.416 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=700 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:58:09.418 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:58:09.418 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:58:09.418 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:58:09.418 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:58:09.418 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:58:09.418 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:58:09.427 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:58:09.428 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:58:09.428 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:58:09.428 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:58:09.428 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:58:09.430 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:58:09.430 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:58:09.430 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:58:09.430 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:58:09.430 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:58:09.430 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:58:09.430 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:58:09.430 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:58:09.430 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:09.433 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:58:09.433 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:58:09.433 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:58:09.433 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:58:09.433 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:58:09.433 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:58:09.433 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:58:09.433 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:58:09.433 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:09.436 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:58:09.436 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:58:09.436 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:58:09.436 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:58:09.436 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:58:09.436 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:58:09.437 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:58:09.437 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:58:09.437 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:09.441 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:58:09.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:58:09.441 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:58:09.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:58:09.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:58:09.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:58:09.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:58:09.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:58:09.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:09.441 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:58:09.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:09.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:58:09.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:09.441 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:09.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:09.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:09.441 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:58:09.441 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:58:09.441 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:58:09.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:09.442 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:58:09.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:58:09.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:09.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:09.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:09.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:09.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:09.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:09.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:09.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:09.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:09.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:09.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:09.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:09.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:09.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:09.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:09.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:09.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:09.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:09.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:09.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:09.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:09.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:09.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:09.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:09.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:09.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:09.447 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:58:09.913 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:58:09.965 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:58:09.966 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:58:09.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:09.967 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:58:09.979 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:58:09.980 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:58:09.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:58:09.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:09.984 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:58:09.984 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:58:09.984 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:58:09.984 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:58:10.003 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:58:10.005 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 02:58:10.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:10.013 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:58:10.014 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:58:10.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:10.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:10.378 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:58:10.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:10.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:10.382 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:58:10.382 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:58:10.386 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:10.386 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:10.386 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:10.386 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:10.387 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:58:10.388 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:58:10.388 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:58:10.388 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:58:10.388 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:58:10.388 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:58:10.388 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:58:15.389 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:58:15.389 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:58:15.389 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:58:15.389 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:58:15.389 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:58:15.389 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:58:15.398 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:58:15.398 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:58:15.398 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:58:15.398 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:58:15.398 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:58:15.400 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:58:15.401 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:58:15.401 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:58:15.401 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:58:15.401 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:58:15.401 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:58:15.401 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:58:15.401 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:58:15.401 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:15.403 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:58:15.404 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:58:15.404 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:58:15.404 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:58:15.404 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:58:15.404 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:58:15.404 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:58:15.404 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:58:15.404 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:15.406 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:58:15.406 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:58:15.406 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:58:15.407 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:58:15.407 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:58:15.407 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:58:15.407 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:58:15.407 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:58:15.407 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:15.411 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:58:15.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:58:15.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:58:15.411 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:58:15.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:58:15.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:58:15.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:58:15.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:58:15.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:15.411 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:58:15.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:15.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:58:15.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:15.411 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:15.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:15.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:15.411 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:58:15.411 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:58:15.411 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:58:15.411 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:15.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:15.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:15.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:15.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:15.416 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:58:15.882 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:58:15.937 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:58:15.938 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:58:15.939 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:58:15.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:15.952 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:58:15.952 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:58:15.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:58:15.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:15.955 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:58:15.955 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:58:15.955 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:58:15.955 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:58:15.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:15.980 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:58:15.980 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:58:15.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:15.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:16.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:16.348 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:58:16.416 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:16.416 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:16.417 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:16.422 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:16.814 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:58:17.279 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:58:17.417 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:17.637 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:17.637 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:17.637 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:17.744 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:58:18.209 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:58:18.638 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:18.638 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:18.638 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:18.638 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:18.674 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:58:19.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:19.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:19.085 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:58:19.085 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:58:19.101 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:58:19.101 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:58:19.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:58:19.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:19.104 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:58:19.104 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:58:19.104 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:58:19.104 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:58:19.139 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:58:19.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:19.144 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:58:19.145 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 02:58:19.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:19.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:19.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:19.604 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:58:19.639 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:19.639 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:19.639 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:19.639 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:20.069 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:58:20.534 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:58:20.640 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:20.640 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:20.640 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:20.640 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:20.999 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:58:21.464 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:58:22.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:22.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:22.301 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:58:22.301 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:58:22.301 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:58:22.318 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:58:22.318 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:58:22.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:58:22.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:22.321 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:58:22.321 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:58:22.321 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:58:22.321 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:58:22.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:22.357 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:58:22.357 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:58:22.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:22.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:22.387 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:58:22.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:22.852 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:58:23.317 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:58:23.783 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:58:24.248 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:58:24.712 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:58:25.177 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:58:25.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:25.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:25.617 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:58:25.617 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:58:25.627 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:58:25.627 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:58:25.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:58:25.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:25.629 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:58:25.629 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:58:25.629 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:58:25.629 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:58:25.641 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:58:25.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:25.649 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:58:25.649 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:58:25.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:25.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:26.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:26.107 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:58:27.265 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:58:27.730 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:58:28.196 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:58:28.661 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:58:29.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:29.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:29.032 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:58:29.032 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:58:29.032 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:58:29.037 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:29.037 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:29.037 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:29.037 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:29.038 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:58:29.038 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:58:29.038 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:58:29.038 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:58:29.038 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:58:29.038 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:58:29.038 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:58:29.038 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2736 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:58:29.038 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2736 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:58:29.038 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2736 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:58:29.038 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2736 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:58:29.038 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2736 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:58:29.038 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2736 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:58:34.040 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:58:34.040 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:58:34.040 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:58:34.040 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:58:34.040 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:58:34.040 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:58:34.049 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:58:34.049 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:58:34.049 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:58:34.049 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:58:34.049 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:58:34.051 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:58:34.052 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:58:34.052 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:58:34.052 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:58:34.052 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:58:34.052 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:58:34.052 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:58:34.052 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:58:34.052 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:34.054 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:58:34.055 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:58:34.055 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:58:34.055 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:58:34.055 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:58:34.055 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:58:34.055 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:58:34.055 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:58:34.055 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:34.057 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:58:34.057 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:58:34.058 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:58:34.058 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:58:34.058 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:58:34.058 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:58:34.058 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:58:34.058 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:58:34.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:34.062 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:58:34.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:58:34.062 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:58:34.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:58:34.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:58:34.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:58:34.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:58:34.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:58:34.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:34.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:58:34.062 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:58:34.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:34.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:34.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:34.062 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:34.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:34.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:34.063 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:58:34.063 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:58:34.063 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:58:34.063 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:58:34.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:34.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:34.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:34.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:58:34.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:34.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:34.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:34.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:34.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:34.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:34.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:34.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:34.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:34.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:34.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:34.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:34.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:34.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:34.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:34.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:34.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:34.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:34.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:34.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:34.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:34.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:34.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:34.067 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:58:34.533 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:58:34.589 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:58:34.590 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:58:34.591 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:58:34.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:34.592 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:58:34.592 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:58:34.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:58:34.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:34.593 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:58:34.593 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:58:34.593 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:58:34.593 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:58:34.999 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:58:35.067 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:35.067 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:35.068 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:35.073 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:35.464 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:58:35.930 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:58:36.067 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:36.067 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:36.069 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:36.074 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:36.395 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:58:36.860 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:58:37.068 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:37.068 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:37.069 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:37.074 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:37.325 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:58:37.790 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:58:38.069 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:38.069 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:38.069 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:38.075 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:38.255 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:58:38.721 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:58:39.069 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:39.070 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:39.070 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:39.075 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:39.187 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:58:39.653 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:58:40.118 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:58:40.583 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:58:41.049 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:58:41.515 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:58:41.981 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:58:42.446 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:58:42.912 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:58:43.378 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:58:43.843 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:58:44.309 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:58:44.775 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:58:45.240 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:58:45.705 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:58:46.170 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:58:46.636 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:58:47.102 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:58:47.567 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:58:48.032 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:58:48.310 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:58:48.310 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:58:48.315 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:48.315 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:48.316 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:48.316 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:48.317 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:58:48.317 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:58:48.317 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:58:48.317 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:58:48.317 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:58:48.317 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:58:48.317 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:58:53.319 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:58:53.319 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:58:53.319 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:58:53.319 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:58:53.319 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:58:53.319 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:58:53.323 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:58:53.324 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:58:53.324 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:58:53.324 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:58:53.324 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:58:53.326 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:58:53.326 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:58:53.326 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:58:53.326 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:58:53.326 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:58:53.326 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:58:53.326 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:58:53.326 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:58:53.326 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:53.329 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:58:53.329 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:58:53.329 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:58:53.329 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:58:53.329 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:58:53.329 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:58:53.329 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:58:53.329 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:58:53.330 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:53.332 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:58:53.332 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:58:53.332 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:58:53.332 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:58:53.332 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:58:53.332 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:58:53.332 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:58:53.332 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:58:53.332 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:53.336 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:58:53.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:58:53.336 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:58:53.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:58:53.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:58:53.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:58:53.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:58:53.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:58:53.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:53.337 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:58:53.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:53.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:58:53.337 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:53.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:53.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:53.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:53.337 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:58:53.337 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:58:53.337 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:58:53.337 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:58:53.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:53.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:53.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:53.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:58:53.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:53.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:53.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:53.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:53.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:53.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:53.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:53.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:53.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:53.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:53.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:53.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:53.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:53.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:53.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:53.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:58:53.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:53.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:58:53.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:53.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:53.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:53.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:58:53.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:53.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:58:53.342 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:58:53.807 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:58:53.861 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:58:53.862 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:58:53.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:53.864 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:58:53.876 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:58:53.876 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:58:53.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:58:53.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:53.879 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:58:53.879 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:58:53.879 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:58:53.879 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:58:53.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:58:53.905 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 02:58:53.905 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 02:58:53.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:53.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:54.272 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:58:54.341 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:54.341 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:54.342 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:54.346 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:54.737 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:58:55.202 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:58:55.342 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:55.342 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:55.343 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:55.346 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:55.667 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:58:55.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:55.905 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:58:55.905 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:58:55.905 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 02:58:55.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:58:55.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:58:55.908 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:58:55.908 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:58:55.908 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:58:55.908 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:58:56.132 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:58:56.343 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:56.343 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:56.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:56.347 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:56.597 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:58:57.062 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:58:57.343 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:57.343 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:57.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:57.348 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:57.528 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:58:57.992 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:58:58.343 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:58:58.343 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:58:58.345 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:58:58.348 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:58:58.457 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:58:58.922 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:58:59.387 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:58:59.853 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:59:00.318 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:59:00.783 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:59:01.248 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:59:01.713 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:59:02.178 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:59:02.643 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:59:03.107 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:59:03.573 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:59:04.038 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:59:04.503 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:59:04.968 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:59:05.433 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:59:05.899 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:59:06.364 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:59:06.829 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:59:07.294 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:59:07.760 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:59:08.225 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:59:08.691 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:59:09.156 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:59:09.621 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:59:10.086 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:59:10.551 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:59:11.016 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:59:11.482 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:59:11.947 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:59:12.413 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:59:12.879 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:59:13.344 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:59:13.809 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 02:59:14.274 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 02:59:14.739 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 02:59:15.204 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 02:59:15.669 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 02:59:16.134 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 02:59:16.599 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 02:59:17.064 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 02:59:17.530 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 02:59:17.995 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 02:59:18.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:59:18.260 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:59:18.260 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:59:18.269 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:59:18.269 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:59:18.269 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:59:18.269 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:59:18.270 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:59:18.270 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:59:18.270 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:59:18.270 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:59:18.270 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:59:18.270 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:59:18.270 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:59:18.270 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5468 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:59:18.270 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5468 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:59:18.270 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5468 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:59:18.271 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5468 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:59:18.271 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5468 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:59:18.271 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5468 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 02:59:23.272 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:59:23.272 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:59:23.272 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:59:23.272 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:59:23.272 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:59:23.272 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:59:23.281 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:59:23.281 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:59:23.281 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:59:23.281 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:59:23.281 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:59:23.284 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:59:23.284 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:59:23.284 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:59:23.284 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:59:23.284 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:59:23.284 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:59:23.284 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:59:23.284 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:59:23.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:59:23.287 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:59:23.287 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:59:23.287 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:59:23.287 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:59:23.287 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:59:23.287 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:59:23.287 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:59:23.287 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:59:23.287 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:59:23.290 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:59:23.290 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:59:23.290 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:59:23.290 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:59:23.290 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:59:23.290 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:59:23.290 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:59:23.290 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:59:23.290 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:59:23.294 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:59:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:59:23.295 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:59:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:59:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:59:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:59:23.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:59:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:59:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:59:23.295 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:59:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:59:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:59:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:59:23.295 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:59:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:59:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:59:23.295 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:59:23.295 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:59:23.295 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:59:23.295 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:59:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:59:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:59:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:59:23.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:59:23.300 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:59:23.766 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:59:23.821 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:59:23.822 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:59:23.822 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:59:23.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:59:23.824 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:59:23.824 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:59:23.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:59:23.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:59:23.824 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:59:23.824 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:59:23.825 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:59:23.825 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:59:24.231 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:59:24.299 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:59:24.300 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:59:24.301 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:59:24.306 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:59:24.696 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:59:25.161 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:59:25.300 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:59:25.301 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:59:25.302 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:59:25.306 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:59:25.625 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:59:26.090 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:59:26.300 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:59:26.301 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:59:26.302 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:59:26.307 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:59:26.554 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:59:27.020 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:59:27.300 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:59:27.301 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:59:27.303 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:59:27.307 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:59:27.485 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:59:27.950 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:59:28.301 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:59:28.302 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:59:28.303 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:59:28.308 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:59:28.415 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:59:28.880 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:59:29.345 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:59:29.810 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:59:30.275 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:59:30.740 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:59:31.205 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:59:31.670 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:59:32.136 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:59:32.601 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 02:59:33.066 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 02:59:33.531 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 02:59:33.996 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 02:59:34.461 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 02:59:34.926 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 02:59:35.391 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 02:59:35.856 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 02:59:36.321 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 02:59:36.786 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 02:59:37.251 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 02:59:37.716 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 02:59:38.182 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 02:59:38.646 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 02:59:39.111 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 02:59:39.576 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 02:59:40.041 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 02:59:40.506 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 02:59:40.971 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 02:59:41.436 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 02:59:41.901 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 02:59:42.366 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 02:59:42.831 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 02:59:43.297 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 02:59:43.762 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 02:59:44.228 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 02:59:44.692 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 02:59:45.157 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 02:59:45.311 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:59:45.311 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:59:45.313 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:59:45.313 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:59:45.313 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:59:45.313 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:59:45.314 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:59:45.314 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:59:45.314 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:59:45.314 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:59:45.314 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:59:45.314 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:59:45.314 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 02:59:50.317 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 02:59:50.317 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 02:59:50.317 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:59:50.317 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:59:50.317 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:59:50.317 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:59:50.322 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 02:59:50.322 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:59:50.322 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:59:50.322 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 02:59:50.322 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 02:59:50.325 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 02:59:50.325 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 02:59:50.325 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:59:50.325 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:59:50.325 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 02:59:50.325 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 02:59:50.325 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 02:59:50.325 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 02:59:50.325 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:59:50.328 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 02:59:50.328 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 02:59:50.328 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:59:50.328 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:59:50.328 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 02:59:50.328 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 02:59:50.328 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 02:59:50.328 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 02:59:50.329 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:59:50.332 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 02:59:50.332 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 02:59:50.332 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:59:50.332 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 02:59:50.332 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 02:59:50.332 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 02:59:50.332 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 02:59:50.332 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 02:59:50.332 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:59:50.337 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 02:59:50.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 02:59:50.337 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 02:59:50.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 02:59:50.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 02:59:50.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 02:59:50.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 02:59:50.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 02:59:50.337 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 02:59:50.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:59:50.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 02:59:50.338 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:59:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:59:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:59:50.338 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 02:59:50.338 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 02:59:50.338 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 02:59:50.338 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 02:59:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:59:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:59:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:59:50.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 02:59:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:59:50.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:59:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:59:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:59:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:59:50.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:59:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:59:50.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:59:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:59:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:59:50.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:59:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:59:50.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:59:50.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:59:50.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 02:59:50.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:59:50.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:59:50.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:59:50.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:59:50.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:59:50.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:59:50.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:59:50.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 02:59:50.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 02:59:50.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:59:50.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 02:59:50.342 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 02:59:50.808 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 02:59:50.863 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 02:59:50.865 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 02:59:50.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 02:59:50.866 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 02:59:50.867 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 02:59:50.867 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 02:59:50.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 02:59:50.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 02:59:50.868 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 02:59:50.868 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 02:59:50.868 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 02:59:50.868 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 02:59:51.273 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 02:59:51.342 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:59:51.342 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:59:51.343 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:59:51.348 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:59:51.739 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 02:59:52.204 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 02:59:52.342 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:59:52.342 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:59:52.343 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:59:52.349 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:59:52.669 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 02:59:53.133 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 02:59:53.342 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:59:53.342 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:59:53.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:59:53.349 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:59:53.598 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 02:59:54.063 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 02:59:54.343 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:59:54.343 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:59:54.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:59:54.350 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:59:54.527 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 02:59:54.991 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 02:59:55.344 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 02:59:55.344 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 02:59:55.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 02:59:55.350 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 02:59:55.455 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 02:59:55.918 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 02:59:56.381 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 02:59:56.845 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 02:59:57.308 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 02:59:57.771 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 02:59:58.233 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 02:59:58.697 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 02:59:59.160 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 02:59:59.623 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:00:00.086 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:00:00.553 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:00:01.016 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:00:01.479 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:00:01.944 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:00:02.409 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:00:02.874 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:00:03.339 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:00:03.804 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:00:04.269 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:00:04.733 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:00:05.204 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:00:05.666 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:00:06.135 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:00:06.607 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:00:07.080 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:00:07.551 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:00:08.024 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:00:08.497 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:00:08.968 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 03:00:09.576 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 03:00:10.039 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 03:00:10.503 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 03:00:10.966 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 03:00:11.430 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 03:00:11.895 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 03:00:12.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:00:12.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:00:12.354 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:00:12.354 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:00:12.354 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:00:12.354 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:00:12.355 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:00:12.355 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:00:12.355 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:00:12.355 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:00:12.355 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:00:12.356 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:00:12.356 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:00:17.357 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:00:17.357 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:00:17.357 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:00:17.357 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:00:17.357 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:00:17.357 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:00:17.363 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:00:17.364 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:00:17.364 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:00:17.364 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:00:17.364 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:00:17.365 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:00:17.365 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:00:17.366 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:00:17.366 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:00:17.366 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:00:17.366 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:00:17.366 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:00:17.366 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:00:17.366 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:00:17.367 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:00:17.367 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:00:17.367 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:00:17.367 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:00:17.367 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:00:17.368 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:00:17.368 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:00:17.368 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:00:17.368 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:00:17.369 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:00:17.370 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:00:17.370 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:00:17.370 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:00:17.370 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:00:17.370 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:00:17.370 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:00:17.370 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:00:17.370 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:00:17.373 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:00:17.373 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:00:17.373 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:00:17.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:00:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:00:17.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:00:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:00:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:00:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:00:17.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:00:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:00:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:00:17.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:00:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:00:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:00:17.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:00:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:00:17.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:00:17.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:00:17.378 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:00:17.841 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:00:17.889 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:00:17.890 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:00:17.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:00:17.891 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:00:17.892 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:00:17.892 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:00:17.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:00:17.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:00:17.892 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:00:17.892 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:00:17.892 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:00:17.892 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:00:18.304 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:00:18.375 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:00:18.375 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:00:18.375 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:00:18.376 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:00:18.767 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:00:19.230 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:00:19.376 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:00:19.376 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:00:19.376 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:00:19.377 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:00:19.695 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:00:20.159 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:00:20.376 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:00:20.376 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:00:20.376 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:00:20.378 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:00:20.621 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:00:21.084 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:00:21.377 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:00:21.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:00:21.377 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:00:21.378 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:00:21.548 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:00:22.011 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:00:22.377 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:00:22.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:00:22.377 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:00:22.378 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:00:22.474 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:00:23.148 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:00:23.611 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:00:24.074 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:00:24.538 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:00:25.000 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:00:25.463 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:00:25.926 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:00:26.389 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:00:26.852 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:00:27.314 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:00:27.778 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:00:28.244 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:00:28.706 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:00:29.173 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:00:29.638 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:00:30.104 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:00:30.567 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:00:31.030 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:00:31.498 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:00:31.968 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:00:32.436 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:00:32.904 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:00:33.375 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:00:33.844 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:00:34.307 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:00:34.770 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:00:35.233 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:00:35.697 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:00:36.161 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 03:00:36.626 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 03:00:37.089 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 03:00:37.553 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 03:00:38.017 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 03:00:38.482 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 03:00:38.945 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 03:00:39.409 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 03:00:39.878 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 03:00:40.348 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 03:00:40.811 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 03:00:41.273 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 03:00:41.736 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 03:00:42.251 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 03:00:42.715 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 03:00:43.181 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 03:00:43.643 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 03:00:44.106 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 03:00:44.870 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 03:00:45.337 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 03:00:45.803 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 03:00:46.267 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 03:00:46.733 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 03:00:47.699 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 03:00:48.166 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 03:00:48.637 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 03:00:50.058 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 03:00:50.527 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 03:00:50.839 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:00:50.839 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:00:50.840 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:00:50.841 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:00:50.841 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:00:50.841 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:00:50.841 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:00:50.842 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:00:50.842 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:00:50.842 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:00:50.842 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:00:50.842 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:00:50.842 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:00:55.844 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:00:55.844 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:00:55.844 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:00:55.844 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:00:55.844 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:00:55.844 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:00:55.847 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:00:55.847 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:00:55.847 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:00:55.847 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:00:55.847 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:00:55.849 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:00:55.849 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:00:55.849 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:00:55.849 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:00:55.849 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:00:55.849 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:00:55.849 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:00:55.849 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:00:55.849 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:00:55.851 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:00:55.851 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:00:55.851 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:00:55.851 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:00:55.851 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:00:55.851 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:00:55.851 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:00:55.851 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:00:55.851 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:00:55.852 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:00:55.852 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:00:55.853 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:00:55.853 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:00:55.853 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:00:55.853 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:00:55.853 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:00:55.853 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:00:55.853 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:00:55.854 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:00:55.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:00:55.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:00:55.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:00:55.854 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:00:55.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:00:55.855 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:00:55.855 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:00:55.855 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:00:55.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:00:55.859 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:00:56.324 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:00:56.383 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:00:56.385 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:00:56.387 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:00:56.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:00:56.389 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:00:56.389 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:00:56.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:00:56.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:00:56.390 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:00:56.391 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:00:56.391 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:00:56.391 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:00:56.795 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:00:56.857 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:00:56.857 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:00:56.857 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:00:56.858 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:00:57.261 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:00:57.858 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:00:57.858 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:00:57.859 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:00:57.859 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:00:57.922 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:00:58.389 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:00:58.856 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:00:58.859 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:00:58.859 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:00:58.859 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:00:58.859 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:00:59.319 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:00:59.782 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:00:59.860 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:00:59.860 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:00:59.860 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:00:59.860 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:01:00.245 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:01:00.707 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:01:00.861 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:01:00.861 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:01:00.861 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:01:00.861 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:01:01.170 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:01:01.632 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:01:02.095 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:01:02.558 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:01:03.021 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:01:03.483 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:01:03.946 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:01:04.409 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:01:04.872 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:01:05.335 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:01:05.799 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:01:06.262 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:01:06.727 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:01:07.190 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:01:07.653 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:01:08.115 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:01:08.578 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:01:09.040 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:01:09.503 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:01:09.966 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:01:10.428 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:01:10.891 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:01:11.354 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:01:11.818 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:01:12.281 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:01:12.745 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:01:13.208 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:01:13.670 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:01:14.134 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:01:14.599 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 03:01:15.063 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 03:01:15.527 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 03:01:15.990 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 03:01:16.454 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 03:01:16.917 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 03:01:17.381 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 03:01:17.844 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 03:01:18.308 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 03:01:18.772 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 03:01:19.236 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 03:01:19.702 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 03:01:20.166 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 03:01:20.630 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 03:01:21.095 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 03:01:21.559 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 03:01:22.024 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 03:01:22.489 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 03:01:22.954 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 03:01:23.418 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 03:01:23.871 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:01:23.871 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:01:23.873 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:01:23.873 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:01:23.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:01:23.873 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:01:23.874 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:01:23.874 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:01:23.874 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:01:23.874 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:01:23.874 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:01:23.874 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:01:23.874 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:01:28.877 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:01:28.877 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:01:28.877 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:01:28.877 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:01:28.877 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:01:28.877 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:01:28.885 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:01:28.886 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:01:28.886 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:01:28.886 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:01:28.886 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:01:28.888 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:01:28.888 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:01:28.888 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:01:28.888 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:01:28.888 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:01:28.888 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:01:28.888 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:01:28.888 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:01:28.888 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:01:28.891 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:01:28.891 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:01:28.891 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:01:28.891 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:01:28.891 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:01:28.891 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:01:28.891 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:01:28.891 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:01:28.891 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:01:28.894 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:01:28.894 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:01:28.894 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:01:28.894 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:01:28.894 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:01:28.894 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:01:28.894 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:01:28.894 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:01:28.894 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:01:28.898 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:01:28.898 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:01:28.898 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:01:28.898 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:01:28.898 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:01:28.898 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:01:28.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:01:28.898 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:01:28.898 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:28.899 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:01:28.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:28.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:01:28.899 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:01:28.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:28.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:28.899 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:01:28.899 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:01:28.899 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:01:28.899 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:01:28.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:28.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:28.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:28.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:01:28.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:28.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:28.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:28.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:28.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:28.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:28.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:28.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:28.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:28.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:28.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:28.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:28.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:28.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:28.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:28.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:28.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:28.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:28.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:28.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:28.900 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:01:28.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:28.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:28.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:28.900 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:01:28.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:28.900 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:01:28.900 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:01:28.900 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:01:28.901 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:01:28.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:33.903 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:01:33.903 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:01:33.903 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:01:33.903 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:01:33.903 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:01:33.903 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:01:33.912 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:01:33.912 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:01:33.912 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:01:33.912 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:01:33.912 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:01:33.915 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:01:33.915 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:01:33.915 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:01:33.915 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:01:33.915 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:01:33.915 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:01:33.915 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:01:33.915 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:01:33.915 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:01:33.918 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:01:33.918 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:01:33.918 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:01:33.918 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:01:33.918 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:01:33.918 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:01:33.918 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:01:33.918 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:01:33.918 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:01:33.920 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:01:33.920 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:01:33.920 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:01:33.920 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:01:33.920 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:01:33.920 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:01:33.920 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:01:33.920 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:01:33.920 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:01:33.924 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:01:33.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:01:33.924 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:01:33.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:01:33.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:01:33.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:01:33.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:01:33.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:33.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:01:33.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:01:33.924 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:01:33.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:33.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:33.924 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:01:33.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:33.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:33.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:33.924 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:01:33.924 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:01:33.924 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:01:33.924 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:01:33.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:33.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:33.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:33.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:01:33.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:33.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:33.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:33.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:33.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:33.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:33.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:33.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:33.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:33.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:33.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:33.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:33.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:33.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:33.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:33.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:33.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:33.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:33.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:33.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:33.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:33.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:33.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:33.929 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:01:34.393 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:01:34.456 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:01:34.457 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:01:34.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:01:34.458 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:01:34.464 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:01:34.464 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:01:34.465 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:01:34.465 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:01:34.466 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:01:34.466 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:01:34.466 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:01:34.466 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:01:34.466 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:01:34.466 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:01:34.466 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:01:39.468 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:01:39.468 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:01:39.468 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:01:39.468 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:01:39.468 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:01:39.468 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:01:39.474 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:01:39.475 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:01:39.475 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:01:39.475 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:01:39.475 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:01:39.477 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:01:39.477 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:01:39.477 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:01:39.477 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:01:39.477 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:01:39.477 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:01:39.477 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:01:39.477 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:01:39.477 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:01:39.479 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:01:39.479 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:01:39.479 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:01:39.479 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:01:39.479 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:01:39.479 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:01:39.479 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:01:39.479 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:01:39.479 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:01:39.480 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:01:39.480 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:01:39.481 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:01:39.481 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:01:39.481 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:01:39.481 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:01:39.481 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:01:39.481 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:01:39.481 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:01:39.483 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:01:39.483 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:01:39.483 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:01:39.483 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:01:39.483 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:01:39.483 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:01:39.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:01:39.483 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:01:39.483 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:01:39.483 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:01:39.483 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:39.483 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:39.483 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:01:39.484 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:01:39.484 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:01:39.484 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:39.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:39.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:39.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:39.489 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:01:39.953 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:01:40.005 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:01:40.007 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:01:40.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:01:40.007 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:01:40.013 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:01:40.013 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:01:40.013 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:01:40.013 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:01:40.014 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:01:40.014 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:01:40.015 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:01:40.015 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:01:40.015 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:01:40.015 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:01:40.015 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:01:45.019 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:01:45.019 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:01:45.019 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:01:45.019 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:01:45.019 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:01:45.019 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:01:45.026 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:01:45.026 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:01:45.026 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:01:45.027 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:01:45.027 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:01:45.029 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:01:45.029 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:01:45.029 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:01:45.029 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:01:45.029 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:01:45.029 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:01:45.029 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:01:45.029 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:01:45.030 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:01:45.032 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:01:45.032 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:01:45.032 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:01:45.032 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:01:45.033 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:01:45.033 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:01:45.033 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:01:45.033 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:01:45.033 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:01:45.035 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:01:45.035 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:01:45.036 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:01:45.036 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:01:45.036 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:01:45.036 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:01:45.036 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:01:45.036 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:01:45.036 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:01:45.040 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:01:45.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:01:45.041 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:01:45.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:01:45.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:01:45.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:01:45.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:01:45.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:01:45.041 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:01:45.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:45.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:45.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:01:45.041 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:01:45.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:45.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:45.041 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:01:45.041 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:01:45.041 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:01:45.042 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:45.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:45.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:45.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:45.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:45.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:45.046 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:01:45.513 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:01:45.598 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:01:45.600 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:01:45.601 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:01:45.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:01:45.626 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:01:45.626 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:01:45.627 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:01:45.627 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:01:45.628 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:01:45.628 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:01:45.628 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:01:45.628 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:01:45.628 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:01:45.628 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:01:45.628 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:01:50.631 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:01:50.631 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:01:50.631 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:01:50.631 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:01:50.631 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:01:50.631 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:01:50.636 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:01:50.636 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:01:50.636 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:01:50.636 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:01:50.636 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:01:50.639 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:01:50.639 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:01:50.639 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:01:50.639 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:01:50.639 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:01:50.639 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:01:50.640 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:01:50.640 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:01:50.640 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:01:50.642 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:01:50.642 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:01:50.642 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:01:50.643 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:01:50.643 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:01:50.643 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:01:50.643 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:01:50.643 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:01:50.643 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:01:50.645 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:01:50.646 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:01:50.646 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:01:50.646 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:01:50.646 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:01:50.646 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:01:50.646 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:01:50.646 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:01:50.646 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:01:50.650 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:01:50.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:01:50.650 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:01:50.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:01:50.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:01:50.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:01:50.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:01:50.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:01:50.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:50.651 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:01:50.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:50.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:01:50.651 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:01:50.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:50.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:50.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:50.651 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:01:50.651 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:01:50.651 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:01:50.651 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:01:50.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:01:50.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:01:50.656 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:01:51.123 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:01:51.182 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:01:51.184 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:01:51.185 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:01:51.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:01:51.188 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:01:51.188 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:01:51.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:01:51.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:01:51.191 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:01:51.191 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:01:51.191 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:01:51.191 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:01:51.589 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:01:51.657 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:01:51.657 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:01:51.658 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:01:51.662 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:01:52.056 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:01:52.521 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:01:52.657 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:01:52.658 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:01:52.659 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:01:52.663 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:01:52.988 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:01:53.454 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:01:53.658 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:01:53.658 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:01:53.660 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:01:53.664 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:01:53.920 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:01:54.387 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:01:54.659 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:01:54.659 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:01:54.661 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:01:54.665 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:01:54.853 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:01:55.319 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:01:55.659 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:01:55.660 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:01:55.662 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:01:55.665 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:01:55.786 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:01:56.252 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:01:56.718 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:01:57.184 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:01:57.651 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:01:58.116 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:01:58.582 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:01:59.049 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:01:59.220 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:01:59.220 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:01:59.222 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:01:59.222 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:01:59.222 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:01:59.222 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:01:59.224 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:01:59.224 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:01:59.224 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:01:59.224 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:01:59.224 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:01:59.224 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:01:59.224 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:01:59.224 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1876 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:01:59.225 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1876 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:01:59.225 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1876 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:01:59.225 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1876 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:01:59.225 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1876 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:01:59.225 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1876 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:02:04.226 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:02:04.226 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:02:04.226 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:02:04.226 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:02:04.227 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:02:04.227 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:02:04.234 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:02:04.235 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:02:04.235 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:02:04.235 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:02:04.235 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:02:04.237 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:02:04.237 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:02:04.238 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:02:04.238 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:02:04.238 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:02:04.238 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:02:04.238 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:02:04.238 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:02:04.238 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:04.241 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:02:04.241 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:02:04.241 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:02:04.241 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:02:04.241 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:02:04.241 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:02:04.241 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:02:04.241 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:02:04.241 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:04.244 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:02:04.244 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:02:04.244 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:02:04.244 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:02:04.245 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:02:04.245 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:02:04.245 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:02:04.245 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:02:04.245 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:04.249 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:02:04.249 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:02:04.249 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:02:04.249 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:02:04.249 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:02:04.249 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:02:04.249 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:02:04.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:02:04.249 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:04.249 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:02:04.249 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:02:04.249 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:04.249 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:04.249 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:04.249 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:04.250 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:04.250 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:04.250 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:02:04.250 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:02:04.250 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:02:04.250 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:02:04.250 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:04.250 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:04.250 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:04.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:02:04.250 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:04.250 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:04.250 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:04.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:04.250 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:04.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:04.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:04.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:04.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:04.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:04.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:04.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:04.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:04.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:04.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:04.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:04.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:04.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:04.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:04.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:04.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:04.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:04.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:04.254 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:02:04.719 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:02:04.777 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:02:04.778 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:02:04.779 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:02:04.781 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:02:04.781 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:02:04.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:02:04.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:02:04.782 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:02:04.782 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:02:04.782 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:02:04.782 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:02:04.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:02:05.208 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:02:05.255 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:05.255 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:05.255 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:05.256 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:05.673 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:02:06.138 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:02:06.255 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:06.255 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:06.255 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:06.257 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:06.603 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:02:07.066 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:02:07.256 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:07.309 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:07.309 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:07.309 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:07.531 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:02:07.997 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:02:08.309 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:08.310 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:08.310 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:08.310 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:08.463 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:02:08.929 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:02:09.310 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:09.310 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:09.310 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:09.310 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:09.395 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:02:09.863 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:02:10.330 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:02:10.797 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:02:11.263 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:02:11.730 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:02:12.196 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:02:12.663 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:02:12.828 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:02:12.828 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:02:12.831 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:12.831 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:12.831 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:12.832 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:12.833 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:02:12.834 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:02:12.834 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:02:12.834 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:02:12.834 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:02:12.834 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:02:12.834 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:02:12.834 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1875 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:02:12.834 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1875 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:02:12.834 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1875 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:02:12.834 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1875 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:02:12.834 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1875 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:02:12.834 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1875 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:02:17.836 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:02:17.836 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:02:17.836 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:02:17.836 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:02:17.836 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:02:17.836 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:02:17.843 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:02:17.843 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:02:17.844 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:02:17.844 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:02:17.844 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:02:17.846 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:02:17.846 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:02:17.846 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:02:17.846 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:02:17.846 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:02:17.846 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:02:17.846 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:02:17.846 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:02:17.847 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:17.849 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:02:17.849 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:02:17.850 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:02:17.850 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:02:17.850 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:02:17.850 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:02:17.850 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:02:17.850 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:02:17.850 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:17.853 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:02:17.853 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:02:17.853 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:02:17.853 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:02:17.853 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:02:17.853 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:02:17.853 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:02:17.853 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:02:17.853 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:17.858 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:02:17.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:02:17.858 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:02:17.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:02:17.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:02:17.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:02:17.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:02:17.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:02:17.859 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:02:17.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:17.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:17.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:02:17.859 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:17.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:17.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:17.859 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:02:17.859 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:02:17.859 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:02:17.859 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:02:17.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:17.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:02:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:17.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:17.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:17.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:17.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:17.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:17.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:17.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:17.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:17.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:17.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:17.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:17.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:17.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:17.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:17.864 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:02:18.330 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:02:18.390 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:02:18.391 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:02:18.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:02:18.392 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:02:18.395 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:02:18.395 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:02:18.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:02:18.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:02:18.395 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:02:18.395 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:02:18.395 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:02:18.395 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:02:18.797 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:02:18.865 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:18.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:18.871 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:18.871 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:19.263 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:02:19.730 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:02:19.866 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:19.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:19.872 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:19.872 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:20.197 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:02:20.663 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:02:20.867 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:20.872 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:20.872 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:20.872 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:21.129 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:02:21.595 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:02:21.868 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:21.873 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:21.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:21.873 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:22.062 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:02:22.528 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:02:22.869 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:22.874 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:22.874 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:22.874 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:22.994 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:02:23.461 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:02:23.927 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:02:24.393 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:02:24.859 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:02:25.327 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:02:25.793 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:02:26.260 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:02:26.425 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:02:26.425 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:02:26.427 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:26.428 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:26.428 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:26.428 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:26.429 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:02:26.430 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:02:26.430 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:02:26.430 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:02:26.430 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:02:26.430 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:02:26.430 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:02:26.430 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1874 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:02:26.430 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1874 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:02:26.430 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1874 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:02:26.430 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1874 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:02:26.430 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1874 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:02:31.431 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:02:31.431 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:02:31.431 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:02:31.431 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:02:31.431 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:02:31.432 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:02:31.438 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:02:31.439 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:02:31.439 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:02:31.439 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:02:31.439 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:02:31.441 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:02:31.442 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:02:31.442 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:02:31.442 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:02:31.442 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:02:31.442 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:02:31.442 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:02:31.442 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:02:31.442 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:31.445 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:02:31.445 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:02:31.445 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:02:31.445 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:02:31.445 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:02:31.445 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:02:31.445 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:02:31.445 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:02:31.445 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:31.448 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:02:31.448 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:02:31.448 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:02:31.448 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:02:31.449 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:02:31.449 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:02:31.449 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:02:31.449 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:02:31.449 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:31.453 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:02:31.454 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:02:31.454 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:02:31.454 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:02:31.454 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:02:31.454 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:02:31.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:02:31.454 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:02:31.454 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:31.454 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:02:31.454 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:31.454 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:02:31.454 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:31.454 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:31.454 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:31.454 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:02:31.454 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:02:31.454 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:02:31.454 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:31.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:31.456 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:31.456 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:31.456 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:31.456 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:31.459 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:02:31.926 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:02:31.987 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:02:31.988 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:02:31.989 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:02:31.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:02:31.991 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:02:31.992 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:02:31.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:02:31.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:02:31.992 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:02:31.992 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:02:31.992 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:02:31.992 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:02:32.392 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:02:32.460 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:32.460 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:32.460 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:32.461 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:32.858 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:02:33.326 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:02:33.460 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:33.460 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:33.461 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:33.463 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:33.792 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:02:34.258 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:02:34.461 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:34.461 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:34.461 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:34.464 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:34.724 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:02:35.190 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:02:35.462 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:35.462 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:35.462 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:35.464 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:35.656 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:02:36.121 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:02:36.463 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:36.463 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:36.463 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:36.465 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:36.669 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:02:37.135 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:02:37.602 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:02:38.068 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:02:38.535 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:02:39.001 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:02:39.468 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:02:39.934 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:02:40.044 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:02:40.044 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:02:40.047 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:40.047 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:40.047 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:40.047 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:40.049 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:02:40.049 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:02:40.049 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:02:40.049 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:02:40.049 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:02:40.049 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:02:40.049 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:02:40.049 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1863 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:02:40.050 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1863 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:02:40.050 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1863 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:02:40.050 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1863 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:02:40.050 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1863 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:02:40.050 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1863 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:02:45.051 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:02:45.051 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:02:45.052 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:02:45.052 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:02:45.052 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:02:45.052 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:02:45.058 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:02:45.059 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:02:45.059 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:02:45.059 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:02:45.059 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:02:45.061 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:02:45.061 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:02:45.062 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:02:45.062 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:02:45.062 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:02:45.062 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:02:45.062 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:02:45.062 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:02:45.062 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:45.065 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:02:45.065 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:02:45.065 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:02:45.065 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:02:45.065 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:02:45.065 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:02:45.065 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:02:45.065 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:02:45.066 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:45.068 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:02:45.068 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:02:45.068 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:02:45.068 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:02:45.068 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:02:45.068 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:02:45.068 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:02:45.068 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:02:45.069 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:45.073 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:02:45.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:02:45.073 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:02:45.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:02:45.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:02:45.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:02:45.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:02:45.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:02:45.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:45.074 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:02:45.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:45.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:02:45.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:45.074 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:45.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:45.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:45.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:45.074 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:02:45.074 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:02:45.074 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:02:45.074 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:02:45.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:45.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:45.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:45.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:02:45.075 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:45.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:45.075 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:45.075 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:45.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:45.075 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:45.075 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:45.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:45.075 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:45.075 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:45.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:45.075 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:45.075 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:45.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:45.075 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:45.075 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:45.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:45.075 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:45.075 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:45.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:45.075 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:45.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:45.075 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:45.079 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:02:45.546 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:02:45.610 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:02:45.612 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:02:45.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:02:45.613 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:02:45.617 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:02:45.617 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:02:45.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:02:45.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:02:45.617 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:02:45.618 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:02:45.618 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:02:45.618 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:02:46.012 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:02:46.081 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:46.082 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:46.083 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:46.091 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:46.478 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:02:46.944 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:02:47.083 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:47.083 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:47.084 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:47.092 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:47.409 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:02:47.875 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:02:48.084 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:48.084 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:48.084 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:48.093 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:48.341 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:02:48.807 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:02:49.085 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:49.085 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:49.085 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:49.093 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:49.272 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:02:49.737 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:02:50.085 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:50.201 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:02:50.271 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:50.272 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:50.272 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:50.738 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:02:51.205 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:02:51.672 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:02:52.139 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:02:52.605 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:02:53.072 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:02:53.539 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:02:53.656 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:02:53.656 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:02:53.659 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:53.659 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:53.659 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:53.659 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:53.660 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:02:53.661 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:02:53.661 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:02:53.661 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:02:53.661 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:02:53.661 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:02:53.661 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:02:53.661 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1865 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:02:53.661 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1865 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:02:53.661 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1865 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:02:53.661 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1865 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:02:53.661 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1865 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:02:53.661 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1865 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:02:58.664 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:02:58.664 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:02:58.664 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:02:58.664 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:02:58.664 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:02:58.664 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:02:58.671 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:02:58.672 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:02:58.672 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:02:58.672 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:02:58.672 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:02:58.675 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:02:58.675 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:02:58.675 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:02:58.675 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:02:58.675 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:02:58.676 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:02:58.676 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:02:58.676 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:02:58.676 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:58.679 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:02:58.679 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:02:58.679 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:02:58.679 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:02:58.679 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:02:58.680 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:02:58.680 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:02:58.680 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:02:58.680 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:58.683 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:02:58.683 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:02:58.684 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:02:58.684 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:02:58.684 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:02:58.684 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:02:58.684 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:02:58.684 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:02:58.684 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:02:58.689 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:02:58.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:02:58.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:02:58.690 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:02:58.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:02:58.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:02:58.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:02:58.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:02:58.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:58.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:58.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:02:58.690 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:02:58.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:58.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:58.690 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:58.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:58.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:58.690 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:02:58.690 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:02:58.690 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:02:58.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:58.690 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:02:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:58.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:02:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:58.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:58.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:58.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:02:58.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:58.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:58.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:02:58.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:58.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:58.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:02:58.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:58.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:02:58.695 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:02:59.162 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:02:59.229 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:02:59.230 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:02:59.231 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:02:59.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:02:59.233 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:02:59.233 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:02:59.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:02:59.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:02:59.234 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:02:59.234 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:02:59.234 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:02:59.234 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:02:59.629 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:02:59.697 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:02:59.697 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:02:59.698 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:02:59.707 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:03:00.096 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:03:00.563 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:03:00.698 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:03:00.698 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:03:00.699 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:03:00.708 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:03:01.030 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:03:01.497 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:03:01.699 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:03:01.699 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:03:01.700 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:03:01.709 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:03:01.964 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:03:02.431 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:03:02.700 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:03:02.700 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:03:02.701 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:03:02.709 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:03:02.898 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:03:03.364 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:03:03.700 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:03:03.700 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:03:03.702 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:03:03.709 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:03:03.831 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:03:04.298 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:03:04.765 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:03:05.232 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:03:05.698 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:03:06.165 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:03:06.632 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:03:07.099 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:03:07.566 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:03:08.033 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:03:08.500 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:03:08.967 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:03:09.433 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:03:09.900 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:03:10.367 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:03:10.834 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:03:11.301 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:03:11.768 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:03:12.234 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:03:12.701 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:03:13.168 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:03:13.636 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:03:14.102 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:03:14.569 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:03:15.038 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:03:15.269 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:03:15.269 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:03:15.269 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:03:15.269 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:03:15.270 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:03:15.270 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:03:15.270 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:03:15.270 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:03:15.270 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:03:15.270 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:03:15.271 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3623 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:03:15.271 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3623 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:03:15.271 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3623 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:03:15.271 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3623 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:03:15.271 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3623 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:03:15.271 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3623 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:03:15.271 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3623 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:03:15.280 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:03:15.280 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:03:15.280 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:03:20.274 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:03:20.274 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:03:20.274 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:03:20.274 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:03:20.274 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:03:20.274 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:03:20.281 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:03:20.281 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:03:20.281 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:03:20.282 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:03:20.282 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:03:20.284 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:03:20.284 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:03:20.284 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:03:20.284 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:03:20.284 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:03:20.284 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:03:20.284 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:03:20.284 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:03:20.285 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:03:20.287 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:03:20.287 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:03:20.287 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:03:20.287 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:03:20.288 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:03:20.288 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:03:20.288 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:03:20.288 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:03:20.288 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:03:20.290 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:03:20.290 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:03:20.290 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:03:20.290 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:03:20.290 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:03:20.290 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:03:20.290 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:03:20.290 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:03:20.290 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:03:20.301 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:03:20.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:03:20.301 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:03:20.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:03:20.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:03:20.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:03:20.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:03:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:03:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:03:20.302 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:03:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:03:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:03:20.302 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:03:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:03:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:03:20.302 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:03:20.302 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:03:20.302 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:03:20.302 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:03:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:03:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:03:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:03:20.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:03:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:03:20.303 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:03:20.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:03:20.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:03:20.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:03:20.303 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:03:20.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:03:20.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:03:20.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:03:20.303 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:03:20.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:03:20.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:03:20.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:03:20.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:03:20.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:03:20.303 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:03:20.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:03:20.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:03:20.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:03:20.303 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:03:20.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:03:20.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:03:20.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:03:20.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:03:20.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:03:20.307 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:03:20.773 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:03:20.833 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:03:20.834 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:03:20.835 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:03:20.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:03:20.851 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:03:20.851 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:03:20.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:03:20.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:03:20.852 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:03:20.852 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:03:20.852 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:03:20.852 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:03:21.240 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:03:21.307 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:03:21.308 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:03:21.308 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:03:21.309 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:03:21.708 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:03:22.175 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:03:22.308 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:03:22.308 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:03:22.308 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:03:22.309 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:03:22.642 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:03:23.109 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:03:23.308 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:03:23.308 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:03:23.308 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:03:23.310 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:03:23.575 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:03:24.041 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:03:24.309 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:03:24.309 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:03:24.310 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:03:24.311 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:03:24.508 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:03:24.976 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:03:25.310 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:03:25.310 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:03:25.310 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:03:25.312 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:03:25.442 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:03:25.910 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:03:26.376 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:03:26.843 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:03:27.311 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:03:27.780 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:03:28.247 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:03:28.713 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:03:28.868 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:03:28.868 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:03:28.877 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:03:28.877 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:03:28.877 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:03:28.877 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:03:28.878 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:03:28.879 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:03:28.879 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:03:28.879 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:03:28.879 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:03:28.879 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:03:28.879 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:03:28.879 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1874 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:03:28.879 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1874 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:03:28.879 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1874 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:03:28.879 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1874 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:03:28.879 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1874 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:03:28.879 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1874 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:03:33.878 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:03:33.878 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:03:33.878 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:03:33.878 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:03:33.878 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:03:33.878 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:03:33.882 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:03:33.882 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:03:33.882 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:03:33.882 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:03:33.882 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:03:33.883 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:03:33.883 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:03:33.883 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:03:33.883 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:03:33.883 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:03:33.884 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:03:33.884 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:03:33.884 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:03:33.884 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:03:33.886 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:03:33.886 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:03:33.886 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:03:33.886 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:03:33.886 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:03:33.886 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:03:33.886 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:03:33.886 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:03:33.886 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:03:33.888 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:03:33.888 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:03:33.888 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:03:33.888 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:03:33.888 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:03:33.888 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:03:33.888 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:03:33.888 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:03:33.888 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:03:33.890 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:03:33.890 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:03:33.890 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:03:33.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:03:33.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:03:33.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:03:33.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:03:33.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:03:33.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:03:33.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:03:33.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:03:33.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:03:33.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:03:33.895 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:03:34.359 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:03:34.410 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:03:34.411 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:03:34.412 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:03:34.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:03:34.417 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:03:34.417 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:03:34.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:03:34.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:03:34.418 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:03:34.418 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:03:34.418 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:03:34.418 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:03:34.839 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:03:34.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:03:34.893 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:03:34.893 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:03:34.893 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:03:35.302 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:03:35.768 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:03:35.894 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:03:35.895 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:03:35.895 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:03:35.895 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:03:36.232 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:03:36.695 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:03:36.895 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:03:36.895 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:03:36.895 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:03:36.895 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:03:37.159 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:03:37.623 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:03:37.896 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:03:37.896 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:03:37.896 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:03:37.896 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:03:38.087 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:03:38.551 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:03:38.896 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:03:38.896 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:03:38.896 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:03:38.896 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:03:39.014 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:03:39.478 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:03:39.941 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:03:40.405 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:03:40.870 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:03:41.336 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:03:41.802 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:03:42.268 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:03:42.734 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:03:43.201 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:03:43.669 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:03:44.132 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:03:44.596 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:03:45.060 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:03:45.524 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:03:45.988 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:03:46.451 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:03:46.914 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:03:47.378 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:03:47.842 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:03:48.306 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:03:48.769 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:03:49.232 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:03:49.694 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:03:50.157 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:03:50.452 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:03:50.452 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:03:50.457 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:03:50.457 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:03:50.457 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:03:50.457 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:03:50.457 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:03:50.457 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:03:50.457 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:03:50.457 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:03:50.458 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:03:50.458 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:03:50.458 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:03:50.458 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3638 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:03:50.458 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3638 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:03:50.458 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3638 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:03:50.458 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3638 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:03:50.458 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3638 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:03:50.458 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3638 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:03:50.458 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3638 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:03:55.460 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:03:55.460 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:03:55.460 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:03:55.460 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:03:55.460 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:03:55.460 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:03:55.463 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:03:55.463 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:03:55.463 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:03:55.463 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:03:55.463 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:03:55.464 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:03:55.464 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:03:55.464 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:03:55.465 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:03:55.465 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:03:55.465 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:03:55.465 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:03:55.465 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:03:55.465 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:03:55.466 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:03:55.466 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:03:55.466 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:03:55.466 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:03:55.466 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:03:55.466 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:03:55.466 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:03:55.466 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:03:55.466 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:03:55.467 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:03:55.467 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:03:55.467 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:03:55.467 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:03:55.468 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:03:55.468 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:03:55.468 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:03:55.468 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:03:55.468 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:03:55.470 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:03:55.470 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:03:55.470 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:03:55.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:03:55.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:03:55.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:03:55.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:03:55.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:03:55.475 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:03:55.939 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:03:55.986 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:03:55.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:03:55.987 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:03:55.987 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:03:55.993 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:03:55.993 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:03:55.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:03:55.997 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:03:55.998 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:03:55.998 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:03:55.998 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:03:55.998 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:03:55.998 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:03:55.998 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:03:55.998 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:03:55.998 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:03:55.998 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:03:55.999 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:04:01.000 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:04:01.033 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:04:01.033 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:04:01.033 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:04:01.033 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:04:01.033 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:04:01.033 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:04:01.033 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:04:01.033 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:04:01.033 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:04:01.033 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:04:01.033 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:04:01.033 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:04:01.033 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:04:01.033 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:04:01.033 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:04:01.033 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:04:01.034 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:04:01.034 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:04:01.034 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:04:01.034 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:04:01.034 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:04:01.034 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:04:01.034 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:04:01.034 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:04:01.034 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:01.034 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:01.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:01.039 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:04:01.503 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:04:01.966 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:04:02.035 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:04:02.035 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:04:02.035 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:04:02.035 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:04:02.428 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:04:02.891 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:04:03.035 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:04:03.035 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:04:03.035 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:04:03.035 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:04:03.354 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:04:03.817 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:04:04.036 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:04:04.036 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:04:04.036 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:04:04.036 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:04:04.279 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:04:04.381 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:04:04.381 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:04:04.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:04:04.382 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:04:04.388 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:04:04.388 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:04:04.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:04:04.406 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:04:04.406 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:04:04.406 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:04:04.406 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:04:04.407 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:04:04.407 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:04:04.407 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:04:04.407 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:04:04.407 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:04:04.407 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:04:04.407 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:04:04.407 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=744 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:04:04.407 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=744 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:04:04.407 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=744 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:04:04.407 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=744 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:04:04.407 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=744 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:04:04.407 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=744 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:04:09.408 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:04:09.408 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:04:09.408 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:04:09.408 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:04:09.408 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:04:09.408 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:04:09.411 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:04:09.412 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:04:09.412 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:04:09.412 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:04:09.412 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:04:09.413 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:04:09.413 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:04:09.413 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:04:09.413 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:04:09.413 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:04:09.414 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:04:09.414 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:04:09.414 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:04:09.414 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:04:09.415 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:04:09.415 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:04:09.415 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:04:09.415 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:04:09.415 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:04:09.415 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:04:09.415 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:04:09.415 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:04:09.415 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:04:09.416 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:04:09.416 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:04:09.416 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:04:09.416 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:04:09.416 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:04:09.416 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:04:09.416 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:04:09.416 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:04:09.416 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:04:09.418 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:04:09.418 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:04:09.418 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:09.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:09.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:09.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:09.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:09.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:09.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:09.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:09.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:09.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:09.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:09.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:09.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:09.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:09.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:09.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:09.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:09.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:09.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:09.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:09.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:09.423 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:04:09.885 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:04:09.930 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:04:09.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:04:09.931 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:04:09.931 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:04:09.936 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:04:09.937 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:04:09.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:04:09.942 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:04:09.942 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:04:09.942 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:04:09.942 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:04:09.943 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:04:09.943 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:04:09.943 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:04:09.943 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:04:09.943 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:04:09.943 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:04:09.943 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:04:14.944 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:04:14.944 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:04:14.944 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:04:14.944 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:04:14.944 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:04:14.944 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:04:14.947 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:04:14.947 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:04:14.947 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:04:14.948 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:04:14.948 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:04:14.948 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:04:14.948 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:04:14.949 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:04:14.949 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:04:14.949 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:04:14.949 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:04:14.949 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:04:14.949 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:04:14.949 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:04:14.950 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:04:14.950 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:04:14.950 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:04:14.950 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:04:14.950 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:04:14.950 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:04:14.950 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:04:14.950 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:04:14.950 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:04:14.951 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:04:14.951 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:04:14.951 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:04:14.951 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:04:14.951 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:04:14.951 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:04:14.951 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:04:14.951 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:04:14.951 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:04:14.953 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:04:14.953 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:04:14.953 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:14.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:14.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:14.954 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:14.954 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:14.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:14.954 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:14.954 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:14.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:14.954 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:14.954 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:14.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:14.954 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:14.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:14.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:14.958 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:04:15.420 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:04:15.464 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:04:15.464 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:04:15.464 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:04:15.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:04:15.469 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:04:15.469 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:04:15.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:04:15.476 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:04:15.476 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:04:15.476 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:04:15.476 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:04:15.476 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:04:15.476 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:04:15.476 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:04:15.476 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:04:15.476 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:04:15.477 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:04:15.477 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:04:20.479 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:04:20.479 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:04:20.479 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:04:20.479 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:04:20.479 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:04:20.479 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:04:20.482 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:04:20.482 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:04:20.482 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:04:20.482 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:04:20.482 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:04:20.483 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:04:20.483 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:04:20.484 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:04:20.484 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:04:20.484 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:04:20.484 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:04:20.484 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:04:20.484 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:04:20.484 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:04:20.485 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:04:20.485 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:04:20.485 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:04:20.485 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:04:20.485 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:04:20.485 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:04:20.485 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:04:20.485 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:04:20.485 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:04:20.486 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:04:20.486 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:04:20.486 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:04:20.486 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:04:20.486 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:04:20.486 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:04:20.486 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:04:20.486 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:04:20.486 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:04:20.488 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:04:20.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:04:20.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:04:20.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:04:20.488 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:04:20.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:04:20.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:04:20.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:04:20.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:20.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:04:20.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:20.488 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:04:20.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:20.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:20.488 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:04:20.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:20.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:20.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:20.488 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:04:20.488 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:04:20.488 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:04:20.488 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:20.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:20.493 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:04:20.961 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:04:21.000 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:04:21.000 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:04:21.001 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:04:21.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:04:21.428 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:04:21.491 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:04:21.492 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:04:21.492 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:04:21.492 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:04:21.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:04:21.776 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:04:21.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:04:21.824 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:04:21.824 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:04:21.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:04:21.828 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:04:21.828 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:04:21.828 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:04:21.828 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:04:21.829 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:04:21.829 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:04:21.829 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:04:21.829 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:04:21.829 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:04:21.829 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:04:21.829 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:04:21.829 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=293 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:04:21.830 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=293 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:04:21.830 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=293 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:04:21.830 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:04:21.830 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:04:21.830 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:04:26.831 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:04:26.831 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:04:26.831 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:04:26.831 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:04:26.831 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:04:26.831 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:04:26.835 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:04:26.835 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:04:26.835 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:04:26.835 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:04:26.835 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:04:26.836 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:04:26.836 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:04:26.836 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:04:26.836 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:04:26.836 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:04:26.836 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:04:26.836 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:04:26.836 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:04:26.837 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:04:26.837 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:04:26.837 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:04:26.837 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:04:26.837 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:04:26.837 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:04:26.837 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:04:26.837 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:04:26.837 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:04:26.837 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:04:26.838 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:04:26.838 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:04:26.838 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:04:26.838 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:04:26.838 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:04:26.838 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:04:26.839 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:04:26.839 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:04:26.839 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:04:26.840 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:04:26.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:04:26.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:04:26.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:04:26.840 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:04:26.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:04:26.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:04:26.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:26.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:04:26.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:04:26.840 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:04:26.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:26.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:26.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:26.840 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:04:26.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:26.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:26.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:26.840 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:04:26.840 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:04:26.841 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:04:26.841 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:26.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:26.845 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:04:27.308 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:04:27.351 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:04:27.351 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:04:27.352 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:04:27.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:04:27.358 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:04:27.358 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:04:27.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:04:27.367 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:04:27.367 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:04:27.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:04:27.371 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:04:27.371 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:04:27.371 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:04:27.371 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:04:27.372 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:04:27.372 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:04:27.372 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:04:27.372 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:04:27.372 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:04:27.372 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:04:27.372 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:04:32.375 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:04:32.375 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:04:32.375 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:04:32.375 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:04:32.375 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:04:32.375 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:04:32.379 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:04:32.379 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:04:32.379 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:04:32.379 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:04:32.379 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:04:32.380 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:04:32.380 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:04:32.380 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:04:32.380 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:04:32.380 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:04:32.380 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:04:32.380 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:04:32.380 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:04:32.380 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:04:32.381 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:04:32.381 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:04:32.381 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:04:32.381 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:04:32.381 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:04:32.381 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:04:32.381 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:04:32.381 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:04:32.381 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:04:32.382 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:04:32.382 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:04:32.382 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:04:32.382 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:04:32.382 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:04:32.382 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:04:32.382 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:04:32.382 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:04:32.383 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:04:32.384 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:04:32.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:04:32.384 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:04:32.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:04:32.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:04:32.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:04:32.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:04:32.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:04:32.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:32.384 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:04:32.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:32.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:04:32.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:32.384 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:04:32.385 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:04:32.385 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:04:32.385 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:04:32.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:04:32.389 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:04:32.853 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:04:32.897 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:04:32.897 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:04:32.897 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:04:32.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:04:32.899 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:04:32.899 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:04:32.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:04:32.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:04:32.899 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:04:32.899 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:04:32.899 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:04:32.899 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:04:33.316 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:04:33.387 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:04:33.387 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:04:33.387 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:04:33.387 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:04:33.780 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:04:34.246 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:04:34.387 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:04:34.387 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:04:34.387 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:04:34.387 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:04:34.708 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:04:35.171 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:04:35.388 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:04:35.388 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:04:35.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:04:35.388 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:04:35.638 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:04:36.106 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:04:36.388 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:04:36.388 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:04:36.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:04:36.388 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:04:36.569 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:04:37.032 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:04:37.388 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:04:37.388 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:04:37.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:04:37.388 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:04:37.494 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:04:37.958 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:04:38.421 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:04:38.886 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:04:39.349 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:04:39.812 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:04:40.274 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:04:40.737 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:04:41.199 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:04:41.662 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:04:42.124 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:04:42.588 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:04:43.052 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:04:43.515 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:04:43.978 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:04:44.441 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:04:44.905 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:04:45.370 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:04:45.837 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:04:46.301 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:04:46.764 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:04:47.230 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:04:47.692 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:04:48.155 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:04:48.618 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:04:49.081 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:04:49.545 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:04:50.008 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:04:50.470 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:04:50.934 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 03:04:51.398 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 03:04:51.861 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 03:04:52.324 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 03:04:52.787 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 03:04:53.250 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 03:04:53.715 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 03:04:54.179 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 03:04:54.642 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 03:04:55.106 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 03:04:55.569 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 03:04:56.034 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 03:04:56.498 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 03:04:56.961 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 03:04:57.428 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 03:04:57.895 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 03:04:58.359 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 03:04:58.824 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 03:04:59.288 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 03:04:59.752 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 03:05:00.220 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 03:05:00.684 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 03:05:01.151 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 03:05:01.621 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 03:05:02.179 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 03:05:02.650 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 03:05:03.122 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 03:05:03.594 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 03:05:04.065 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 03:05:04.536 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 03:05:05.009 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 03:05:05.477 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 03:05:05.944 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 03:05:06.403 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:05:06.403 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:05:06.407 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:06.407 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:06.407 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:06.407 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:06.408 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 03:05:06.412 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:05:06.412 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:05:06.412 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:05:06.412 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:05:06.413 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:05:06.413 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:05:06.413 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:05:06.413 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7447 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:05:06.413 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7447 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:05:06.413 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7447 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:05:06.413 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7447 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:05:06.413 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7447 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:05:06.413 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7447 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:05:06.413 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7448 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:05:06.413 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7448 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:05:06.413 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7448 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:05:06.413 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7448 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:05:06.413 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7448 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:05:06.413 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7448 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:05:06.413 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7448 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:05:06.413 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7448 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:05:06.413 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7449 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:05:06.413 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7449 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:05:06.413 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7449 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:05:06.413 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7449 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:05:06.413 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7449 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:05:06.413 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7449 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:05:06.413 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7449 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:05:06.413 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7449 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:05:11.414 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:05:11.414 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:05:11.414 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:05:11.414 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:05:11.414 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:05:11.414 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:05:11.419 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:05:11.420 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:05:11.420 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:05:11.420 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:05:11.420 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:05:11.422 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:05:11.422 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:05:11.422 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:05:11.422 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:05:11.422 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:05:11.422 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:05:11.422 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:05:11.423 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:05:11.423 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:11.425 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:05:11.425 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:05:11.425 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:05:11.425 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:05:11.425 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:05:11.425 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:05:11.425 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:05:11.425 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:05:11.425 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:11.427 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:05:11.427 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:05:11.427 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:05:11.427 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:05:11.427 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:05:11.427 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:05:11.427 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:05:11.427 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:05:11.427 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:11.433 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:05:11.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:05:11.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:05:11.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:05:11.433 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:05:11.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:05:11.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:05:11.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:11.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:05:11.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:05:11.433 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:05:11.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:11.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:11.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:11.433 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:11.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:11.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:11.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:11.433 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:05:11.433 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:05:11.433 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:05:11.434 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:05:11.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:11.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:11.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:11.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:05:11.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:11.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:11.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:11.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:11.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:11.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:11.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:11.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:11.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:11.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:11.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:11.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:11.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:11.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:11.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:11.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:11.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:11.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:11.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:11.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:11.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:11.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:11.438 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:05:11.906 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:05:11.957 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:05:11.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:05:11.958 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:05:11.959 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:05:12.370 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:05:12.436 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:12.436 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:12.436 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:12.437 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:12.834 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:05:13.302 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:05:13.437 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:13.437 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:13.437 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:13.437 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:13.766 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:05:14.233 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:05:14.439 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:14.439 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:14.439 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:14.439 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:14.699 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:05:14.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:05:14.986 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:14.986 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:14.986 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:14.986 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:14.988 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:05:14.988 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:05:14.988 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:05:14.989 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:05:14.989 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:05:14.989 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:05:14.989 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:05:14.989 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=778 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:05:14.989 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=778 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:05:19.988 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:05:19.988 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:05:19.988 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:05:19.989 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:05:19.989 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:05:19.989 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:05:19.992 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:05:19.992 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:05:19.992 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:05:19.992 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:05:19.992 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:05:19.994 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:05:19.994 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:05:19.994 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:05:19.994 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:05:19.994 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:05:19.994 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:05:19.994 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:05:19.994 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:05:19.994 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:19.996 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:05:19.996 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:05:19.996 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:05:19.996 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:05:19.996 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:05:19.996 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:05:19.996 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:05:19.996 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:05:19.996 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:19.998 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:05:19.998 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:05:19.998 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:05:19.998 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:05:19.998 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:05:19.998 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:05:19.999 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:05:19.999 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:05:19.999 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:05:20.002 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:05:20.002 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:05:20.002 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:20.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:20.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:20.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:20.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:20.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:20.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:20.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:20.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:20.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:20.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:20.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:20.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:20.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:20.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:20.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:20.007 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:05:20.470 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:05:20.513 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:05:20.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:05:20.519 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:05:20.520 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:05:20.934 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:05:21.005 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:21.006 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:21.006 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:21.006 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:21.400 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:05:21.865 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:05:22.006 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:22.006 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:22.006 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:22.006 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:22.328 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:05:22.790 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:05:23.007 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:23.007 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:23.007 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:23.007 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:23.253 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:05:23.716 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:05:24.007 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:24.007 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:24.007 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:24.007 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:24.180 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:05:24.644 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:05:25.008 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:25.008 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:25.008 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:25.008 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:25.108 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:05:25.571 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:05:26.034 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:05:26.497 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:05:26.607 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:26.607 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:26.607 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:26.607 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:26.608 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:05:26.608 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:05:26.608 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:05:26.608 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:05:26.608 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:05:26.608 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:05:26.608 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:05:31.610 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:05:31.610 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:05:31.610 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:05:31.610 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:05:31.610 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:05:31.610 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:05:31.614 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:05:31.614 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:05:31.614 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:05:31.614 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:05:31.614 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:05:31.615 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:05:31.615 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:05:31.615 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:05:31.615 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:05:31.615 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:05:31.615 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:05:31.616 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:05:31.616 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:05:31.616 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:31.616 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:05:31.617 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:05:31.617 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:05:31.617 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:05:31.617 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:05:31.617 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:05:31.617 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:05:31.617 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:05:31.617 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:31.618 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:05:31.618 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:05:31.618 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:05:31.618 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:05:31.618 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:05:31.618 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:05:31.618 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:05:31.618 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:05:31.618 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:05:31.620 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:05:31.620 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:05:31.620 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:31.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:31.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:31.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:31.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:31.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:31.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:31.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:31.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:31.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:31.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:31.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:31.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:31.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:31.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:31.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:31.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:31.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:31.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:31.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:31.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:31.625 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:05:32.088 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:05:32.134 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:05:32.135 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:05:32.135 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:05:32.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:05:32.550 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:05:32.622 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:32.622 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:32.623 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:32.623 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:33.013 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:05:33.475 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:05:33.622 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:33.622 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:33.623 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:33.623 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:33.939 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:05:34.405 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:05:34.623 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:34.624 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:34.624 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:34.624 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:34.868 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:05:35.332 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:05:35.625 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:35.625 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:35.625 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:35.625 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:35.795 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:05:36.259 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:05:36.626 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:36.626 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:36.627 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:36.627 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:36.723 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:05:37.187 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:05:37.650 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:05:38.113 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:05:38.140 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:38.140 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:38.140 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:38.140 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:38.141 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:05:38.141 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:05:38.141 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:05:38.141 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:05:38.141 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:05:38.141 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:05:38.141 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:05:43.142 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:05:43.143 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:05:43.143 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:05:43.143 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:05:43.143 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:05:43.143 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:05:43.145 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:05:43.145 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:05:43.145 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:05:43.145 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:05:43.146 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:05:43.146 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:05:43.146 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:05:43.147 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:05:43.147 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:05:43.147 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:05:43.147 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:05:43.147 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:05:43.147 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:05:43.147 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:43.148 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:05:43.148 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:05:43.148 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:05:43.148 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:05:43.148 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:05:43.148 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:05:43.148 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:05:43.148 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:05:43.148 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:43.149 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:05:43.149 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:05:43.149 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:05:43.149 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:05:43.149 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:05:43.149 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:05:43.149 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:05:43.149 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:05:43.149 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:43.151 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:05:43.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:05:43.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:05:43.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:05:43.151 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:05:43.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:05:43.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:05:43.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:43.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:05:43.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:05:43.151 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:05:43.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:43.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:43.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:43.151 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:43.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:43.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:43.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:43.151 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:05:43.151 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:05:43.151 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:05:43.151 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:05:43.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:43.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:43.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:43.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:05:43.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:43.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:43.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:43.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:43.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:43.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:43.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:43.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:43.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:43.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:43.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:43.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:43.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:43.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:43.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:43.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:43.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:43.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:43.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:43.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:43.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:43.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:43.156 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:05:43.622 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:05:43.665 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:05:43.666 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:05:43.666 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:05:43.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:05:44.086 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:05:44.153 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:44.154 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:44.154 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:44.154 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:44.550 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:05:45.013 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:05:45.155 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:45.155 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:45.155 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:45.155 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:45.477 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:05:46.156 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:48.921 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:48.921 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:48.921 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:48.921 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:48.922 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:48.922 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:48.922 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:48.925 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:48.926 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:05:48.926 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:48.926 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:48.926 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:48.926 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:05:48.926 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:05:48.926 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:05:48.926 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:05:48.927 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:05:48.927 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:05:49.949 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:05:49.949 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:05:49.949 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:05:49.949 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:05:49.949 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:05:49.949 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:05:54.952 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:05:54.953 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:05:54.953 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:05:54.953 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:05:54.953 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:05:54.954 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:05:54.954 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:05:54.954 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:05:54.954 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:05:54.954 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:05:54.954 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:05:54.954 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:05:54.954 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:05:54.954 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:54.955 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:05:54.955 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:05:54.955 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:05:54.955 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:05:54.955 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:05:54.955 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:05:54.955 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:05:54.955 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:05:54.956 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:54.957 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:05:54.957 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:05:54.957 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:05:54.957 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:05:54.957 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:05:54.957 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:05:54.957 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:05:54.957 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:05:54.957 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:54.958 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:05:54.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:05:54.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:05:54.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:05:54.958 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:05:54.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:05:54.958 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:05:54.958 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:54.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:05:54.958 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:05:54.958 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:05:54.958 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:05:54.958 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:05:54.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:54.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:05:54.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:05:54.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:54.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:54.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:54.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:54.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:54.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:54.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:54.960 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:05:54.960 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:05:54.960 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:05:54.960 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:05:54.960 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:05:54.960 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:05:54.960 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:05:59.963 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:05:59.963 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:05:59.963 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:05:59.963 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:05:59.963 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:05:59.963 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:05:59.966 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:05:59.966 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:05:59.966 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:05:59.966 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:05:59.966 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:05:59.967 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:05:59.967 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:05:59.967 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:05:59.967 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:05:59.967 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:05:59.968 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:05:59.968 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:05:59.968 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:05:59.968 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:05:59.969 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:05:59.969 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:05:59.969 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:05:59.969 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:05:59.969 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:05:59.969 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:05:59.969 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:05:59.969 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:05:59.969 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:05:59.970 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:05:59.970 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:05:59.970 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:05:59.970 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:05:59.970 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:05:59.970 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:05:59.970 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:05:59.970 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:05:59.970 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:05:59.972 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:05:59.972 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:05:59.972 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:59.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:59.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:59.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:59.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:59.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:59.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:59.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:59.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:59.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:59.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:59.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:59.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:05:59.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:05:59.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:59.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:59.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:05:59.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:59.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:05:59.977 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:06:00.440 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:06:00.487 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:06:00.487 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:06:00.488 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:06:00.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:06:00.902 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:06:00.975 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:00.975 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:00.977 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:00.980 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:01.365 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:06:01.827 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:06:01.976 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:01.976 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:01.977 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:01.980 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:02.289 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:06:02.752 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:06:02.976 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:02.976 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:02.978 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:02.981 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:03.214 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:06:03.676 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:06:03.977 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:03.977 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:03.978 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:03.981 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:04.138 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:06:04.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:06:04.601 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:06:05.064 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:06:05.526 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:06:05.988 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:06:06.450 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:06:06.913 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:06:07.375 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:06:07.837 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:06:08.299 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:06:08.494 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:08.494 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:08.494 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:08.494 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:08.495 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:06:08.495 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:06:08.495 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:06:08.495 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:06:08.495 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:06:08.495 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:06:08.495 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:06:08.495 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1881 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:06:08.495 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1881 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:06:08.495 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1881 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:06:08.495 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1881 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:06:08.495 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1881 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:06:08.495 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1881 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:06:13.497 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:06:13.497 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:06:13.497 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:06:13.497 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:06:13.497 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:06:13.497 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:06:13.500 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:06:13.500 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:06:13.500 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:13.501 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:06:13.501 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:06:13.502 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:06:13.502 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:06:13.502 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:06:13.502 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:13.502 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:06:13.502 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:06:13.503 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:06:13.503 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:06:13.503 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:13.503 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:06:13.504 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:06:13.504 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:06:13.504 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:13.504 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:06:13.504 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:06:13.504 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:06:13.504 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:06:13.504 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:13.505 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:06:13.505 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:06:13.505 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:06:13.505 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:13.505 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:06:13.505 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:06:13.505 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:06:13.505 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:06:13.505 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:13.507 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:06:13.507 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:06:13.507 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:06:13.507 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:06:13.507 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:06:13.507 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:06:13.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:06:13.508 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:06:13.508 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:06:13.508 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:13.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:13.512 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:06:13.978 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:06:14.020 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:06:14.021 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:06:14.021 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:06:14.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:06:14.440 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:06:14.510 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:14.510 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:14.510 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:14.511 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:14.902 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:06:15.365 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:06:15.510 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:15.511 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:15.511 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:15.512 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:15.827 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:06:16.289 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:06:16.511 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:16.512 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:16.512 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:16.512 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:16.752 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:06:17.216 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:06:17.512 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:17.512 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:17.512 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:17.512 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:17.679 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:06:18.024 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:18.024 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:18.024 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:18.024 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:18.025 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:06:18.025 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:06:18.025 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:06:18.025 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:06:18.025 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:06:18.025 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:06:18.025 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:06:23.027 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:06:23.027 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:06:23.027 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:06:23.027 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:06:23.027 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:06:23.027 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:06:23.030 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:06:23.031 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:06:23.031 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:23.031 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:06:23.031 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:06:23.032 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:06:23.032 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:06:23.032 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:06:23.032 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:23.032 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:06:23.032 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:06:23.032 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:06:23.032 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:06:23.032 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:23.033 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:06:23.033 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:06:23.033 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:06:23.033 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:23.033 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:06:23.033 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:06:23.033 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:06:23.033 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:06:23.033 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:23.034 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:06:23.034 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:06:23.034 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:06:23.034 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:23.034 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:06:23.034 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:06:23.034 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:06:23.034 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:06:23.034 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:23.036 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:06:23.036 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:06:23.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:06:23.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:06:23.036 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:06:23.036 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:06:23.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:06:23.036 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:23.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:06:23.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:06:23.036 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:06:23.036 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:23.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:23.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:23.036 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:23.036 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:23.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:23.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:23.036 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:06:23.036 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:06:23.036 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:23.037 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:23.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:23.041 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:06:23.504 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:06:23.549 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:06:23.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:06:23.550 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:06:23.550 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:06:23.553 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:23.553 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:23.553 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:23.553 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:23.554 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:06:23.554 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:06:23.554 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:06:23.554 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:06:23.554 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:06:23.554 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:06:23.554 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:06:28.556 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:06:28.556 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:06:28.556 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:06:28.556 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:06:28.556 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:06:28.556 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:06:28.559 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:06:28.560 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:06:28.560 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:28.560 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:06:28.560 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:06:28.561 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:06:28.561 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:06:28.561 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:06:28.561 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:28.561 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:06:28.561 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:06:28.561 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:06:28.561 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:06:28.562 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:28.562 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:06:28.562 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:06:28.562 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:06:28.562 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:28.562 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:06:28.562 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:06:28.563 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:06:28.563 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:06:28.563 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:28.564 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:06:28.564 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:06:28.564 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:06:28.564 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:28.564 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:06:28.564 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:06:28.564 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:06:28.564 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:06:28.564 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:06:28.566 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:06:28.566 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:06:28.566 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:28.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:28.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:28.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:28.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:28.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:28.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:28.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:28.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:28.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:28.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:28.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:28.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:28.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:28.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:28.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:28.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:28.571 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:06:29.033 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:06:29.077 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:06:29.077 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:06:29.078 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:06:29.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:06:29.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:06:29.081 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:29.081 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:29.081 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:29.081 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:29.082 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:06:29.082 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:06:29.082 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:06:29.082 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:06:29.082 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:06:29.082 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:06:29.082 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:06:34.084 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:06:34.084 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:06:34.084 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:06:34.084 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:06:34.084 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:06:34.084 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:06:34.087 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:06:34.087 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:06:34.087 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:34.087 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:06:34.087 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:06:34.088 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:06:34.088 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:06:34.088 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:06:34.088 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:34.089 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:06:34.089 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:06:34.089 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:06:34.089 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:06:34.089 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:34.090 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:06:34.090 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:06:34.090 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:06:34.090 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:34.090 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:06:34.090 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:06:34.090 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:06:34.090 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:06:34.090 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:34.091 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:06:34.091 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:06:34.091 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:06:34.091 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:34.091 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:06:34.091 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:06:34.091 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:06:34.091 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:06:34.091 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:34.093 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:06:34.093 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:06:34.093 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:06:34.093 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:06:34.093 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:06:34.093 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:06:34.093 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:06:34.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:06:34.093 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:06:34.094 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:06:34.094 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:06:34.094 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:34.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:34.098 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:06:34.561 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:06:34.607 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:06:34.608 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:06:34.608 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:06:34.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:06:34.611 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:34.611 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:34.611 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:34.611 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:34.612 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:06:34.612 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:06:34.612 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:06:34.612 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:06:34.612 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:06:34.612 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:06:34.612 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:06:34.612 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:06:34.612 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:06:34.612 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:06:34.612 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:06:34.612 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:06:34.612 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:06:39.614 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:06:39.614 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:06:39.614 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:06:39.614 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:06:39.614 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:06:39.614 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:06:39.617 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:06:39.617 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:06:39.617 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:39.618 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:06:39.618 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:06:39.618 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:06:39.619 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:06:39.619 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:06:39.619 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:39.619 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:06:39.619 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:06:39.619 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:06:39.619 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:06:39.619 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:39.620 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:06:39.620 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:06:39.620 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:06:39.620 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:39.620 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:06:39.620 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:06:39.620 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:06:39.620 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:06:39.620 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:39.621 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:06:39.621 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:06:39.621 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:06:39.621 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:39.621 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:06:39.621 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:06:39.621 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:06:39.621 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:06:39.621 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:39.623 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:06:39.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:06:39.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:06:39.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:06:39.623 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:06:39.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:06:39.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:06:39.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:39.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:06:39.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:06:39.623 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:06:39.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:39.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:39.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:39.623 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:39.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:39.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:39.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:39.623 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:06:39.623 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:06:39.623 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:06:39.623 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:06:39.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:39.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:39.624 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:39.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:06:39.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:39.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:39.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:39.624 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:39.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:39.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:39.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:39.624 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:39.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:39.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:39.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:39.624 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:39.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:39.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:39.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:39.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:39.624 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:39.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:39.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:39.624 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:39.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:39.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:39.628 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:06:40.090 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:06:40.136 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:06:40.137 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:06:40.137 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:06:40.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:06:40.139 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:06:40.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:06:40.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:06:40.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:06:40.139 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:06:40.139 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:06:40.140 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:06:40.140 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:06:40.553 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:06:40.625 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:40.625 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:40.625 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:40.626 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:41.016 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:06:41.478 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:06:41.626 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:41.626 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:41.626 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:41.626 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:41.940 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:06:42.404 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:06:42.626 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:42.627 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:42.627 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:42.627 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:42.868 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:06:43.183 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:06:43.183 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-06 03:06:43.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:06:43.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:06:43.234 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:06:43.234 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:06:43.234 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:06:43.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:06:43.235 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:43.235 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:43.235 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:43.235 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:43.236 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:06:43.236 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:06:43.236 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:06:43.236 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:06:43.236 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:06:43.236 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:06:43.236 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:06:48.238 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:06:48.238 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:06:48.238 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:06:48.238 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:06:48.238 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:06:48.238 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:06:48.241 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:06:48.241 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:06:48.241 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:48.241 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:06:48.241 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:06:48.243 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:06:48.243 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:06:48.243 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:06:48.243 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:48.243 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:06:48.243 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:06:48.243 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:06:48.243 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:06:48.243 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:48.245 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:06:48.245 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:06:48.245 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:06:48.245 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:48.245 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:06:48.245 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:06:48.246 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:06:48.246 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:06:48.246 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:48.248 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:06:48.248 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:06:48.248 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:06:48.248 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:48.248 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:06:48.248 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:06:48.248 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:06:48.248 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:06:48.248 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:48.250 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:06:48.250 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:06:48.250 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:06:48.250 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:06:48.250 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:06:48.250 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:06:48.251 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:06:48.251 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:06:48.251 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:48.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:48.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:48.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:48.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:48.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:48.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:48.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:48.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:48.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:48.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:48.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:48.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:48.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:48.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:48.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:48.256 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:06:48.719 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:06:48.767 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:06:48.768 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:06:48.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:06:48.768 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:06:48.769 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:06:48.769 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:06:48.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:06:48.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:06:48.770 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:06:48.770 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:06:48.770 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:06:48.770 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:06:49.183 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:06:49.254 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:49.254 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:49.254 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:49.254 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:49.647 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:06:50.112 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:06:50.255 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:50.255 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:50.255 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:50.255 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:50.574 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:06:51.037 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:06:51.256 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:51.256 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:51.256 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:51.256 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:51.500 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:06:51.843 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:06:51.843 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-06 03:06:51.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:06:51.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:06:51.964 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:06:52.257 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:52.257 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:52.257 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:52.257 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:52.427 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:06:52.436 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:06:52.436 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:06:52.436 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:06:52.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:06:52.441 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:52.442 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:52.442 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:52.442 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:52.444 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:06:52.444 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:06:52.444 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:06:52.444 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:06:52.444 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:06:52.444 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:06:52.444 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:06:52.444 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=924 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:06:52.444 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=924 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:06:52.444 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=924 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:06:52.444 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=924 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:06:52.444 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=924 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:06:52.444 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=924 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:06:52.444 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=924 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:06:52.444 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=924 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:06:57.444 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:06:57.444 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:06:57.444 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:06:57.444 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:06:57.444 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:06:57.444 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:06:57.449 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:06:57.449 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:06:57.450 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:57.450 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:06:57.450 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:06:57.451 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:06:57.451 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:06:57.451 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:06:57.451 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:57.451 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:06:57.451 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:06:57.451 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:06:57.451 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:06:57.451 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:57.453 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:06:57.453 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:06:57.453 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:06:57.453 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:57.453 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:06:57.453 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:06:57.453 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:06:57.453 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:06:57.453 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:57.455 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:06:57.455 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:06:57.455 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:06:57.455 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:06:57.455 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:06:57.455 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:06:57.455 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:06:57.455 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:06:57.455 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:57.458 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:06:57.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:06:57.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:06:57.459 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:06:57.459 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:06:57.459 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:57.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:57.460 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:57.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:57.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:57.460 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:06:57.460 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:57.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:57.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:57.460 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:06:57.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:57.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:57.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:06:57.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:57.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:57.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:06:57.464 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:06:57.928 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:06:57.970 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:06:57.970 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:06:57.970 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:06:57.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:06:57.972 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:06:57.972 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:06:57.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:06:57.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:06:57.972 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:06:57.972 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:06:57.972 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:06:57.973 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:06:58.391 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:06:58.461 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:58.461 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:58.462 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:58.462 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:58.855 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:06:59.319 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:06:59.461 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:06:59.461 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:06:59.462 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:06:59.462 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:06:59.784 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:07:00.253 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:07:00.462 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:00.462 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:00.463 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:00.463 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:00.717 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:07:01.034 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:07:01.034 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-06 03:07:01.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:07:01.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:07:01.181 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:07:01.462 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:01.462 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:01.463 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:01.463 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:01.644 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:07:02.107 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:07:02.464 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:02.464 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:02.464 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:02.464 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:02.570 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:07:03.033 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:07:03.497 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:07:03.960 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:07:04.422 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:07:04.885 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:07:05.348 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:07:05.811 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:07:06.035 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:07:06.035 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:07:06.035 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:07:06.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:07:06.039 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:06.039 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:06.039 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:06.039 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:06.040 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:07:06.040 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:07:06.040 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:07:06.040 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:07:06.040 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:07:06.040 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:07:06.040 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:07:11.049 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:07:11.050 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:07:11.050 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:07:11.050 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:07:11.050 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:07:11.050 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:07:11.058 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:07:11.059 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:07:11.059 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:07:11.059 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:07:11.059 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:07:11.060 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:07:11.061 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:07:11.061 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:07:11.061 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:07:11.061 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:07:11.061 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:07:11.061 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:07:11.061 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:07:11.061 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:11.062 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:07:11.063 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:07:11.063 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:07:11.063 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:07:11.063 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:07:11.063 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:07:11.063 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:07:11.063 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:07:11.063 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:11.064 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:07:11.064 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:07:11.064 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:07:11.064 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:07:11.064 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:07:11.064 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:07:11.064 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:07:11.064 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:07:11.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:11.066 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:07:11.066 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:07:11.066 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:07:11.066 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:07:11.066 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:07:11.066 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:07:11.066 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:07:11.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:07:11.066 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:11.066 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:07:11.066 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:07:11.066 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:11.066 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:11.066 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:11.066 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:11.066 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:07:11.067 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:07:11.067 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:07:11.067 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:11.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:11.071 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:07:11.533 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:07:11.607 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:07:11.609 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:07:11.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:07:11.612 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:07:11.616 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:07:11.616 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:07:11.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:07:11.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:07:11.617 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:07:11.617 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:07:11.617 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:07:11.617 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:07:12.005 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:07:12.069 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:12.070 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:12.070 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:12.070 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:12.508 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:07:12.973 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:07:13.071 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:13.071 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:13.071 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:13.071 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:13.436 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:07:13.902 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:07:14.071 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:14.071 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:14.071 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:14.071 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:14.365 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:07:14.648 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:07:14.648 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-06 03:07:14.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:07:14.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:07:14.831 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:07:15.072 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:15.072 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:15.072 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:15.073 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:15.297 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:07:15.762 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:07:16.073 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:16.073 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:16.073 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:16.073 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:16.226 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:07:16.691 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:07:17.154 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:07:17.620 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:07:18.083 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:07:18.548 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:07:19.014 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:07:19.478 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:07:19.650 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:07:19.650 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:07:19.650 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:07:19.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:07:19.654 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:19.654 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:19.654 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:19.654 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:19.655 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:07:19.655 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:07:19.655 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:07:19.655 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:07:19.655 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:07:19.655 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:07:19.655 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:07:24.657 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:07:24.657 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:07:24.657 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:07:24.657 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:07:24.657 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:07:24.657 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:07:24.660 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:07:24.661 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:07:24.661 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:07:24.661 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:07:24.661 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:07:24.662 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:07:24.662 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:07:24.662 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:07:24.662 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:07:24.662 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:07:24.662 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:07:24.662 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:07:24.662 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:07:24.662 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:24.663 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:07:24.663 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:07:24.663 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:07:24.663 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:07:24.663 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:07:24.663 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:07:24.663 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:07:24.663 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:07:24.663 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:24.664 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:07:24.664 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:07:24.664 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:07:24.664 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:07:24.664 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:07:24.664 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:07:24.664 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:07:24.664 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:07:24.665 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:24.666 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:07:24.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:07:24.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:07:24.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:07:24.666 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:07:24.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:07:24.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:07:24.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:07:24.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:24.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:07:24.666 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:07:24.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:24.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:24.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:24.666 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:07:24.667 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:07:24.667 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:07:24.667 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:24.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:24.671 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:07:25.136 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:07:25.178 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:07:25.179 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:07:25.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:07:25.179 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:07:25.180 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:07:25.180 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:07:25.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:07:25.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:07:25.181 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:07:25.181 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:07:25.181 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:07:25.181 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:07:25.604 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:07:25.669 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:25.669 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:25.669 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:25.669 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:26.070 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:07:26.533 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:07:26.669 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:26.669 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:26.669 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:26.669 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:26.996 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:07:27.464 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:07:27.669 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:27.670 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:27.670 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:27.670 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:27.929 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:07:28.231 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:07:28.231 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-06 03:07:28.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:07:28.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:07:28.398 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:07:28.671 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:28.671 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:28.671 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:28.671 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:28.871 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:07:29.343 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:07:29.671 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:29.672 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:29.672 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:29.672 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:29.816 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:07:30.289 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:07:30.761 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:07:31.230 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:07:31.696 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:07:32.162 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:07:32.627 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:07:33.092 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:07:33.234 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:07:33.234 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:07:33.235 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:07:33.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:07:33.252 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:33.253 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:33.253 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:33.253 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:33.255 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:07:33.255 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:07:33.256 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:07:33.256 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:07:33.256 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:07:33.256 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:07:33.256 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:07:38.255 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:07:38.365 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:07:38.365 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:07:38.365 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:07:38.365 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:07:38.365 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:07:38.366 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:07:38.366 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:07:38.366 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:07:38.366 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:07:38.366 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:07:38.368 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:07:38.368 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:07:38.368 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:07:38.368 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:07:38.369 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:07:38.369 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:07:38.369 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:07:38.369 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:07:38.369 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:38.370 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:07:38.370 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:07:38.370 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:07:38.370 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:07:38.370 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:07:38.370 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:07:38.370 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:07:38.370 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:07:38.370 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:38.371 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:07:38.372 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:07:38.372 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:07:38.372 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:07:38.372 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:07:38.372 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:07:38.372 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:07:38.372 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:07:38.372 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:07:38.374 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:07:38.374 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:07:38.374 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:38.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:38.379 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:07:38.846 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:07:38.894 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:07:38.895 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:07:38.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:07:38.898 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:07:38.903 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:07:38.903 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:07:38.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:07:38.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:07:38.904 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:07:38.904 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:07:38.904 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:07:38.904 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:07:38.935 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:07:38.935 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-06 03:07:38.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:07:38.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:07:39.313 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:07:39.377 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:39.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:39.378 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:39.378 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:39.778 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:07:40.242 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:07:40.379 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:40.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:40.379 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:40.379 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:40.705 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:07:41.169 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:07:41.379 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:41.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:41.379 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:41.379 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:41.633 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:07:42.098 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:07:42.380 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:42.380 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:42.380 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:42.380 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:42.562 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:07:43.031 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:07:43.381 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:43.382 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:43.382 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:43.382 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:43.499 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:07:43.935 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:07:43.936 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:07:43.936 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:07:43.940 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:43.940 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:43.940 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:43.940 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:43.942 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:07:43.943 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:07:43.943 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:07:43.943 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:07:43.943 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:07:43.944 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:07:43.944 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:07:43.944 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1221 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:07:43.944 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1221 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:07:43.944 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1221 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:07:43.944 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1221 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:07:43.944 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1221 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:07:43.944 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1221 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:07:48.951 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:07:48.951 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:07:48.952 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:07:48.952 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:07:48.952 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:07:48.952 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:07:48.962 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:07:48.963 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:07:48.963 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:07:48.963 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:07:48.963 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:07:48.965 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:07:48.965 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:07:48.965 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:07:48.965 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:07:48.965 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:07:48.965 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:07:48.965 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:07:48.965 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:07:48.965 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:48.966 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:07:48.967 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:07:48.967 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:07:48.967 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:07:48.967 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:07:48.967 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:07:48.967 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:07:48.967 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:07:48.967 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:48.968 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:07:48.968 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:07:48.968 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:07:48.968 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:07:48.968 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:07:48.968 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:07:48.968 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:07:48.968 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:07:48.968 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:48.970 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:07:48.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:07:48.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:07:48.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:07:48.970 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:07:48.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:07:48.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:07:48.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:48.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:07:48.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:07:48.970 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:07:48.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:48.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:48.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:48.970 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:48.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:48.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:48.970 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:07:48.970 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:07:48.970 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:07:48.970 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:07:48.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:48.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:48.975 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:07:49.441 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:07:49.486 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:07:49.487 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:07:49.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:07:49.488 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:07:49.490 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:07:49.490 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:07:49.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:07:49.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:07:49.491 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:07:49.491 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:07:49.491 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:07:49.491 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:07:49.906 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:07:49.972 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:49.973 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:49.973 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:49.973 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:50.376 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:07:50.839 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:07:50.973 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:50.973 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:50.973 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:50.973 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:51.303 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:07:51.766 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:07:51.973 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:51.973 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:51.973 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:51.973 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:52.228 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:07:52.543 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:07:52.543 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-06 03:07:52.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:07:52.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:07:52.690 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:07:52.974 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:52.975 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:52.975 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:52.975 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:53.156 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:07:53.620 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:07:53.976 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:53.976 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:53.976 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:53.976 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:54.082 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:07:54.544 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:07:54.544 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:07:54.544 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:07:54.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:07:54.546 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:07:54.546 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:54.547 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:54.547 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:54.547 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:54.547 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:07:54.547 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:07:54.547 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:07:54.547 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:07:54.547 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:07:54.547 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:07:54.547 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:07:59.549 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:07:59.549 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:07:59.549 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:07:59.549 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:07:59.549 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:07:59.549 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:07:59.552 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:07:59.552 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:07:59.552 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:07:59.552 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:07:59.552 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:07:59.553 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:07:59.553 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:07:59.553 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:07:59.553 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:07:59.553 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:07:59.553 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:07:59.553 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:07:59.553 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:07:59.554 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:07:59.554 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:07:59.554 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:07:59.554 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:07:59.554 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:07:59.554 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:07:59.554 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:07:59.554 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:07:59.554 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:07:59.554 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:07:59.555 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:07:59.555 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:07:59.555 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:07:59.555 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:07:59.556 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:07:59.556 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:07:59.556 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:07:59.556 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:07:59.556 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:07:59.557 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:07:59.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:07:59.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:07:59.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:07:59.557 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:07:59.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:07:59.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:07:59.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:59.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:07:59.558 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:07:59.558 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:07:59.558 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:07:59.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:07:59.562 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:08:00.025 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:08:00.070 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:08:00.071 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:08:00.071 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:08:00.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:08:00.073 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:08:00.073 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:08:00.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:08:00.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:08:00.073 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:08:00.073 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:08:00.073 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:08:00.073 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:08:00.488 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:08:00.560 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:00.560 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:00.560 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:00.560 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:00.950 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:08:01.413 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:08:01.560 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:01.560 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:01.561 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:01.561 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:01.876 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:08:02.338 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:08:02.561 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:02.561 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:02.561 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:02.561 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:02.801 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:08:03.263 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:08:03.293 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:08:03.293 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:08:03.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:08:03.294 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:03.294 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:03.294 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:03.295 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:03.295 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:08:03.295 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:08:03.295 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:08:03.295 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:08:03.295 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:08:03.295 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:08:03.295 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:08:08.297 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:08:08.297 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:08:08.297 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:08:08.297 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:08:08.297 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:08:08.297 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:08:08.300 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:08:08.300 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:08:08.300 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:08:08.301 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:08:08.301 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:08:08.301 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:08:08.302 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:08:08.302 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:08:08.302 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:08:08.302 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:08:08.302 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:08:08.302 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:08:08.302 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:08:08.302 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:08.303 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:08:08.303 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:08:08.303 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:08:08.303 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:08:08.303 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:08:08.303 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:08:08.303 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:08:08.303 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:08:08.303 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:08.304 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:08:08.304 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:08:08.304 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:08:08.304 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:08:08.304 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:08:08.304 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:08:08.304 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:08:08.304 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:08:08.304 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:08.306 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:08:08.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:08:08.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:08:08.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:08:08.306 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:08:08.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:08:08.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:08:08.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:08.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:08:08.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:08:08.306 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:08:08.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:08.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:08.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:08.306 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:08.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:08.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:08.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:08.306 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:08:08.306 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:08:08.306 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:08:08.306 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:08:08.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:08.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:08.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:08.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:08:08.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:08.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:08.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:08.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:08.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:08.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:08.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:08.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:08.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:08.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:08.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:08.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:08.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:08.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:08.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:08.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:08.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:08.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:08.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:08.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:08.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:08.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:08.311 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:08:08.773 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:08:08.817 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:08:08.818 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:08:08.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:08:08.819 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:08:08.821 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:08:08.821 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:08:08.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:08:08.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:08:08.821 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:08:08.821 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:08:08.821 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:08:08.821 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:08:09.236 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:08:09.309 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:09.309 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:09.309 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:09.309 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:09.698 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:08:10.161 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:08:10.309 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:10.309 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:10.309 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:10.309 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:10.623 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:08:11.086 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:08:11.310 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:11.310 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:11.310 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:11.310 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:11.548 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:08:12.011 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:08:12.310 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:12.310 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:12.310 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:12.310 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:12.324 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:08:12.324 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:08:12.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:08:12.325 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:12.325 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:12.325 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:12.325 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:12.326 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:08:12.326 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:08:12.326 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:08:12.326 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:08:12.326 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:08:12.326 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:08:12.326 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:08:17.328 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:08:17.328 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:08:17.328 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:08:17.328 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:08:17.328 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:08:17.328 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:08:17.335 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:08:17.335 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:08:17.335 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:08:17.335 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:08:17.335 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:08:17.337 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:08:17.337 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:08:17.337 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:08:17.337 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:08:17.337 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:08:17.337 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:08:17.337 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:08:17.337 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:08:17.337 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:17.338 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:08:17.338 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:08:17.338 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:08:17.338 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:08:17.338 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:08:17.338 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:08:17.338 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:08:17.338 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:08:17.338 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:17.339 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:08:17.339 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:08:17.339 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:08:17.339 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:08:17.339 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:08:17.339 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:08:17.340 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:08:17.340 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:08:17.340 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:17.341 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:08:17.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:08:17.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:08:17.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:08:17.341 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:08:17.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:08:17.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:08:17.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:17.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:08:17.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:08:17.341 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:08:17.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:17.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:08:17.342 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:08:17.342 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:08:17.342 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:17.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:17.346 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:08:17.809 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:08:17.873 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:08:17.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:08:17.873 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:08:17.874 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:08:17.876 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:08:17.876 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:08:17.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:08:17.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:08:17.876 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:08:17.876 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:08:17.877 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:08:17.877 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:08:18.124 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:08:18.124 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:08:18.125 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:18.125 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:18.125 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:18.125 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:18.126 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:08:18.126 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:08:18.126 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:08:18.126 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:08:18.126 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:08:18.126 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:08:18.127 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:08:23.128 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:08:23.128 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:08:23.128 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:08:23.128 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:08:23.128 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:08:23.128 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:08:23.131 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:08:23.131 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:08:23.131 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:08:23.132 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:08:23.132 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:08:23.133 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:08:23.133 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:08:23.133 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:08:23.133 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:08:23.133 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:08:23.133 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:08:23.133 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:08:23.133 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:08:23.133 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:23.134 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:08:23.134 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:08:23.134 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:08:23.134 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:08:23.134 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:08:23.134 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:08:23.134 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:08:23.134 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:08:23.134 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:23.135 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:08:23.135 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:08:23.136 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:08:23.136 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:08:23.136 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:08:23.136 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:08:23.136 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:08:23.136 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:08:23.136 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:08:23.138 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:08:23.138 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:08:23.138 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:23.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:23.143 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:08:23.608 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:08:23.652 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:08:23.652 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:08:23.653 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:08:23.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:08:23.654 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:08:23.654 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:08:23.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:08:23.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:08:23.655 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:08:23.655 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:08:23.655 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:08:23.655 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:08:23.877 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:08:23.877 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:08:23.879 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:23.879 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:23.879 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:23.879 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:23.879 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:08:23.879 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:08:23.879 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:08:23.879 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:08:23.880 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:08:23.880 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:08:23.880 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:08:28.882 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:08:28.882 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:08:28.882 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:08:28.882 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:08:28.882 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:08:28.882 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:08:28.885 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:08:28.885 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:08:28.885 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:08:28.885 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:08:28.885 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:08:28.886 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:08:28.886 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:08:28.886 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:08:28.886 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:08:28.887 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:08:28.887 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:08:28.887 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:08:28.887 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:08:28.887 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:28.888 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:08:28.888 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:08:28.888 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:08:28.888 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:08:28.888 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:08:28.888 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:08:28.888 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:08:28.888 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:08:28.888 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:28.889 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:08:28.889 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:08:28.889 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:08:28.889 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:08:28.889 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:08:28.889 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:08:28.889 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:08:28.889 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:08:28.889 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:28.891 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:08:28.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:08:28.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:08:28.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:08:28.891 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:08:28.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:08:28.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:08:28.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:28.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:08:28.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:08:28.891 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:08:28.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:28.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:28.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:28.891 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:28.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:28.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:28.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:28.891 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:08:28.891 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:08:28.891 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:08:28.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:28.891 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:08:28.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:28.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:28.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:08:28.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:28.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:28.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:28.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:28.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:28.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:28.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:28.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:28.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:28.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:28.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:28.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:28.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:28.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:28.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:28.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:28.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:28.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:28.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:28.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:28.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:28.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:28.896 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:08:29.361 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:08:29.405 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:08:29.406 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:08:29.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:08:29.407 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:08:29.408 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:08:29.408 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:08:29.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:08:29.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:08:29.409 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:08:29.409 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:08:29.409 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:08:29.409 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:08:29.824 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:08:29.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:29.893 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:29.893 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:29.894 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:30.286 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:08:30.749 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:08:30.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:30.894 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:30.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:30.895 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:31.212 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:08:31.677 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:08:31.894 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:31.895 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:31.895 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:31.895 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:32.140 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:08:32.603 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:08:32.895 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:32.895 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:32.895 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:32.895 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:33.066 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:08:33.529 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:08:33.896 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:33.896 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:33.896 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:33.896 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:33.992 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:08:34.458 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:08:34.921 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:08:35.383 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:08:35.848 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:08:36.311 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:08:36.774 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:08:37.237 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:08:37.700 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:08:38.163 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:08:38.528 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:08:38.528 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:08:38.530 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:38.530 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:38.530 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:38.530 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:38.530 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:08:38.530 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:08:38.530 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:08:38.531 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:08:38.531 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:08:38.531 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:08:38.531 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:08:43.533 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:08:43.533 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:08:43.533 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:08:43.533 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:08:43.533 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:08:43.533 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:08:43.537 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:08:43.538 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:08:43.538 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:08:43.538 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:08:43.538 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:08:43.539 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:08:43.539 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:08:43.539 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:08:43.539 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:08:43.539 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:08:43.539 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:08:43.539 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:08:43.539 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:08:43.539 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:43.540 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:08:43.540 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:08:43.540 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:08:43.540 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:08:43.540 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:08:43.541 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:08:43.541 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:08:43.541 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:08:43.541 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:43.542 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:08:43.542 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:08:43.542 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:08:43.542 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:08:43.542 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:08:43.542 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:08:43.542 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:08:43.542 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:08:43.542 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:43.543 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:08:43.544 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:08:43.544 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:08:43.544 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:43.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:43.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:43.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:43.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:43.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:43.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:43.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:43.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:43.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:43.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:43.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:43.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:43.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:43.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:43.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:43.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:43.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:43.549 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:08:44.012 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:08:44.055 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:08:44.056 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:08:44.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:08:44.056 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:08:44.058 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:08:44.058 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:08:44.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:08:44.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:08:44.058 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:08:44.058 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:08:44.058 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:08:44.058 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:08:44.475 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:08:44.546 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:44.546 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:44.546 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:44.546 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:44.937 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:08:45.400 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:08:45.546 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:45.546 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:45.546 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:45.546 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:45.863 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:08:46.325 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:08:46.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:46.547 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:46.547 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:46.547 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:46.789 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:08:47.252 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:08:47.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:47.547 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:47.547 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:47.547 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:47.715 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:08:48.177 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:08:48.548 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:48.548 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:48.548 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:48.548 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:48.640 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:08:49.105 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:08:49.568 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:08:50.031 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:08:50.494 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:08:50.958 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:08:51.421 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:08:51.886 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:08:52.351 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:08:52.816 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:08:52.954 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:08:52.954 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:08:52.956 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:52.956 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:52.956 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:52.956 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:52.958 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:08:52.958 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:08:52.958 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:08:52.958 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:08:52.958 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:08:52.958 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:08:52.958 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:08:52.958 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2073 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:08:52.958 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2073 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:08:52.958 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2073 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:08:52.958 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2073 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:08:52.958 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2073 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:08:52.958 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2073 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:08:57.959 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:08:57.959 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:08:57.959 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:08:57.959 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:08:57.959 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:08:57.959 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:08:57.963 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:08:57.963 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:08:57.963 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:08:57.963 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:08:57.963 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:08:57.964 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:08:58.023 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:08:58.023 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:08:58.023 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:08:58.023 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:08:58.023 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:08:58.023 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:08:58.023 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:08:58.024 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:08:58.024 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:08:58.024 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:58.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:08:58.028 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:08:58.492 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:08:58.541 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:08:58.542 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:08:58.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:08:58.542 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:08:58.544 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:08:58.544 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:08:58.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:08:58.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:08:58.544 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:08:58.544 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:08:58.544 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:08:58.544 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:08:58.956 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:08:59.026 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:08:59.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:08:59.028 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:08:59.029 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:08:59.419 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:08:59.883 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:09:00.026 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:00.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:00.028 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:00.030 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:00.346 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:09:00.809 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:09:01.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:01.028 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:01.029 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:01.030 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:01.272 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:09:01.590 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:09:01.590 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-06 03:09:01.590 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:09:01.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:09:01.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:09:01.735 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:09:02.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:02.028 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:02.029 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:02.030 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:02.199 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:09:02.620 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:09:02.620 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:09:02.620 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:09:02.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:09:02.622 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:02.622 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:02.622 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:02.623 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:02.623 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:09:02.623 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:09:02.623 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:09:02.623 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:09:02.624 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:09:02.624 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:09:02.624 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:09:02.624 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1012 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:09:02.624 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1012 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:09:02.624 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1012 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:09:02.624 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1012 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:09:02.624 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1012 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:09:02.624 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1012 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:09:07.625 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:09:07.625 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:09:07.625 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:09:07.625 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:09:07.625 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:09:07.625 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:09:07.633 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:09:07.633 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:09:07.633 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:07.633 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:09:07.633 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:09:07.635 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:09:07.635 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:09:07.636 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:09:07.636 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:07.636 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:09:07.636 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:09:07.636 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:09:07.636 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:09:07.636 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:07.638 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:09:07.638 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:09:07.638 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:09:07.638 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:07.638 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:09:07.638 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:09:07.638 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:09:07.638 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:09:07.638 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:07.640 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:09:07.641 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:09:07.641 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:09:07.641 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:07.641 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:09:07.641 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:09:07.641 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:09:07.641 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:09:07.641 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:07.643 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:09:07.643 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:09:07.643 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:09:07.643 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:09:07.643 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:09:07.643 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:09:07.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:09:07.644 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:07.644 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:09:07.644 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:09:07.644 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:09:07.644 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:07.644 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:07.644 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:07.644 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:07.644 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:07.644 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:07.644 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:09:07.644 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:09:07.644 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:09:07.644 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:09:07.644 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:07.644 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:07.644 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:07.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:09:07.645 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:07.645 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:07.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:07.645 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:07.645 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:07.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:07.645 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:07.645 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:07.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:07.645 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:07.645 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:07.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:07.645 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:07.645 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:07.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:07.645 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:07.645 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:07.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:07.645 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:07.645 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:07.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:07.645 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:07.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:07.649 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:09:08.112 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:09:08.160 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:09:08.160 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:09:08.161 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:09:08.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:09:08.256 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:08.256 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:08.256 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:08.256 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:08.257 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:09:08.257 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:09:08.257 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:09:08.257 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:09:08.257 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:09:08.257 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:09:08.257 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:09:13.259 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:09:13.259 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:09:13.259 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:09:13.259 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:09:13.259 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:09:13.259 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:09:13.267 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:09:13.267 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:09:13.267 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:13.268 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:09:13.268 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:09:13.269 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:09:13.270 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:09:13.270 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:09:13.270 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:13.270 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:09:13.270 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:09:13.270 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:09:13.270 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:09:13.270 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:13.272 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:09:13.272 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:09:13.272 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:09:13.272 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:13.273 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:09:13.273 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:09:13.273 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:09:13.273 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:09:13.273 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:13.275 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:09:13.275 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:09:13.275 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:09:13.275 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:13.275 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:09:13.275 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:09:13.275 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:09:13.275 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:09:13.275 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:13.279 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:09:13.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:09:13.279 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:09:13.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:09:13.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:09:13.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:09:13.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:09:13.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:09:13.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:13.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:09:13.279 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:09:13.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:13.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:13.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:13.279 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:13.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:13.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:09:13.280 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:09:13.280 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:09:13.280 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:13.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:13.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:13.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:13.284 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:09:13.748 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:09:13.798 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:09:13.799 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:09:13.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:09:13.800 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:09:14.212 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:09:14.283 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:14.283 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:14.283 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:14.283 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:14.677 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:09:15.140 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:09:15.284 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:15.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:15.284 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:15.284 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:15.604 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:09:16.067 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:09:16.284 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:16.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:16.284 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:16.284 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:16.529 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:09:16.992 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:09:17.285 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:17.285 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:17.285 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:17.285 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:17.456 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:09:17.918 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:09:18.285 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:18.285 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:18.285 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:18.285 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:18.381 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:09:18.844 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:09:19.306 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:09:19.769 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:09:20.232 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:09:20.699 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:09:21.161 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:09:21.623 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:09:22.086 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:09:22.548 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:09:22.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:09:22.811 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:22.811 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:22.811 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:22.811 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:22.811 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:09:22.812 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:09:22.812 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:09:22.812 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:09:22.812 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:09:22.812 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:09:22.812 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:09:27.813 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:09:27.814 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:09:27.814 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:09:27.814 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:09:27.814 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:09:27.814 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:09:27.817 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:09:27.817 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:09:27.817 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:27.817 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:09:27.817 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:09:27.818 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:09:27.818 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:09:27.819 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:09:27.819 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:27.819 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:09:27.819 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:09:27.819 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:09:27.819 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:09:27.819 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:27.820 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:09:27.820 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:09:27.820 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:09:27.820 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:27.820 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:09:27.820 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:09:27.820 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:09:27.820 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:09:27.820 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:27.821 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:09:27.821 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:09:27.822 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:09:27.822 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:27.822 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:09:27.822 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:09:27.822 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:09:27.822 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:09:27.822 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:09:27.824 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:09:27.824 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:09:27.824 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:27.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:27.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:27.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:27.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:27.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:27.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:27.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:27.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:27.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:27.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:27.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:27.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:27.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:27.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:27.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:27.829 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:09:28.296 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:09:28.338 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:09:28.339 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:09:28.339 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:09:28.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:09:28.758 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:09:28.827 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:28.828 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:28.830 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:28.831 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:29.220 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:09:29.683 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:09:29.828 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:29.828 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:29.830 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:29.831 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:30.147 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:09:30.612 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:09:30.828 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:30.828 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:30.831 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:30.832 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:31.075 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:09:31.538 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:09:31.829 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:32.063 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:32.064 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:32.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:32.527 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:09:32.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:09:32.541 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:32.542 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:32.542 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:32.542 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:32.543 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:09:32.543 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:09:32.543 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:09:32.543 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:09:32.543 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:09:32.543 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:09:32.543 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:09:37.544 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:09:37.544 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:09:37.544 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:09:37.544 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:09:37.544 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:09:37.544 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:09:37.548 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:09:37.548 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:09:37.548 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:37.548 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:09:37.548 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:09:37.549 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:09:37.549 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:09:37.549 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:09:37.549 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:37.550 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:09:37.550 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:09:37.550 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:09:37.550 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:09:37.550 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:37.551 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:09:37.551 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:09:37.551 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:09:37.551 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:37.551 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:09:37.551 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:09:37.551 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:09:37.551 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:09:37.552 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:37.553 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:09:37.553 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:09:37.553 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:09:37.553 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:37.553 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:09:37.553 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:09:37.553 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:09:37.553 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:09:37.553 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:09:37.556 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:09:37.556 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:09:37.556 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:37.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:37.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:37.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:37.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:37.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:37.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:37.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:37.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:37.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:37.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:37.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:37.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:37.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:37.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:37.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:37.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:37.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:37.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:37.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:37.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:37.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:37.561 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:09:38.025 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:09:38.073 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:09:38.073 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:09:38.074 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:09:38.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:09:38.488 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:09:38.559 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:38.687 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:38.687 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:38.687 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:38.955 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:09:39.419 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:09:39.687 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:39.688 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:39.688 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:39.688 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:39.882 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:09:40.344 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:09:40.688 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:40.688 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:40.688 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:40.688 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:40.807 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:09:41.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:09:41.094 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:41.094 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:41.094 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:41.094 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:41.095 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:09:41.095 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:09:41.095 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:09:41.095 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:09:41.095 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:09:41.095 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:09:41.095 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:09:41.095 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=779 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:09:41.095 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=779 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:09:41.095 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=779 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:09:41.095 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=779 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:09:41.095 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=779 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:09:41.095 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=779 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:09:46.098 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:09:46.098 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:09:46.098 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:09:46.098 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:09:46.098 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:09:46.098 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:09:46.102 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:09:46.102 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:09:46.102 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:46.102 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:09:46.102 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:09:46.103 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:09:46.103 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:09:46.103 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:09:46.103 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:46.103 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:09:46.103 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:09:46.103 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:09:46.103 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:09:46.103 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:46.104 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:09:46.105 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:09:46.105 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:09:46.105 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:46.105 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:09:46.105 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:09:46.105 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:09:46.105 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:09:46.105 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:46.106 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:09:46.106 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:09:46.106 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:09:46.106 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:46.106 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:09:46.106 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:09:46.106 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:09:46.106 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:09:46.106 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:46.108 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:09:46.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:09:46.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:09:46.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:09:46.108 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:09:46.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:09:46.109 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:09:46.109 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:09:46.109 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:46.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:46.113 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:09:46.576 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:09:46.623 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:09:46.623 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:09:46.624 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:09:46.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:09:46.633 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:09:46.633 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:09:46.633 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:09:46.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:09:46.637 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:09:46.637 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:09:46.637 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:09:46.637 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:09:46.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:09:46.667 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:09:46.667 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:09:46.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:09:46.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:09:47.038 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:09:47.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:09:47.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:09:47.045 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:09:47.045 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:09:47.047 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:47.047 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:47.047 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:47.047 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:47.048 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:09:47.048 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:09:47.048 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:09:47.048 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:09:47.048 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:09:47.048 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:09:47.048 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:09:47.048 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=208 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:09:47.048 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=208 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:09:47.048 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=208 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:09:47.048 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=208 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:09:47.048 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=208 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:09:52.050 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:09:52.050 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:09:52.050 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:09:52.050 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:09:52.050 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:09:52.050 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:09:52.053 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:09:52.054 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:09:52.054 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:52.054 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:09:52.054 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:09:52.055 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:09:52.055 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:09:52.055 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:09:52.055 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:52.055 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:09:52.055 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:09:52.055 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:09:52.055 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:09:52.055 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:52.056 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:09:52.056 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:09:52.056 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:09:52.056 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:52.056 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:09:52.056 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:09:52.056 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:09:52.056 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:09:52.056 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:52.058 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:09:52.058 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:09:52.058 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:09:52.058 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:52.058 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:09:52.058 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:09:52.058 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:09:52.058 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:09:52.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:09:52.060 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:09:52.060 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:09:52.060 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:52.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:52.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:52.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:52.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:52.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:52.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:52.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:52.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:52.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:52.065 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:09:52.527 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:09:52.575 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:09:52.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:09:52.576 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:09:52.576 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:09:52.581 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:52.581 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:52.581 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:52.581 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:52.582 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:09:52.582 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:09:52.582 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:09:52.582 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:09:52.582 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:09:52.582 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:09:52.582 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:09:57.584 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:09:57.584 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:09:57.584 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:09:57.584 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:09:57.584 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:09:57.584 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:09:57.590 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:09:57.590 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:09:57.591 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:57.591 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:09:57.591 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:09:57.592 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:09:57.592 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:09:57.592 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:09:57.592 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:57.592 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:09:57.592 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:09:57.592 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:09:57.592 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:09:57.592 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:57.594 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:09:57.594 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:09:57.594 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:09:57.594 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:57.594 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:09:57.594 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:09:57.594 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:09:57.594 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:09:57.594 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:57.596 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:09:57.596 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:09:57.596 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:09:57.596 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:09:57.596 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:09:57.596 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:09:57.596 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:09:57.596 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:09:57.596 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:57.599 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:09:57.599 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:09:57.599 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:09:57.599 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:09:57.599 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:09:57.599 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:09:57.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:09:57.599 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:57.599 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:09:57.599 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:09:57.599 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:09:57.599 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:57.599 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:57.599 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:57.599 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:57.599 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:57.599 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:57.599 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:09:57.599 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:09:57.599 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:09:57.599 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:57.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:09:57.604 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:09:58.067 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:09:58.114 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:09:58.115 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:09:58.115 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:09:58.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:09:58.529 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:09:58.602 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:58.603 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:58.604 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:58.607 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:58.994 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:09:59.458 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:09:59.603 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:09:59.603 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:09:59.604 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:09:59.608 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:09:59.922 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:10:00.121 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:00.121 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:00.121 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:00.121 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:00.122 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:10:00.122 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:10:00.122 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:10:00.122 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:10:00.122 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:10:00.122 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:10:00.122 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:10:05.124 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:10:05.124 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:10:05.124 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:10:05.124 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:10:05.124 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:10:05.124 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:10:05.132 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:10:05.132 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:10:05.132 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:05.132 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:10:05.132 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:10:05.134 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:10:05.134 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:10:05.134 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:10:05.134 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:05.134 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:10:05.134 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:10:05.134 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:10:05.134 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:10:05.135 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:05.137 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:10:05.137 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:10:05.137 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:10:05.137 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:05.137 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:10:05.137 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:10:05.137 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:10:05.137 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:10:05.137 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:05.139 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:10:05.139 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:10:05.139 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:10:05.139 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:05.139 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:10:05.140 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:10:05.140 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:10:05.140 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:10:05.140 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:05.143 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:10:05.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:10:05.143 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:10:05.143 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:10:05.143 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:10:05.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:10:05.143 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:10:05.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:10:05.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:05.143 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:10:05.143 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:10:05.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:10:05.144 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:10:05.144 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:10:05.144 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:05.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:05.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:05.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:05.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:05.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:05.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:05.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:05.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:05.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:05.148 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:10:05.611 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:10:05.663 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:10:05.663 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:10:05.664 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:10:05.664 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:10:05.664 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:10:05.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:10:05.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:10:05.664 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:10:05.664 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:10:05.664 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:10:05.665 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:10:05.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:10:06.074 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:10:06.147 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:06.147 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:06.148 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:06.152 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:06.537 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:10:07.000 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:10:07.147 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:07.148 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:07.148 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:07.152 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:07.462 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:10:07.925 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:10:08.147 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:08.149 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:08.149 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:08.153 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:08.388 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:10:08.401 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:10:08.401 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:10:08.402 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:08.402 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:08.402 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:08.402 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:08.402 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:10:08.402 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:10:08.402 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:10:08.402 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:10:08.402 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:10:08.402 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:10:08.403 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:10:13.404 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:10:13.404 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:10:13.404 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:10:13.404 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:10:13.404 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:10:13.404 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:10:13.407 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:10:13.407 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:10:13.407 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:13.407 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:10:13.407 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:10:13.409 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:10:13.409 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:10:13.409 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:10:13.409 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:13.409 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:10:13.409 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:10:13.409 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:10:13.409 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:10:13.409 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:13.411 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:10:13.411 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:10:13.411 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:10:13.411 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:13.411 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:10:13.411 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:10:13.411 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:10:13.411 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:10:13.411 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:13.413 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:10:13.413 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:10:13.413 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:10:13.413 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:13.413 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:10:13.413 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:10:13.413 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:10:13.413 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:10:13.413 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:13.415 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:10:13.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:10:13.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:10:13.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:10:13.415 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:10:13.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:10:13.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:10:13.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:10:13.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:13.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:10:13.415 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:10:13.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:13.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:13.415 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:13.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:13.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:13.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:13.415 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:10:13.415 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:10:13.415 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:10:13.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:13.415 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:10:13.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:13.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:13.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:10:13.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:13.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:13.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:13.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:13.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:13.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:13.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:13.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:13.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:13.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:13.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:13.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:13.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:13.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:13.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:13.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:13.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:13.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:13.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:13.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:13.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:13.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:13.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:13.420 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:10:13.884 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:10:13.929 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:10:13.929 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:10:13.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:10:13.930 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:10:13.931 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:10:13.931 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:10:13.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:10:13.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:10:13.931 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:10:13.931 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:10:13.931 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:10:13.931 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:10:14.346 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:10:14.417 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:14.417 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:14.418 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:14.418 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:14.809 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:10:15.273 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:10:15.418 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:15.418 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:15.419 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:15.419 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:15.735 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:10:15.986 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:10:15.986 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:10:15.987 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:15.987 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:15.987 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:15.987 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:15.988 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:10:15.988 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:10:15.988 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:10:15.988 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:10:15.988 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:10:15.988 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:10:15.988 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:10:20.990 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:10:20.990 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:10:20.990 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:10:20.990 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:10:20.990 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:10:20.990 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:10:20.993 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:10:20.993 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:10:20.993 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:20.993 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:10:20.993 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:10:20.994 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:10:20.994 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:10:20.994 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:10:20.994 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:20.994 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:10:20.994 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:10:20.994 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:10:20.994 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:10:20.994 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:20.995 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:10:20.995 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:10:20.996 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:10:20.996 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:20.996 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:10:20.996 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:10:20.996 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:10:20.996 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:10:20.996 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:20.997 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:10:20.997 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:10:20.997 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:10:20.997 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:20.997 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:10:20.997 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:10:20.997 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:10:20.997 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:10:20.997 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:10:20.999 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:10:20.999 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:10:20.999 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:20.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:21.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:21.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:21.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:21.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:21.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:21.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:21.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:21.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:21.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:21.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:21.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:21.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:21.004 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:10:21.467 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:10:21.510 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:10:21.511 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:10:21.511 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:10:21.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:10:21.512 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:10:21.512 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:10:21.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:10:21.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:10:21.513 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:10:21.513 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:10:21.513 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:10:21.513 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:10:21.929 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:10:22.001 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:22.001 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:22.001 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:22.002 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:22.392 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:10:22.854 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:10:23.001 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:23.001 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:23.001 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:23.002 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:23.317 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:10:23.779 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:10:24.002 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:24.002 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:24.002 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:24.003 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:24.242 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:10:24.256 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:10:24.256 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:10:24.258 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:24.258 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:24.258 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:24.258 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:24.258 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:10:24.258 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:10:24.258 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:10:24.258 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:10:24.258 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:10:24.259 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:10:24.259 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:10:29.533 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:10:29.533 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:10:29.533 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:10:29.533 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:10:29.533 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:10:29.533 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:10:29.536 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:10:29.537 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:10:29.537 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:29.537 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:10:29.537 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:10:29.538 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:10:29.538 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:10:29.538 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:10:29.538 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:29.538 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:10:29.538 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:10:29.538 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:10:29.538 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:10:29.538 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:29.539 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:10:29.539 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:10:29.539 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:10:29.539 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:29.539 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:10:29.539 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:10:29.539 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:10:29.539 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:10:29.539 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:29.540 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:10:29.540 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:10:29.540 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:10:29.540 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:29.540 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:10:29.540 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:10:29.540 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:10:29.540 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:10:29.540 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:29.541 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:10:29.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:10:29.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:10:29.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:10:29.541 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:10:29.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:10:29.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:10:29.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:29.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:10:29.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:10:29.542 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:10:29.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:29.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:29.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:29.542 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:29.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:29.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:29.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:29.542 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:10:29.542 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:10:29.542 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:10:29.542 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:10:29.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:29.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:29.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:29.542 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:10:29.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:29.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:29.542 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:10:29.542 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:10:29.542 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:10:29.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:29.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:29.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:34.545 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:10:34.545 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:10:34.545 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:10:34.545 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:10:34.545 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:10:34.545 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:10:34.551 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:10:34.551 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:10:34.551 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:34.551 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:10:34.551 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:10:34.553 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:10:34.554 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:10:34.554 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:10:34.554 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:34.554 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:10:34.554 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:10:34.554 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:10:34.554 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:10:34.554 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:34.556 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:10:34.556 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:10:34.556 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:10:34.556 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:34.556 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:10:34.556 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:10:34.556 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:10:34.556 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:10:34.556 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:34.557 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:10:34.557 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:10:34.557 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:10:34.557 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:34.557 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:10:34.557 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:10:34.557 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:10:34.557 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:10:34.557 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:34.559 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:10:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:10:34.559 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:10:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:10:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:10:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:10:34.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:10:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:10:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:10:34.559 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:10:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:34.559 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:34.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:10:34.560 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:10:34.560 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:34.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:34.564 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:10:35.029 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:10:35.074 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:10:35.075 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:10:35.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:10:35.076 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:10:35.079 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:10:35.079 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:10:35.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:10:35.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:10:35.079 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:10:35.079 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:10:35.079 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:10:35.080 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:10:35.494 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:10:35.561 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:35.561 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:35.561 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:35.563 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:35.957 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:10:36.419 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:10:36.562 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:36.562 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:36.562 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:36.563 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:36.882 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:10:37.131 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:10:37.131 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:10:37.134 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:37.134 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:37.134 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:37.134 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:37.135 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:10:37.135 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:10:37.135 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:10:37.135 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:10:37.135 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:10:37.135 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:10:37.135 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:10:37.135 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=567 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:10:37.135 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=567 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:10:37.135 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=567 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:10:37.135 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=567 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:10:37.135 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=567 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:10:37.135 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=567 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:10:42.137 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:10:42.137 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:10:42.137 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:10:42.137 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:10:42.137 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:10:42.137 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:10:42.143 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:10:42.144 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:10:42.144 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:42.144 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:10:42.144 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:10:42.146 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:10:42.146 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:10:42.146 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:10:42.146 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:42.146 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:10:42.146 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:10:42.146 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:10:42.146 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:10:42.146 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:42.148 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:10:42.148 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:10:42.148 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:10:42.148 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:42.148 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:10:42.148 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:10:42.148 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:10:42.148 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:10:42.148 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:42.150 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:10:42.150 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:10:42.150 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:10:42.150 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:42.150 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:10:42.150 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:10:42.150 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:10:42.150 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:10:42.150 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:42.154 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:10:42.154 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:10:42.154 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:10:42.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:10:42.154 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:10:42.154 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:10:42.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:10:42.154 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:42.154 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:10:42.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:10:42.154 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:10:42.154 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:42.154 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:10:42.155 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:10:42.155 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:42.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:42.159 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:10:42.623 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:10:42.673 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:10:42.674 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:10:42.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:10:42.674 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:10:42.677 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:10:42.677 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:10:42.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:10:42.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:10:42.677 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:10:42.678 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:10:42.678 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:10:42.678 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:10:43.085 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:10:43.158 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:43.158 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:43.159 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:43.162 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:43.548 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:10:44.011 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:10:44.158 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:44.158 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:44.159 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:44.163 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:44.473 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:10:44.936 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:10:45.159 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:45.159 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:45.160 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:45.163 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:45.399 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:10:45.863 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:10:46.159 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:46.159 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:46.160 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:46.164 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:46.328 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:10:46.339 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:10:46.339 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:10:46.341 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:46.341 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:46.341 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:46.341 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:46.342 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:10:46.342 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:10:46.342 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:10:46.342 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:10:46.342 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:10:46.342 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:10:46.342 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:10:51.345 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:10:51.345 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:10:51.345 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:10:51.345 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:10:51.345 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:10:51.345 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:10:51.352 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:10:51.353 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:10:51.353 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:51.353 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:10:51.353 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:10:51.355 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:10:51.355 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:10:51.356 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:10:51.356 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:51.356 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:10:51.356 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:10:51.356 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:10:51.356 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:10:51.356 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:51.358 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:10:51.358 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:10:51.358 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:10:51.358 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:51.358 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:10:51.358 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:10:51.358 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:10:51.358 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:10:51.358 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:51.361 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:10:51.361 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:10:51.361 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:10:51.361 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:10:51.361 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:10:51.361 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:10:51.361 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:10:51.361 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:10:51.361 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:51.365 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:10:51.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:10:51.365 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:10:51.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:10:51.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:10:51.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:10:51.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:10:51.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:10:51.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:51.366 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:10:51.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:51.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:10:51.366 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:51.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:51.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:51.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:51.366 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:10:51.366 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:10:51.366 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:10:51.366 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:10:51.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:51.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:51.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:51.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:10:51.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:51.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:51.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:51.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:51.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:51.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:51.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:51.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:51.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:51.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:51.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:51.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:51.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:51.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:51.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:51.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:10:51.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:51.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:10:51.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:51.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:51.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:51.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:10:51.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:51.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:10:51.371 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:10:51.834 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:10:51.891 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:10:51.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:10:51.892 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:10:51.893 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:10:51.897 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:10:51.897 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:10:51.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:10:51.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:10:51.897 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:10:51.897 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:10:51.898 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:10:51.898 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:10:52.299 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:10:52.370 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:52.370 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:52.372 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:52.375 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:52.763 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:10:53.228 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:10:53.371 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:53.371 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:53.372 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:53.376 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:53.694 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:10:54.159 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:10:54.371 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:54.371 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:54.372 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:54.377 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:54.629 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:10:55.098 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:10:55.371 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:55.371 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:55.373 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:55.378 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:55.564 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:10:55.814 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:10:55.814 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:10:55.822 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:10:55.822 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:10:55.823 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:10:55.823 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:10:55.824 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:10:55.824 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:10:55.824 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:10:55.824 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:10:55.824 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:10:55.824 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:10:55.824 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:10:55.824 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=977 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:10:55.824 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=977 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:10:55.824 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=977 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:10:55.824 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=977 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:11:00.824 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:11:00.824 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:11:00.824 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:00.824 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:00.824 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:00.824 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:00.832 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:00.832 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:11:00.832 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:00.833 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:11:00.833 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:11:00.835 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:11:00.835 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:11:00.835 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:11:00.835 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:00.835 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:00.835 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:11:00.835 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:11:00.835 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:11:00.835 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:00.838 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:11:00.838 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:11:00.838 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:11:00.838 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:00.838 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:00.838 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:11:00.838 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:11:00.838 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:11:00.838 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:00.840 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:11:00.841 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:11:00.841 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:11:00.841 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:00.841 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:00.841 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:11:00.841 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:11:00.841 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:11:00.841 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:00.845 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:11:00.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:11:00.845 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:11:00.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:11:00.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:11:00.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:11:00.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:11:00.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:11:00.845 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:11:00.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:00.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:11:00.845 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:00.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:00.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:00.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:00.846 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:11:00.846 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:11:00.846 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:11:00.846 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:11:00.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:00.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:00.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:00.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:11:00.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:00.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:00.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:00.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:00.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:00.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:00.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:00.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:00.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:00.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:00.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:00.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:00.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:00.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:00.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:00.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:00.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:00.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:00.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:00.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:00.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:00.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:00.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:00.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:00.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:00.850 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:11:01.316 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:11:01.370 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:11:01.371 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:11:01.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:11:01.372 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:11:01.781 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:11:01.850 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:01.850 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:01.851 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:01.854 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:02.246 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:11:02.710 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:11:02.851 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:02.851 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:02.852 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:02.854 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:03.175 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:11:03.379 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:03.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:03.379 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:03.379 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:03.380 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:03.381 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:03.381 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:03.381 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:03.381 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:11:03.381 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:11:03.381 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:11:08.382 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:11:08.382 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:11:08.382 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:08.382 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:08.382 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:08.382 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:08.389 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:08.389 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:11:08.389 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:08.390 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:11:08.390 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:11:08.391 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:11:08.391 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:11:08.391 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:11:08.391 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:08.391 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:08.392 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:11:08.392 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:11:08.392 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:11:08.392 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:08.394 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:11:08.394 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:11:08.394 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:11:08.394 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:08.394 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:08.394 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:11:08.394 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:11:08.394 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:11:08.394 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:08.396 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:11:08.396 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:11:08.396 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:11:08.396 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:08.396 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:08.396 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:11:08.396 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:11:08.396 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:11:08.396 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:08.400 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:11:08.400 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:11:08.400 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:11:08.400 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:11:08.400 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:11:08.400 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:11:08.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:11:08.400 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:11:08.400 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:08.400 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:11:08.400 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:08.400 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:11:08.400 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:08.400 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:08.400 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:08.400 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:11:08.400 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:11:08.400 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:11:08.400 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:11:08.400 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:08.400 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:08.400 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:08.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:08.405 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:11:08.870 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:11:08.917 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:11:08.918 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:11:08.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:11:08.919 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:11:08.926 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:11:08.926 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:11:08.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:11:08.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:08.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:11:09.334 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:11:09.403 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:09.404 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:09.404 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:09.409 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:09.799 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:11:10.263 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:11:10.404 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:10.405 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:10.405 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:10.409 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:10.727 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:11:11.190 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:11:11.404 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:11.405 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:11.405 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:11.410 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:11.654 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:11:11.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:11:11.939 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:11.939 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:11.939 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:11.939 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:11.940 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:11.940 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:11.940 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:11.940 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:11.940 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:11:11.940 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:11:11.940 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:11:11.941 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=778 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:11:11.941 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=778 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:11:11.941 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=778 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:11:11.941 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=778 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:11:16.942 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:11:16.942 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:11:16.942 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:16.942 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:16.942 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:16.942 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:16.946 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:16.946 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:11:16.946 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:16.946 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:11:16.946 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:11:16.947 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:11:16.947 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:11:16.947 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:11:16.947 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:16.947 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:16.947 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:11:16.947 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:11:16.947 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:11:16.947 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:16.948 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:11:16.948 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:11:16.948 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:11:16.948 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:16.949 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:16.949 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:11:16.949 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:11:16.949 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:11:16.949 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:16.950 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:11:16.950 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:11:16.950 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:11:16.950 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:16.950 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:16.950 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:11:16.950 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:11:16.950 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:11:16.950 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:11:16.952 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:11:16.952 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:11:16.952 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:16.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:16.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:16.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:16.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:16.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:16.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:16.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:16.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:16.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:16.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:16.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:16.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:16.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:16.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:16.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:16.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:16.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:16.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:16.957 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:11:17.421 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:11:17.463 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:11:17.464 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:11:17.464 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:11:17.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:11:17.470 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:11:17.470 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:11:17.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:11:17.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:17.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:11:17.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:11:17.478 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:17.478 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:17.478 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:17.478 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:17.479 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:17.479 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:17.479 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:17.479 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:11:17.479 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:11:17.479 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:11:17.479 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:22.481 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:11:22.481 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:11:22.481 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:22.481 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:22.481 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:22.481 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:22.485 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:22.486 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:11:22.486 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:22.486 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:11:22.486 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:11:22.487 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:11:22.487 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:11:22.487 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:11:22.487 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:22.487 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:22.487 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:11:22.487 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:11:22.487 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:11:22.488 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:22.489 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:11:22.489 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:11:22.489 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:11:22.489 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:22.489 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:22.489 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:11:22.490 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:11:22.490 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:11:22.490 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:22.491 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:11:22.491 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:11:22.491 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:11:22.491 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:22.491 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:22.491 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:11:22.491 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:11:22.491 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:11:22.491 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:22.493 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:11:22.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:11:22.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:11:22.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:11:22.493 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:11:22.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:11:22.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:11:22.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:22.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:11:22.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:11:22.493 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:11:22.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:22.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:22.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:22.493 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:22.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:22.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:22.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:22.493 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:11:22.493 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:11:22.493 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:11:22.493 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:22.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:22.498 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:11:22.960 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:11:23.005 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:11:23.005 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:11:23.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:11:23.005 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:11:23.222 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:11:23.222 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:11:23.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:11:23.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:23.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:11:23.423 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:11:23.495 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:23.495 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:23.495 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:23.495 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:23.885 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:11:24.347 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:11:24.496 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:24.496 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:24.496 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:24.496 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:24.810 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:11:25.272 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:11:25.496 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:25.497 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:25.497 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:25.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:25.734 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:11:26.197 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:11:26.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:11:26.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:26.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:26.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:26.232 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:26.232 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:26.233 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:26.233 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:11:26.233 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:11:26.233 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:11:26.233 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:26.233 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:26.233 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:26.233 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=826 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:11:26.233 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=826 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:11:26.233 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=826 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:11:26.233 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=826 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:11:26.233 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=826 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:11:26.233 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=826 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:11:31.235 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:11:31.235 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:11:31.235 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:31.235 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:31.235 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:31.235 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:31.238 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:31.238 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:11:31.238 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:31.239 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:11:31.239 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:11:31.240 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:11:31.240 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:11:31.240 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:11:31.240 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:31.240 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:31.240 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:11:31.240 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:11:31.240 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:11:31.240 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:31.241 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:11:31.241 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:11:31.241 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:11:31.241 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:31.241 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:31.241 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:11:31.241 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:11:31.241 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:11:31.241 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:31.242 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:11:31.242 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:11:31.243 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:11:31.243 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:31.243 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:31.243 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:11:31.243 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:11:31.243 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:11:31.243 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:31.244 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:11:31.245 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:11:31.245 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:11:31.245 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:31.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:31.250 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:11:31.712 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:11:31.767 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:11:31.768 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:11:31.768 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:11:31.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:11:31.774 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:11:31.774 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:11:31.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:11:31.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:31.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:11:31.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:11:31.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:31.783 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:31.783 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:31.783 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:31.783 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:31.784 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:31.784 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:31.784 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:11:31.784 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:11:31.784 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:11:31.784 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:31.784 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:36.786 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:11:36.786 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:11:36.786 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:36.786 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:36.786 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:36.786 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:36.790 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:36.790 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:11:36.790 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:36.790 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:11:36.790 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:11:36.791 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:11:36.791 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:11:36.791 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:11:36.791 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:36.791 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:36.791 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:11:36.791 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:11:36.791 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:11:36.791 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:36.792 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:11:36.792 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:11:36.792 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:11:36.792 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:36.792 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:36.792 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:11:36.793 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:11:36.793 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:11:36.793 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:36.793 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:11:36.794 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:11:36.794 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:11:36.794 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:36.794 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:36.794 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:11:36.794 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:11:36.794 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:11:36.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:36.795 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:11:36.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:11:36.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:11:36.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:11:36.795 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:11:36.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:11:36.796 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:11:36.796 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:11:36.796 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:36.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:36.801 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:11:37.263 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:11:37.308 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:11:37.309 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:11:37.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:11:37.309 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:11:37.313 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:37.313 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:37.313 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:37.313 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:37.313 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:37.313 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:37.313 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:11:37.313 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:11:37.313 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:11:37.313 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:37.314 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:42.315 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:11:42.315 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:11:42.315 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:42.315 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:42.315 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:42.315 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:42.317 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:42.318 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:11:42.318 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:42.318 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:11:42.318 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:11:42.319 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:11:42.319 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:11:42.319 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:11:42.320 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:42.320 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:42.320 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:11:42.320 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:11:42.320 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:11:42.320 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:42.321 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:11:42.321 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:11:42.321 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:11:42.321 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:42.321 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:42.321 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:11:42.321 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:11:42.321 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:11:42.321 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:42.323 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:11:42.323 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:11:42.323 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:11:42.323 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:42.323 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:42.323 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:11:42.323 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:11:42.323 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:11:42.323 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:42.325 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:11:42.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:11:42.325 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:11:42.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:11:42.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:11:42.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:11:42.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:11:42.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:11:42.326 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:11:42.326 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:11:42.326 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:42.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:42.330 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:11:42.794 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:11:42.840 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:11:42.841 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:11:42.841 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:11:42.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:11:42.844 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:42.844 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:42.844 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:42.844 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:42.845 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:42.845 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:42.845 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:11:42.845 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:11:42.845 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:11:42.845 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:42.845 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:47.847 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:11:47.847 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:11:47.847 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:47.847 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:47.847 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:47.847 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:47.850 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:47.850 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:11:47.850 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:47.851 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:11:47.851 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:11:47.851 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:11:47.852 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:11:47.852 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:11:47.852 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:47.852 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:47.852 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:11:47.852 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:11:47.852 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:11:47.852 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:47.853 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:11:47.853 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:11:47.853 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:11:47.853 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:47.853 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:47.853 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:11:47.853 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:11:47.853 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:11:47.853 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:47.854 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:11:47.854 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:11:47.854 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:11:47.854 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:47.854 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:47.854 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:11:47.854 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:11:47.854 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:11:47.854 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:11:47.857 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:11:47.857 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:47.857 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:47.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:47.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:47.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:47.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:47.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:47.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:47.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:47.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:47.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:47.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:47.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:47.862 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:11:48.324 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:11:48.369 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:11:48.369 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:11:48.370 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:11:48.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:11:48.372 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:48.372 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:48.372 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:48.372 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:48.373 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:48.373 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:48.373 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:11:48.373 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:11:48.373 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:11:48.373 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:48.373 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:53.375 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:11:53.375 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:11:53.376 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:53.376 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:53.376 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:53.376 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:53.379 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:53.379 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:11:53.379 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:53.379 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:11:53.379 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:11:53.380 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:11:53.380 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:11:53.380 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:11:53.380 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:53.380 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:53.380 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:11:53.380 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:11:53.380 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:11:53.380 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:53.381 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:11:53.381 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:11:53.382 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:11:53.382 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:53.382 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:53.382 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:11:53.382 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:11:53.382 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:11:53.382 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:53.383 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:11:53.383 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:11:53.383 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:11:53.383 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:53.383 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:53.383 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:11:53.383 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:11:53.383 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:11:53.383 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:53.385 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:11:53.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:11:53.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:11:53.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:11:53.385 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:11:53.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:11:53.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:11:53.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:11:53.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:11:53.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:53.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:53.385 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:11:53.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:53.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:53.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:53.385 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:11:53.386 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:11:53.386 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:11:53.386 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:53.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:53.390 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:11:53.853 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:11:53.979 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:11:53.979 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:11:53.980 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:11:53.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:11:53.982 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:53.983 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:53.983 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:53.983 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:53.983 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:53.983 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:53.983 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:53.983 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:53.983 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:11:53.983 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:11:53.983 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:11:53.984 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=132 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:11:53.984 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=132 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:11:53.984 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=132 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:11:53.984 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=132 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:11:53.984 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=132 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:11:53.984 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=132 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:11:58.985 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:11:58.985 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:11:58.985 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:58.985 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:58.985 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:58.985 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:58.988 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:11:58.988 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:11:58.988 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:58.988 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:11:58.988 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:11:58.989 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:11:58.989 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:11:58.989 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:11:58.989 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:58.989 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:11:58.989 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:11:58.989 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:11:58.989 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:11:58.989 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:58.990 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:11:58.990 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:11:58.990 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:11:58.990 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:58.990 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:11:58.991 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:11:58.991 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:11:58.991 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:11:58.991 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:58.992 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:11:58.992 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:11:58.992 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:11:58.992 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:11:58.992 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:11:58.992 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:11:58.992 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:11:58.992 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:11:58.992 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:11:58.995 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:11:58.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:11:58.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:11:58.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:11:58.995 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:11:58.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:11:58.996 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:11:58.996 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:11:58.996 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:11:58.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:58.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:58.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:58.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:11:58.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:58.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:11:58.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:58.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:11:59.001 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:11:59.463 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:11:59.508 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:11:59.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:11:59.509 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:11:59.510 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:11:59.926 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:11:59.998 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:11:59.998 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:11:59.998 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:11:59.998 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:00.389 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:12:00.851 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:12:00.999 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:00.999 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:00.999 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:00.999 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:01.314 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:12:01.776 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:12:01.999 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:01.999 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:01.999 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:01.999 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:02.239 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:12:02.519 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:12:02.519 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:12:02.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:12:02.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:12:02.519 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:12:02.519 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:12:02.519 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:12:02.519 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:12:02.701 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:12:03.000 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:03.000 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:03.000 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:03.000 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:03.164 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:12:03.626 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:12:04.000 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:04.000 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:04.000 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:04.000 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:04.089 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:12:04.552 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:12:04.689 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:12:04.689 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:12:04.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:04.690 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:04.690 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:04.690 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:04.690 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:04.691 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:04.691 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:04.691 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:04.691 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:12:04.691 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:12:04.691 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:12:04.691 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:09.693 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:12:09.693 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:12:09.693 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:09.693 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:09.693 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:09.693 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:09.697 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:09.697 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:12:09.697 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:09.697 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:12:09.697 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:12:09.698 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:12:09.698 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:12:09.698 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:12:09.698 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:09.699 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:09.699 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:12:09.699 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:12:09.699 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:12:09.699 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:09.700 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:12:09.700 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:12:09.700 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:12:09.700 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:09.700 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:09.700 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:12:09.700 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:12:09.700 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:12:09.700 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:09.701 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:12:09.701 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:12:09.701 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:12:09.701 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:09.701 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:09.701 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:12:09.701 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:12:09.701 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:12:09.701 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:09.703 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:12:09.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:12:09.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:12:09.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:12:09.703 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:12:09.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:12:09.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:12:09.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:12:09.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:12:09.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:09.703 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:12:09.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:09.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:09.703 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:09.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:09.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:09.703 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:12:09.703 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:12:09.703 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:12:09.703 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:09.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:09.708 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:12:10.172 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:12:10.215 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:12:10.215 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:12:10.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:10.216 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:12:10.222 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:12:10.222 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:12:10.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:12:10.227 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:10.227 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:10.227 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:10.227 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:10.228 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:10.228 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:10.228 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:10.228 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:10.228 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:12:10.228 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:12:10.228 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:12:15.230 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:12:15.230 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:12:15.230 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:15.230 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:15.230 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:15.230 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:15.233 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:15.234 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:12:15.234 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:15.234 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:12:15.234 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:12:15.235 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:12:15.235 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:12:15.235 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:12:15.235 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:15.235 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:15.235 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:12:15.235 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:12:15.235 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:12:15.235 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:15.236 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:12:15.236 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:12:15.236 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:12:15.236 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:15.236 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:15.236 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:12:15.236 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:12:15.236 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:12:15.236 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:15.237 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:12:15.237 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:12:15.238 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:12:15.238 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:15.238 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:15.238 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:12:15.238 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:12:15.238 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:12:15.238 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:12:15.240 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:12:15.240 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:12:15.240 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:15.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:15.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:15.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:15.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:15.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:15.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:15.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:15.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:15.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:15.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:15.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:15.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:15.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:15.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:15.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:15.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:15.245 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:12:15.712 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:12:15.755 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:12:15.755 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:12:15.755 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:12:15.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:15.762 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:12:15.762 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:12:15.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:12:15.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:15.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:15.770 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:15.770 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:15.770 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:15.770 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:15.771 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:15.771 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:15.771 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:15.771 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:15.771 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:12:15.771 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:12:15.771 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:12:20.773 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:12:20.773 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:12:20.773 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:20.773 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:20.773 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:20.773 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:20.776 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:20.776 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:12:20.776 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:20.776 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:12:20.776 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:12:20.777 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:12:20.777 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:12:20.777 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:12:20.777 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:20.777 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:20.777 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:12:20.778 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:12:20.778 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:12:20.778 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:20.779 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:12:20.779 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:12:20.779 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:12:20.779 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:20.779 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:20.779 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:12:20.779 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:12:20.779 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:12:20.779 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:20.780 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:12:20.780 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:12:20.780 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:12:20.780 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:20.780 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:20.780 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:12:20.780 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:12:20.780 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:12:20.780 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:20.782 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:12:20.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:12:20.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:12:20.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:12:20.782 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:12:20.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:12:20.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:12:20.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:20.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:12:20.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:12:20.782 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:12:20.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:20.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:20.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:20.782 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:20.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:20.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:20.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:20.782 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:12:20.782 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:12:20.782 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:12:20.783 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:20.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:20.787 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:12:21.252 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:12:21.296 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:12:21.297 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:12:21.298 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:12:21.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:21.307 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:12:21.307 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:12:21.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:12:21.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:21.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:21.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:21.315 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:21.315 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:21.315 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:21.315 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:21.315 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:21.316 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:21.316 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:21.316 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:21.316 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:12:21.316 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:12:21.316 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:12:26.317 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:12:26.317 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:12:26.317 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:26.317 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:26.317 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:26.317 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:26.321 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:26.321 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:12:26.321 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:26.321 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:12:26.321 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:12:26.322 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:12:26.322 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:12:26.322 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:12:26.322 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:26.322 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:26.322 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:12:26.322 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:12:26.322 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:12:26.323 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:26.323 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:12:26.324 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:12:26.324 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:12:26.324 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:26.324 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:26.324 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:12:26.324 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:12:26.324 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:12:26.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:26.325 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:12:26.325 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:12:26.325 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:12:26.325 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:26.325 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:26.325 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:12:26.325 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:12:26.325 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:12:26.325 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:26.327 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:12:26.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:12:26.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:12:26.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:12:26.327 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:12:26.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:12:26.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:12:26.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:26.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:12:26.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:12:26.327 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:12:26.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:26.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:26.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:12:26.328 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:12:26.328 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:12:26.328 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:26.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:26.332 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:12:26.797 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:12:26.841 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:12:26.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:26.841 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:12:26.842 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:12:26.847 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:12:26.847 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:12:26.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:12:26.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:26.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:26.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:26.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:26.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:26.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:26.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:26.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:26.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:26.857 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:26.857 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:26.857 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:26.857 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:26.858 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:26.858 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:26.858 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:12:26.858 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:12:26.858 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:12:26.858 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:26.858 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:31.860 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:12:31.860 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:12:31.860 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:31.860 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:31.860 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:31.860 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:31.865 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:31.865 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:12:31.865 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:31.865 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:12:31.865 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:12:31.866 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:12:31.866 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:12:31.866 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:12:31.866 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:31.867 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:31.867 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:12:31.867 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:12:31.867 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:12:31.867 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:31.867 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:12:31.868 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:12:31.868 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:12:31.868 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:31.868 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:31.868 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:12:31.868 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:12:31.868 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:12:31.868 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:31.869 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:12:31.869 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:12:31.869 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:12:31.869 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:31.869 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:31.869 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:12:31.869 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:12:31.869 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:12:31.869 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:31.871 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:12:31.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:12:31.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:12:31.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:12:31.871 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:12:31.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:12:31.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:12:31.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:31.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:12:31.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:12:31.871 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:12:31.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:31.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:31.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:31.871 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:31.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:31.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:31.871 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:12:31.871 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:12:31.871 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:12:31.871 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:31.872 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:31.876 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:12:32.342 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:12:32.397 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:12:32.398 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:12:32.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:32.401 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:12:32.402 [DEBUG] fake_trx.py:382 (BTS@172.18.59.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-06 03:12:32.402 [INFO] fake_trx.py:385 (BTS@172.18.59.20:5700) Artificial TRXC delay set to 200
2026-03-06 03:12:32.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-06 03:12:32.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:32.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:32.814 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:12:33.013 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:33.013 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:33.013 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:33.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:33.213 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:33.284 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:12:33.746 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:12:33.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:34.018 [DEBUG] fake_trx.py:382 (BTS@172.18.59.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-06 03:12:34.018 [INFO] fake_trx.py:385 (BTS@172.18.59.20:5700) Artificial TRXC delay set to 0
2026-03-06 03:12:34.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-06 03:12:34.018 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:34.018 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:34.018 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:34.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:34.020 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:34.020 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:34.020 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:34.020 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:34.021 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:34.021 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:34.021 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:12:34.021 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:12:34.021 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:12:34.021 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:34.021 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:39.023 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:12:39.023 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:12:39.023 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:39.023 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:39.023 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:39.023 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:39.026 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:39.026 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:12:39.026 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:39.026 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:12:39.026 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:12:39.027 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:12:39.027 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:12:39.027 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:12:39.027 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:39.027 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:39.027 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:12:39.028 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:12:39.028 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:12:39.028 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:39.029 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:12:39.029 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:12:39.029 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:12:39.029 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:39.029 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:39.029 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:12:39.029 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:12:39.029 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:12:39.029 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:39.030 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:12:39.030 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:12:39.030 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:12:39.030 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:39.030 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:39.030 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:12:39.030 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:12:39.030 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:12:39.030 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:39.032 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:12:39.032 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:12:39.032 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:12:39.032 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:12:39.032 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:12:39.032 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:12:39.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:12:39.032 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:39.032 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:12:39.032 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:12:39.032 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:12:39.032 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:39.032 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:39.032 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:39.032 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:39.032 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:39.032 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:39.032 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:39.032 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:12:39.033 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:12:39.033 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:12:39.033 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:39.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:39.037 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:12:39.503 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:12:39.545 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:12:39.546 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:12:39.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:39.546 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:12:39.547 [DEBUG] fake_trx.py:382 (BTS@172.18.59.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-06 03:12:39.547 [INFO] fake_trx.py:385 (BTS@172.18.59.20:5700) Artificial TRXC delay set to 200
2026-03-06 03:12:39.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-06 03:12:39.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:39.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:39.969 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:12:40.157 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:40.157 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:40.157 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:40.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:40.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:40.438 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:12:40.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:40.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:40.900 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:12:40.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:41.157 [DEBUG] fake_trx.py:382 (BTS@172.18.59.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-06 03:12:41.157 [INFO] fake_trx.py:385 (BTS@172.18.59.20:5700) Artificial TRXC delay set to 0
2026-03-06 03:12:41.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-06 03:12:41.158 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:41.158 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:41.158 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:41.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:41.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:41.158 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:41.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:41.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:41.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:41.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:41.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:41.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:41.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:41.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:41.160 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:41.160 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:41.160 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:41.160 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:41.161 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:41.161 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:41.161 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:12:41.161 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:12:41.161 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:12:41.161 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:41.161 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:41.161 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=467 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:12:41.161 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=467 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:12:41.161 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=467 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:12:41.161 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=467 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:12:41.161 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=467 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:12:41.161 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=467 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:12:46.162 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:12:46.162 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:12:46.162 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:46.162 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:46.162 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:46.162 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:46.166 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:46.166 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:12:46.166 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:46.166 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:12:46.166 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:12:46.167 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:12:46.167 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:12:46.167 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:12:46.167 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:46.167 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:46.167 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:12:46.168 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:12:46.168 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:12:46.168 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:46.169 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:12:46.169 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:12:46.169 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:12:46.169 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:46.169 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:46.169 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:12:46.169 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:12:46.169 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:12:46.169 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:46.170 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:12:46.170 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:12:46.170 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:12:46.170 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:46.170 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:46.170 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:12:46.170 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:12:46.170 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:12:46.170 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:46.172 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:12:46.172 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:12:46.172 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:12:46.172 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:12:46.172 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:12:46.172 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:12:46.173 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:12:46.173 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:12:46.173 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:46.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:46.177 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:12:46.640 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:12:46.685 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:12:46.686 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:12:46.686 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:12:46.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:46.692 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:12:46.692 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:12:46.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:12:46.727 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:46.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:46.731 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:46.731 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:46.731 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:46.731 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:46.732 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:46.732 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:46.732 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:12:46.732 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:12:46.732 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:12:46.732 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:46.732 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:46.732 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:12:46.732 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:12:46.732 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:12:46.732 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:12:46.732 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:12:46.732 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:12:46.732 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:12:46.733 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:12:51.734 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:12:51.734 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:12:51.734 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:51.734 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:51.734 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:51.734 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:51.737 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:51.737 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:12:51.737 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:51.737 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:12:51.737 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:12:51.738 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:12:51.738 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:12:51.738 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:12:51.738 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:51.738 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:51.739 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:12:51.739 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:12:51.739 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:12:51.739 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:51.740 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:12:51.740 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:12:51.740 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:12:51.740 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:51.740 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:51.740 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:12:51.740 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:12:51.740 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:12:51.740 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:51.741 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:12:51.741 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:12:51.741 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:12:51.741 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:51.741 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:51.741 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:12:51.741 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:12:51.741 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:12:51.741 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:51.743 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:12:51.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:12:51.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:12:51.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:12:51.743 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:12:51.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:12:51.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:12:51.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:12:51.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:12:51.744 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:12:51.744 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:12:51.744 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:51.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:51.748 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:12:52.211 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:12:52.256 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:12:52.256 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:12:52.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:52.257 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:12:52.262 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:12:52.262 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:12:52.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:12:52.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:52.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:52.269 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:52.269 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:52.269 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:52.269 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:52.270 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:52.270 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:52.270 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:12:52.270 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:12:52.270 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:12:52.270 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:52.270 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:57.272 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:12:57.272 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:12:57.272 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:57.272 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:57.272 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:57.272 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:57.275 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:12:57.275 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:12:57.275 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:57.275 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:12:57.276 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:12:57.276 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:12:57.276 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:12:57.277 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:12:57.277 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:57.277 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:12:57.277 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:12:57.277 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:12:57.277 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:12:57.277 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:57.277 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:12:57.278 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:12:57.278 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:12:57.278 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:57.278 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:12:57.278 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:12:57.278 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:12:57.278 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:12:57.278 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:57.279 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:12:57.279 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:12:57.279 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:12:57.279 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:12:57.279 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:12:57.279 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:12:57.279 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:12:57.279 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:12:57.279 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:57.281 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:12:57.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:12:57.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:12:57.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:12:57.281 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:12:57.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:12:57.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:12:57.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:57.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:12:57.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:12:57.281 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:12:57.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:57.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:57.281 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:57.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:57.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:57.281 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:12:57.281 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:12:57.281 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:12:57.282 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:57.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:12:57.286 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:12:57.749 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:12:57.795 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:12:57.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:57.796 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:12:57.796 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:12:57.803 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:12:57.803 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:12:57.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:12:57.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:12:57.804 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:12:57.804 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:12:57.804 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:12:57.804 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:12:57.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:57.840 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:12:57.840 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:12:57.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:12:57.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:12:57.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:57.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:12:57.885 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:12:57.885 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:12:57.891 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:12:57.891 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:12:57.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:12:57.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:12:57.892 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:12:57.892 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:12:57.892 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:12:57.892 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:12:57.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:12:57.933 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:12:57.933 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:12:57.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:12:57.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:12:58.211 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:12:58.284 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:58.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:58.284 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:58.284 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:58.674 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:12:59.137 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:12:59.285 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:12:59.285 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:12:59.285 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:12:59.285 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:12:59.600 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:13:00.063 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:13:00.285 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:13:00.285 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:13:00.285 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:13:00.285 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:13:00.525 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:13:00.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:00.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:00.935 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:00.935 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:00.942 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:00.942 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:00.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:00.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:00.943 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:00.943 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:00.943 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:00.943 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:00.988 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:13:00.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:00.992 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:00.992 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:00.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:00.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:01.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:01.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:01.042 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:01.042 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:01.049 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:01.049 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:01.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:01.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:01.051 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:01.051 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:01.051 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:01.051 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:01.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:01.078 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:01.078 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:01.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:01.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:01.286 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:13:01.286 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:13:01.286 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:13:01.286 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:13:01.451 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:13:01.914 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:13:02.286 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:13:02.286 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:13:02.286 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:13:02.286 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:13:02.377 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:13:02.839 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:13:03.302 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:13:03.764 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:13:04.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:04.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:04.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:04.080 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:04.087 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:04.087 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:04.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:04.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:04.088 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:04.088 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:04.088 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:04.088 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:04.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:04.136 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:04.136 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:04.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:04.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:04.226 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:13:04.689 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:13:05.152 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:13:05.615 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:13:06.077 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:13:06.540 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:13:07.002 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:13:07.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:07.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:07.138 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:07.138 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:07.145 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:07.145 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:07.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:07.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:07.146 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:07.146 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:07.146 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:07.146 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:07.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:07.182 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:07.182 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:07.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:07.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:07.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:07.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:07.217 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:07.217 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:07.224 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:07.224 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:07.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:07.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:07.225 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:07.225 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:07.225 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:07.225 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:07.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:07.232 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:07.232 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:07.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:07.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:07.464 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:13:07.928 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:13:08.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:08.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:08.127 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:08.127 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:08.134 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:08.134 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:08.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:08.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:08.135 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:08.135 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:08.135 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:08.135 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:08.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:08.160 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:13:08.160 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:13:08.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:08.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:08.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:08.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:08.225 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:08.225 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:08.225 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:13:08.231 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:08.231 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:08.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:08.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:08.232 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:08.232 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:08.232 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:08.232 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:08.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:08.252 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:13:08.252 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:13:08.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:08.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:08.390 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:13:08.853 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:13:09.315 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:13:09.778 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:13:10.241 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:13:10.703 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:13:11.166 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:13:11.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:11.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:11.255 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:11.255 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:11.255 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:13:11.263 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:11.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:11.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:11.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:11.264 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:11.264 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:11.264 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:11.264 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:11.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:11.298 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:13:11.298 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:13:11.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:11.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:11.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:11.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:11.362 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:11.362 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:11.362 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:13:11.368 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:11.368 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:11.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:11.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:11.369 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:11.369 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:11.369 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:11.369 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:11.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:11.396 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:13:11.396 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:13:11.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:11.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:11.629 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:13:12.091 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:13:12.554 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:13:13.016 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:13:13.478 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:13:13.940 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:13:14.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:14.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:14.398 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:14.398 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:14.398 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:13:14.403 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:13:14.409 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:14.409 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:14.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:14.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:14.411 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:14.411 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:14.411 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:14.411 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:14.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:14.449 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:13:14.449 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:13:14.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:14.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:14.867 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:13:15.329 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:13:15.791 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 03:13:16.254 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 03:13:16.716 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 03:13:17.179 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 03:13:17.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:17.450 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:17.451 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:17.451 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:17.451 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:13:17.457 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:17.458 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:17.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:17.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:17.459 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:17.459 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:17.459 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:17.459 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:17.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:17.502 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:13:17.502 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:13:17.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:17.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:17.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:17.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:17.579 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:17.579 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:17.579 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:13:17.586 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:17.586 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:17.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:17.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:17.587 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:17.587 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:17.587 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:17.587 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:17.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:17.594 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:13:17.594 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:13:17.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:17.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:17.641 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 03:13:18.103 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 03:13:18.566 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 03:13:18.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:18.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:18.738 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:18.738 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:18.738 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:13:18.744 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:18.744 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:18.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:18.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:18.745 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:18.745 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:18.745 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:18.745 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:18.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:18.798 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:18.799 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:18.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:18.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:19.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:19.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:19.023 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:19.023 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:19.028 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 03:13:19.029 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:19.029 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:19.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:19.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:19.030 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:19.030 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:19.030 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:19.030 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:19.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:19.071 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:19.071 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:19.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:19.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:19.490 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 03:13:19.953 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 03:13:20.415 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 03:13:20.877 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 03:13:21.340 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 03:13:21.803 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 03:13:22.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:22.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:22.072 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:22.072 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:22.078 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:22.078 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:22.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:22.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:22.079 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:22.079 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:22.079 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:22.079 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:22.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:22.126 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:22.126 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:22.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:22.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:22.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:22.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:22.259 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:22.259 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:22.265 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:22.265 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:22.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:22.265 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 03:13:22.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:22.266 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:22.266 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:22.266 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:22.266 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:22.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:22.306 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:22.306 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:22.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:22.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:22.727 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 03:13:23.189 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 03:13:23.652 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 03:13:24.114 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 03:13:24.577 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 03:13:25.040 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 03:13:25.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:25.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:25.308 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:25.308 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:25.314 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:25.314 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:25.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:25.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:25.315 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:25.315 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:25.315 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:25.315 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:25.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:25.320 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:25.320 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:25.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:25.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:25.503 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 03:13:25.965 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 03:13:26.427 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 03:13:26.891 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 03:13:27.353 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 03:13:27.816 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 03:13:28.279 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 03:13:28.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:28.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:28.321 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:28.321 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:28.327 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:28.327 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:28.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:28.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:28.328 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:28.328 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:28.328 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:28.328 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:28.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:28.366 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:28.366 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:28.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:28.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:28.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:28.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:28.498 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:28.499 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:28.504 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:28.504 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:28.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:28.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:28.505 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:28.505 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:28.505 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:28.505 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:28.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:28.509 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:28.509 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:28.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:28.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:28.741 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 03:13:29.203 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 03:13:29.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:29.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:29.238 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:29.238 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:29.244 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:29.244 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:29.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:29.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:29.245 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:29.245 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:29.245 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:29.245 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:29.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:29.294 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:13:29.294 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:13:29.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:29.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:29.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:29.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:29.353 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:29.353 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:29.353 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:13:29.358 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:29.358 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:29.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:29.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:29.359 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:29.360 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:29.360 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:29.360 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:29.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:29.386 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:13:29.386 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:13:29.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:29.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:29.666 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 03:13:30.128 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 03:13:30.591 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 03:13:31.053 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 03:13:31.516 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-06 03:13:31.978 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-06 03:13:32.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:32.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:32.388 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:32.388 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:32.388 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:13:32.394 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:32.394 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:32.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:32.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:32.395 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:32.395 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:32.395 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:32.395 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:32.441 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-06 03:13:32.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:32.446 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:13:32.446 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:13:32.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:32.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:32.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:32.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:32.830 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:32.830 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:32.830 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:13:32.836 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:32.836 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:32.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:32.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:32.837 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:32.837 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:32.837 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:32.837 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:32.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:32.857 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:13:32.857 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:13:32.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:32.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:32.903 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-06 03:13:33.366 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-06 03:13:33.828 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-06 03:13:34.291 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-06 03:13:34.753 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-06 03:13:35.216 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-06 03:13:35.678 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-06 03:13:35.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:35.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:35.858 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:35.858 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:35.858 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:13:35.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:35.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:35.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:35.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:35.866 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:35.866 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:35.866 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:35.866 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:35.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:35.908 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:13:35.908 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:13:35.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:35.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:36.141 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-06 03:13:36.603 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-06 03:13:37.066 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-06 03:13:37.529 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-06 03:13:37.993 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-06 03:13:38.456 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-06 03:13:38.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:38.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:38.910 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:38.910 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:38.910 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:13:38.917 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:38.917 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:38.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:38.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:38.918 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:38.918 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:38.918 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:38.918 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:38.919 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-06 03:13:38.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:38.922 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:13:38.922 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:13:38.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:38.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:39.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:39.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:39.295 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:39.295 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:39.295 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:13:39.301 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:39.301 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:39.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:39.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:39.302 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:39.302 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:39.302 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:39.302 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:39.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:39.337 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:13:39.337 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:13:39.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:39.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:39.381 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-06 03:13:39.844 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-06 03:13:40.306 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-06 03:13:40.769 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-06 03:13:41.231 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-06 03:13:41.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:41.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:41.682 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:41.682 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:41.682 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:13:41.686 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:13:41.686 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:13:41.686 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:13:41.686 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:13:41.687 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:13:41.687 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:13:41.687 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:13:41.687 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:13:41.687 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:13:41.687 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:13:41.687 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:13:46.689 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:13:46.689 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:13:46.689 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:13:46.689 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:13:46.689 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:13:46.689 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:13:46.694 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:13:46.694 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:13:46.694 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:13:46.694 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:13:46.694 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:13:46.696 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:13:46.696 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:13:46.696 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:13:46.696 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:13:46.696 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:13:46.696 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:13:46.696 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:13:46.696 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:13:46.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:13:46.697 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:13:46.697 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:13:46.697 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:13:46.697 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:13:46.697 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:13:46.697 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:13:46.697 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:13:46.697 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:13:46.697 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:13:46.699 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:13:46.699 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:13:46.699 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:13:46.699 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:13:46.699 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:13:46.699 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:13:46.699 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:13:46.699 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:13:46.699 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:13:46.701 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:13:46.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:13:46.701 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:13:46.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:13:46.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:13:46.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:13:46.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:13:46.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:13:46.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:13:46.701 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:13:46.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:13:46.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:13:46.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:13:46.701 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:13:46.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:13:46.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:13:46.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:13:46.701 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:13:46.701 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:13:46.702 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:13:46.702 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:13:46.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:13:46.706 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:13:47.171 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:13:47.221 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:13:47.222 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:13:47.223 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:13:47.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:47.235 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:47.235 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:47.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:47.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:47.238 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:47.238 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:47.238 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:47.238 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:47.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:47.267 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:47.267 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:47.267 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:47.267 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:47.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:47.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:47.326 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:47.326 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:47.333 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:47.333 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:47.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:47.334 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:47.334 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:47.334 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:47.334 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:47.334 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:47.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:47.355 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:13:47.355 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:13:47.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:47.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:47.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:47.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:47.446 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:47.446 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:47.446 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:13:47.451 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:47.451 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:47.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:47.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:47.452 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:47.452 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:47.452 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:47.452 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:47.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:47.498 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:47.498 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:47.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:47.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:47.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:47.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:47.561 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:47.561 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:47.567 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:47.567 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:47.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:47.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:47.570 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:47.570 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:47.570 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:47.570 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:47.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:47.591 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:13:47.591 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:13:47.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:47.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:47.635 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:13:47.704 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:13:47.704 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:13:47.706 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:13:47.710 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:13:47.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:47.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:47.714 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:47.714 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:47.714 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:13:47.716 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:13:47.716 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:13:47.717 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:13:47.717 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:13:47.717 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:13:47.717 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:13:47.717 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:13:47.717 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:13:47.717 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:13:47.717 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:13:47.717 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:13:52.719 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:13:52.720 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:13:52.720 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:13:52.720 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:13:52.720 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:13:52.720 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:13:52.723 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:13:52.724 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:13:52.724 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:13:52.724 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:13:52.724 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:13:52.725 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:13:52.725 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:13:52.725 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:13:52.725 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:13:52.725 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:13:52.725 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:13:52.725 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:13:52.725 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:13:52.725 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:13:52.726 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:13:52.726 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:13:52.726 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:13:52.726 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:13:52.727 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:13:52.727 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:13:52.727 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:13:52.727 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:13:52.727 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:13:52.728 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:13:52.728 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:13:52.728 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:13:52.728 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:13:52.728 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:13:52.728 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:13:52.728 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:13:52.728 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:13:52.728 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:13:52.731 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:13:52.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:13:52.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:13:52.731 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:13:52.731 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:13:52.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:13:52.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:13:52.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:13:52.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:13:52.731 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:13:52.731 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:13:52.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:13:52.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:13:52.731 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:13:52.731 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:13:52.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:13:52.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:13:52.731 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:13:52.731 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:13:52.731 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:13:52.731 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:13:52.731 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:13:52.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:13:52.736 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:13:53.200 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:13:53.243 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:13:53.244 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:13:53.244 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:13:53.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:53.250 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:53.250 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:53.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:53.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:53.251 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:53.251 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:53.251 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:53.251 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:53.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:53.292 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:53.292 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:53.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:53.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:53.663 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:13:53.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:53.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:53.669 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:53.669 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:53.678 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:53.679 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:53.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:53.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:53.680 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:53.680 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:53.680 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:53.681 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:53.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:53.708 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:13:53.708 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:13:53.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:53.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:53.734 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:13:53.734 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:13:53.734 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:13:53.734 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:13:54.126 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:13:54.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:54.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:54.379 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:54.379 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:54.379 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:13:54.386 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:54.387 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:54.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:54.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:54.389 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:54.389 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:54.389 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:54.389 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:54.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:54.406 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:54.406 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:54.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:54.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:54.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:54.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:54.559 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:54.559 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:54.566 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:54.567 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:54.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:13:54.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:54.568 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:13:54.568 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:13:54.568 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:13:54.568 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:13:54.589 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:13:54.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:54.592 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:13:54.592 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:13:54.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:54.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:54.734 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:13:54.734 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:13:54.734 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:13:54.734 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:13:54.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:13:54.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:13:54.979 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:13:54.979 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:13:54.979 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:13:54.981 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:13:54.981 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:13:54.981 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:13:54.981 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:13:54.982 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:13:54.982 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:13:54.982 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:13:54.982 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:13:54.982 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:13:54.982 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:13:54.982 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:13:59.984 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:13:59.984 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:13:59.984 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:13:59.984 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:13:59.984 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:13:59.984 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:13:59.989 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:13:59.989 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:13:59.989 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:13:59.989 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:13:59.989 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:13:59.990 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:13:59.990 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:13:59.990 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:13:59.990 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:13:59.990 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:13:59.990 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:13:59.990 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:13:59.991 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:13:59.991 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:13:59.992 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:13:59.992 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:13:59.992 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:13:59.992 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:13:59.992 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:13:59.992 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:13:59.992 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:13:59.992 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:13:59.992 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:13:59.995 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:13:59.995 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:13:59.995 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:13:59.995 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:13:59.995 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:13:59.995 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:13:59.995 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:13:59.995 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:13:59.995 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:13:59.998 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:13:59.999 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:13:59.999 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:13:59.999 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:13:59.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:00.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:00.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:00.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:00.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:00.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:00.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:00.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:00.004 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:14:00.467 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:14:00.512 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:14:00.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:00.572 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:14:00.572 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:14:00.579 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:00.579 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:00.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:14:00.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:00.580 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:14:00.581 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:14:00.581 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:14:00.581 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:14:00.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:00.606 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:14:00.606 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:14:00.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:00.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:00.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:00.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:00.774 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:00.774 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:00.781 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:00.781 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:00.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:14:00.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:00.782 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:14:00.782 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:14:00.782 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:14:00.782 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:14:00.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:00.794 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:14:00.794 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:14:00.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:00.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:00.931 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:14:01.002 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:14:01.002 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:14:01.002 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:14:01.002 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:14:01.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:01.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:01.070 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:01.070 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:01.070 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:14:01.077 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:01.077 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:01.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:14:01.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:01.078 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:14:01.078 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:14:01.078 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:14:01.078 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:14:01.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:01.113 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:14:01.113 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:14:01.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:01.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:01.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:01.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:01.389 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:01.389 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:01.394 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:14:01.397 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:01.397 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:01.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:14:01.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:01.398 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:14:01.398 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:14:01.398 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:14:01.398 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:14:01.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:01.436 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:14:01.436 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:14:01.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:01.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:01.858 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:14:02.003 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:14:02.003 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:14:02.003 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:14:02.003 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:14:02.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:02.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:02.242 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:02.242 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:02.242 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:14:02.245 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:14:02.245 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:14:02.245 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:14:02.245 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:14:02.246 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:14:02.246 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:14:02.246 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:14:02.246 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:14:02.246 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:14:02.246 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:14:02.246 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:14:07.249 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:14:07.249 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:14:07.249 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:14:07.249 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:14:07.249 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:14:07.249 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:14:07.253 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:14:07.254 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:14:07.254 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:14:07.254 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:14:07.254 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:14:07.256 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:14:07.256 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:14:07.256 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:14:07.256 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:14:07.256 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:14:07.256 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:14:07.256 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:14:07.256 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:14:07.256 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:14:07.258 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:14:07.258 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:14:07.259 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:14:07.259 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:14:07.259 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:14:07.259 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:14:07.259 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:14:07.259 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:14:07.259 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:14:07.261 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:14:07.261 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:14:07.261 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:14:07.261 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:14:07.261 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:14:07.261 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:14:07.262 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:14:07.262 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:14:07.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:14:07.266 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:14:07.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:14:07.266 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:14:07.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:14:07.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:14:07.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:14:07.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:14:07.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:14:07.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:14:07.266 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:14:07.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:07.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:14:07.266 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:14:07.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:14:07.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:07.266 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:14:07.266 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:14:07.266 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:14:07.266 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:14:07.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:07.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:14:07.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:07.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:07.271 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:14:07.737 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:14:07.791 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:14:07.792 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:14:07.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:07.792 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:14:07.806 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:07.806 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:07.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:14:07.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:07.810 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:14:07.810 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:14:07.810 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:14:07.810 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:14:07.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:07.834 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:14:07.834 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:14:07.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:07.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:08.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:08.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:08.004 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:08.004 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:08.018 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:08.018 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:08.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:14:08.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:08.022 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:14:08.022 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:14:08.022 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:14:08.022 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:14:08.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:08.070 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:14:08.070 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:14:08.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:08.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:08.203 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:14:08.271 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:14:08.271 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:14:08.271 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:14:08.276 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:14:08.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:08.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:08.341 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:08.341 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:08.341 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:14:08.355 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:08.355 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:08.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:14:08.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:08.358 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:14:08.358 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:14:08.358 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:14:08.358 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:14:08.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:08.387 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:14:08.387 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:14:08.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:08.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:08.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:08.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:08.660 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:08.660 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:08.668 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:14:08.673 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:08.673 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:08.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:14:08.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:08.675 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:14:08.676 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:14:08.676 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:14:08.676 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:14:08.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:08.714 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:14:08.714 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:14:08.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:08.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:09.133 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:14:09.272 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:14:09.272 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:14:09.272 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:14:09.276 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:14:09.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:09.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:09.518 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:09.518 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:09.518 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:14:09.521 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:14:09.522 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:14:09.522 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:14:09.522 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:14:09.523 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:14:09.523 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:14:09.523 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:14:09.523 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:14:09.523 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:14:09.524 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:14:09.524 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:14:09.524 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=495 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:14:09.524 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=495 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:14:09.524 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=495 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:14:09.524 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=495 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:14:09.524 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=495 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:14:09.524 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=495 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:14:14.525 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:14:14.525 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:14:14.525 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:14:14.525 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:14:14.525 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:14:14.525 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:14:14.532 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:14:14.533 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:14:14.533 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:14:14.533 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:14:14.533 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:14:14.536 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:14:14.536 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:14:14.536 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:14:14.536 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:14:14.536 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:14:14.536 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:14:14.536 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:14:14.536 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:14:14.536 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:14:14.539 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:14:14.539 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:14:14.539 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:14:14.539 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:14:14.539 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:14:14.539 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:14:14.539 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:14:14.539 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:14:14.539 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:14:14.542 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:14:14.542 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:14:14.542 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:14:14.542 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:14:14.542 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:14:14.542 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:14:14.542 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:14:14.542 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:14:14.542 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:14:14.547 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:14:14.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:14:14.547 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:14:14.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:14:14.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:14:14.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:14:14.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:14:14.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:14:14.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:14:14.547 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:14:14.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:14.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:14:14.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:14:14.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:14:14.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:14.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:14:14.547 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:14:14.547 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:14:14.547 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:14:14.547 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:14:14.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:14.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:14.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:14:14.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:14:14.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:14.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:14.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:14:14.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:14.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:14.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:14.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:14:14.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:14.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:14.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:14:14.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:14.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:14.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:14.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:14:14.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:14.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:14.549 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:14.549 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:14.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:14.549 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:14.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:14.549 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:14.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:14.549 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:14.552 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:14:15.018 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:14:15.069 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:14:15.070 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:14:15.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:15.071 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:14:15.084 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:15.084 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:15.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:14:15.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:15.088 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:14:15.088 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:14:15.088 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:14:15.088 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:14:15.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:15.113 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:14:15.113 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:14:15.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:15.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:15.483 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:14:15.551 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:14:15.552 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:14:15.552 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:14:15.553 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:14:15.949 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:14:16.414 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:14:16.552 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:14:16.552 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:14:16.552 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:14:16.553 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:14:16.879 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:14:16.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:16.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:16.924 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:16.924 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:16.940 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:16.940 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:16.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:14:16.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:16.944 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:14:16.944 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:14:16.944 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:14:16.944 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:14:16.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:16.973 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:14:16.973 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:14:16.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:16.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:17.344 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:14:17.553 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:14:17.553 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:14:17.553 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:14:17.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:14:17.809 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:14:18.274 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:14:18.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:14:18.554 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:14:18.554 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:14:18.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:14:18.739 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:14:19.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:19.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:19.065 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:19.065 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:19.065 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:14:19.078 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:19.079 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:19.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:14:19.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:19.081 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:14:19.082 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:14:19.082 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:14:19.082 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:14:19.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:19.115 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:14:19.116 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:14:19.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:19.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:19.204 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:14:19.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:14:19.554 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:14:19.554 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:14:19.556 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:14:19.670 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:14:20.135 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:14:20.600 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:14:20.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:20.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:20.634 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:20.635 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:20.648 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:20.648 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:20.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:14:20.651 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:20.651 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:14:20.652 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:14:20.652 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:14:20.652 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:14:20.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:20.693 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:14:20.693 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:14:20.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:20.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:21.065 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:14:21.531 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:14:21.996 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:14:22.461 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:14:22.925 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:14:23.393 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:14:23.861 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:14:24.328 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:14:24.793 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:14:25.259 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:14:25.726 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:14:26.192 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:14:26.657 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:14:27.123 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:14:27.587 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:14:28.052 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:14:28.516 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:14:28.979 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:14:29.443 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:14:29.906 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:14:30.369 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:14:30.831 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:14:31.295 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:14:31.759 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:14:32.222 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:14:32.685 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:14:33.149 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 03:14:33.612 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 03:14:34.076 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 03:14:34.543 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 03:14:35.007 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 03:14:35.470 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 03:14:35.934 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 03:14:36.397 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 03:14:36.861 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 03:14:37.324 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 03:14:37.788 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 03:14:38.251 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 03:14:38.713 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 03:14:39.177 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 03:14:39.639 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 03:14:40.102 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 03:14:40.564 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 03:14:40.651 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:40.651 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:40.651 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:14:40.651 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:14:40.651 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:14:40.651 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:14:40.651 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:14:40.652 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:14:40.652 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:14:40.652 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:14:40.652 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:14:40.652 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:14:40.652 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:14:40.652 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:14:40.652 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5733 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:14:40.652 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5733 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:14:40.652 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5733 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:14:40.652 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5733 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:14:40.652 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5733 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:14:40.652 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5733 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:14:45.654 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:14:45.654 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:14:45.654 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:14:45.654 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:14:45.654 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:14:45.654 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:14:45.660 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:14:45.661 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:14:45.661 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:14:45.661 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:14:45.661 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:14:45.662 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:14:45.662 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:14:45.662 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:14:45.662 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:14:45.662 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:14:45.662 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:14:45.662 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:14:45.662 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:14:45.662 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:14:45.664 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:14:45.664 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:14:45.664 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:14:45.664 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:14:45.664 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:14:45.664 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:14:45.665 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:14:45.665 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:14:45.665 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:14:45.667 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:14:45.667 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:14:45.667 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:14:45.667 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:14:45.667 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:14:45.667 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:14:45.667 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:14:45.667 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:14:45.667 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:14:45.670 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:14:45.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:14:45.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:14:45.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:14:45.670 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:14:45.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:14:45.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:14:45.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:14:45.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:14:45.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:14:45.670 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:14:45.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:45.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:14:45.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:45.670 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:14:45.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:14:45.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:45.670 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:14:45.670 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:14:45.671 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:14:45.671 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:14:45.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:14:45.675 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:14:46.139 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:14:46.240 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:14:46.240 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:14:46.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:46.241 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:14:46.248 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:46.248 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:46.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:14:46.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:46.249 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:14:46.249 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:14:46.249 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:14:46.249 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:14:46.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:46.276 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:14:46.276 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:14:46.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:46.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:46.604 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:14:46.673 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:14:46.673 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:14:46.673 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:14:46.674 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:14:47.067 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:14:47.529 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:14:47.673 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:14:47.673 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:14:47.673 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:14:47.674 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:14:47.992 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:14:48.455 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:48.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:48.504 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:48.504 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:48.510 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:48.510 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:48.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:14:48.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:48.511 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:14:48.511 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:14:48.511 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:14:48.511 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:14:48.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:48.542 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:14:48.542 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:14:48.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:48.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:48.674 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:14:48.674 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:14:48.674 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:14:48.675 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:14:48.917 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:14:49.379 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:14:49.674 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:14:49.674 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:14:49.674 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:14:49.676 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:14:49.842 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:14:50.304 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:14:50.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:50.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:50.635 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:50.636 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:50.636 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:14:50.641 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:50.641 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:50.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:14:50.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:50.642 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:14:50.643 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:14:50.643 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:14:50.643 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:14:50.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:50.674 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:14:50.674 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:14:50.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:50.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:50.675 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:14:50.675 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:14:50.675 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:14:50.676 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:14:50.767 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:14:51.276 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:14:51.742 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:14:52.214 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:14:52.686 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:14:52.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:52.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:52.729 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:52.730 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:52.746 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:14:52.746 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:14:52.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:14:52.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:52.748 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:14:52.748 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:14:52.748 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:14:52.748 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:14:52.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:14:52.785 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:14:52.785 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:14:52.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:52.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:14:53.157 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:14:53.628 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:14:54.093 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:14:54.557 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:14:55.019 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:14:55.481 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:14:55.943 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:14:56.405 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:14:56.867 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:14:57.329 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:14:57.793 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:14:58.258 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:14:58.721 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:14:59.183 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:14:59.690 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:15:00.153 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:15:00.615 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:15:01.077 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:15:01.540 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:15:02.003 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:15:02.467 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:15:02.930 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:15:03.393 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:15:03.857 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:15:04.320 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 03:15:04.782 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 03:15:05.245 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 03:15:05.707 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 03:15:06.170 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 03:15:06.633 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 03:15:07.096 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 03:15:07.558 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 03:15:08.021 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 03:15:08.484 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 03:15:08.947 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 03:15:09.409 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 03:15:09.872 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 03:15:10.335 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 03:15:10.798 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 03:15:11.261 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 03:15:11.723 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 03:15:12.186 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 03:15:12.648 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 03:15:12.748 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:12.748 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:12.748 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:15:12.749 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:15:12.749 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:15:12.749 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:15:12.749 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:15:12.749 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:15:12.749 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:15:12.749 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:15:12.749 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:15:12.749 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:15:12.749 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:15:12.749 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:15:17.752 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:15:17.752 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:15:17.752 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:15:17.752 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:15:17.752 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:15:17.752 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:15:17.758 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:15:17.759 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:15:17.759 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:15:17.759 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:15:17.759 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:15:17.760 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:15:17.761 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:15:17.761 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:15:17.761 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:15:17.761 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:15:17.761 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:15:17.761 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:15:17.761 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:15:17.761 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:15:17.763 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:15:17.763 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:15:17.763 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:15:17.763 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:15:17.763 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:15:17.763 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:15:17.763 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:15:17.763 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:15:17.763 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:15:17.765 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:15:17.765 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:15:17.765 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:15:17.765 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:15:17.765 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:15:17.765 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:15:17.765 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:15:17.765 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:15:17.765 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:15:17.768 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:15:17.768 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:15:17.768 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:15:17.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:15:17.769 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:15:17.769 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:15:17.769 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:15:17.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:15:17.769 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:15:17.769 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:15:17.769 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:15:17.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:15:17.769 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:15:17.769 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:15:17.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:15:17.769 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:15:17.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:15:17.769 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:15:17.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:15:17.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:15:17.773 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:15:18.235 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:15:18.313 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:15:18.313 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:15:18.314 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:15:18.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:18.320 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:18.320 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:18.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:15:18.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:18.321 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:18.321 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:18.321 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:15:18.321 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:15:18.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:18.326 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:18.326 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:18.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:18.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:18.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:18.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:18.491 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:18.491 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:18.498 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:18.498 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:18.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:15:18.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:18.500 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:18.500 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:18.500 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:15:18.500 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:15:18.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:18.516 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:18.516 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:18.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:18.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:18.697 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:15:18.770 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:15:18.770 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:15:18.770 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:15:18.770 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:15:19.160 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:15:19.623 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:15:19.771 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:15:19.814 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:15:19.815 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:15:19.815 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:15:20.087 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:15:20.550 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:15:20.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:20.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:20.591 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:20.591 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:20.599 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:20.599 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:20.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:15:20.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:20.600 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:20.601 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:20.601 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:15:20.601 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:15:20.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:20.638 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:20.638 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:20.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:20.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:20.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:20.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:20.807 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:20.807 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:20.814 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:20.814 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:20.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:15:20.814 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:15:20.815 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:15:20.815 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:15:20.815 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:15:20.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:20.815 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:20.815 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:20.815 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:15:20.815 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:15:20.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:20.828 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:20.828 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:20.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:20.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:21.014 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:15:21.477 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:15:21.815 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:15:21.815 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:15:21.815 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:15:21.815 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:15:21.939 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:15:22.402 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:15:22.816 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:15:22.816 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:15:22.816 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:15:22.816 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:15:22.865 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:15:22.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:22.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:22.953 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:22.953 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:22.961 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:22.961 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:22.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:15:22.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:22.962 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:22.962 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:22.962 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:15:22.962 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:15:23.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:23.002 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:15:23.002 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:15:23.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:23.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:23.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:23.272 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:23.272 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:23.272 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:23.272 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:15:23.280 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:23.280 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:23.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:15:23.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:23.281 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:23.281 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:23.281 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:15:23.281 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:15:23.328 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:15:23.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:23.332 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:15:23.332 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:15:23.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:23.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:23.791 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:15:24.253 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:15:24.717 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:15:25.179 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:15:25.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:25.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:25.553 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:25.553 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:25.553 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:15:25.559 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:25.559 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:25.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:15:25.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:25.561 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:25.561 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:25.561 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:15:25.561 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:15:25.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:25.597 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:15:25.597 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:15:25.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:25.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:25.642 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:15:25.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:25.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:25.862 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:25.862 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:25.862 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:15:25.869 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:25.869 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:25.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:15:25.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:25.870 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:25.870 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:25.870 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:15:25.870 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:15:25.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:25.919 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:15:25.919 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:15:25.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:25.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:26.105 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:15:26.567 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:15:27.030 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:15:27.495 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:15:27.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:27.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:27.915 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:27.915 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:27.915 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:15:27.922 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:27.922 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:27.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:15:27.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:27.923 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:27.923 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:27.923 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:15:27.923 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:15:27.957 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:15:28.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:28.127 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:28.127 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:28.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:28.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:28.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:28.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:28.580 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:28.580 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:28.587 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:28.587 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:28.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:15:28.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:28.588 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:28.588 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:28.588 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:15:28.588 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:15:28.591 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:15:28.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:28.775 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:28.775 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:28.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:28.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:29.054 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:15:29.517 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:15:29.980 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:15:30.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:30.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:30.416 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:30.416 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:30.423 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:30.423 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:30.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:15:30.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:30.424 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:30.424 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:30.424 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:15:30.424 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:15:30.444 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:15:30.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:30.448 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:30.448 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:30.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:30.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:30.906 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:15:31.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:31.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:31.058 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:31.058 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:31.065 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:31.065 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:31.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:15:31.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:31.066 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:31.066 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:31.066 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:15:31.066 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:15:31.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:31.087 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:31.087 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:31.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:31.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:31.369 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:15:31.832 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:15:32.295 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:15:32.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:32.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:32.729 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:32.729 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:32.735 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:32.735 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:32.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:15:32.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:32.736 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:32.736 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:32.736 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:15:32.736 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:15:32.758 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:15:32.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:32.762 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:15:32.762 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:15:32.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:32.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:33.220 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:15:33.683 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:15:33.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:33.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:33.999 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:33.999 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:33.999 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:15:34.006 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:34.006 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:34.006 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:15:34.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:34.007 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:34.007 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:34.007 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:15:34.007 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:15:34.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:34.055 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:15:34.055 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:15:34.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:34.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:34.146 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:15:34.609 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:15:35.072 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:15:35.535 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:15:35.998 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:15:36.461 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 03:15:36.924 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 03:15:37.386 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 03:15:37.850 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 03:15:38.312 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 03:15:38.775 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 03:15:39.238 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 03:15:39.701 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 03:15:40.164 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 03:15:40.628 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 03:15:41.091 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 03:15:41.554 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 03:15:42.017 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 03:15:42.480 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 03:15:42.942 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 03:15:43.405 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 03:15:43.868 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 03:15:44.330 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 03:15:44.793 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 03:15:45.257 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 03:15:45.720 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 03:15:46.182 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 03:15:46.645 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 03:15:47.108 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 03:15:47.571 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 03:15:48.035 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 03:15:48.497 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 03:15:48.960 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 03:15:49.422 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 03:15:49.885 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 03:15:50.347 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 03:15:50.810 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 03:15:51.272 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 03:15:51.735 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 03:15:52.198 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-06 03:15:52.661 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-06 03:15:53.124 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-06 03:15:53.586 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-06 03:15:54.007 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:54.007 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:54.007 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:15:54.008 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:15:54.008 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:15:54.008 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:15:54.008 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:15:54.009 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:15:54.009 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:15:54.009 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:15:54.009 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:15:54.009 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:15:54.009 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:15:54.009 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:15:54.009 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7948 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:15:54.009 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7948 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:15:54.009 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7948 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:15:54.009 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7948 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:15:54.009 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7948 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:15:54.009 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=7948 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:15:59.011 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:15:59.011 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:15:59.011 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:15:59.011 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:15:59.011 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:15:59.011 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:15:59.014 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:15:59.014 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:15:59.014 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:15:59.014 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:15:59.014 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:15:59.015 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:15:59.015 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:15:59.015 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:15:59.015 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:15:59.015 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:15:59.015 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:15:59.016 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:15:59.016 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:15:59.016 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:15:59.017 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:15:59.017 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:15:59.017 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:15:59.017 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:15:59.017 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:15:59.017 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:15:59.017 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:15:59.017 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:15:59.017 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:15:59.018 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:15:59.018 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:15:59.018 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:15:59.018 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:15:59.018 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:15:59.018 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:15:59.018 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:15:59.018 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:15:59.018 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:15:59.020 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:15:59.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:15:59.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:15:59.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:15:59.020 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:15:59.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:15:59.021 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:15:59.021 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:15:59.021 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:15:59.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:15:59.026 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:15:59.488 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:15:59.534 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:15:59.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:59.534 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:15:59.535 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:15:59.540 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:59.540 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:59.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:15:59.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:59.542 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:59.542 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:59.542 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:15:59.542 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:15:59.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:59.579 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:59.579 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:59.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:59.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:59.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:59.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:59.642 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:59.642 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:59.648 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:59.648 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:59.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:15:59.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:59.649 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:59.649 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:59.649 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:15:59.649 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:15:59.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:59.671 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:59.671 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:59.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:59.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:59.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:59.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:59.720 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:59.720 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:59.727 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:59.727 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:59.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:15:59.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:59.728 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:59.728 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:59.728 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:15:59.728 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:15:59.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:59.768 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:15:59.768 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:15:59.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:59.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:59.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:59.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:59.841 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:59.841 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:59.841 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:15:59.848 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:59.848 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:59.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:15:59.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:59.849 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:59.849 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:59.849 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:15:59.849 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:15:59.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:59.860 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:15:59.860 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:15:59.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:59.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:59.950 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:15:59.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:59.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:59.952 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:59.952 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:59.952 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:15:59.959 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:15:59.959 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:15:59.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:15:59.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:59.960 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:59.960 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:59.960 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:15:59.960 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:15:59.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:15:59.994 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:15:59.994 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:15:59.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:15:59.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:00.023 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:00.023 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:00.024 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:00.024 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:00.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:00.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:00.103 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:00.103 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:00.109 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:00.109 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:00.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:00.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:00.110 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:00.110 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:00.111 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:00.111 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:00.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:00.133 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:00.133 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:00.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:00.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:00.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:00.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:00.339 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:00.339 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:00.346 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:00.346 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:00.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:00.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:00.347 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:00.347 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:00.347 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:00.347 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:00.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:00.368 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:16:00.368 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:16:00.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:00.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:00.413 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:16:00.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:00.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:00.491 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:00.491 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:00.491 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:16:00.498 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:00.498 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:00.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:00.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:00.499 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:00.499 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:00.499 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:00.499 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:00.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:00.548 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:16:00.548 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:16:00.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:00.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:00.727 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:00.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:00.729 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:00.729 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:00.729 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:16:00.732 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:00.732 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:00.732 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:00.732 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:00.733 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:16:00.733 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:16:00.733 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:16:00.733 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:16:00.733 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:16:00.733 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:16:00.733 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:16:05.734 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:16:05.734 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:16:05.734 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:16:05.734 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:16:05.734 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:16:05.735 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:16:05.738 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:16:05.739 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:16:05.739 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:05.739 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:16:05.739 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:16:05.740 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:16:05.740 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:16:05.740 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:16:05.740 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:05.740 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:16:05.740 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:16:05.740 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:16:05.740 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:16:05.740 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:05.741 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:16:05.741 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:16:05.741 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:16:05.741 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:05.741 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:16:05.741 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:16:05.741 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:16:05.741 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:16:05.742 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:05.743 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:16:05.743 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:16:05.743 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:16:05.743 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:05.743 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:16:05.743 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:16:05.743 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:16:05.743 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:16:05.743 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:05.745 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:16:05.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:16:05.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:16:05.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:16:05.745 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:16:05.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:16:05.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:16:05.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:16:05.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:05.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:16:05.745 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:16:05.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:05.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:05.745 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:05.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:05.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:05.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:05.745 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:16:05.745 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:16:05.745 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:16:05.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:05.745 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:16:05.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:05.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:05.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:16:05.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:05.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:05.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:05.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:05.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:05.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:05.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:05.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:05.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:05.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:05.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:05.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:05.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:05.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:05.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:05.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:05.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:05.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:05.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:05.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:05.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:05.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:05.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:05.750 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:16:06.214 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:16:06.257 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:16:06.257 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:16:06.258 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:16:06.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:06.263 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:06.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:06.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:06.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:06.264 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:06.265 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:06.265 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:06.265 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:06.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:06.306 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:06.306 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:06.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:06.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:06.676 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:16:06.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:06.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:06.683 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:06.683 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:06.688 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:06.688 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:06.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:06.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:06.690 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:06.690 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:06.690 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:06.690 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:06.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:06.720 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:06.720 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:06.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:06.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:06.748 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:06.748 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:06.748 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:06.748 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:07.139 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:16:07.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:07.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:07.152 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:07.152 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:07.159 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:07.159 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:07.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:07.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:07.161 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:07.161 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:07.161 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:07.161 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:07.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:07.182 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:16:07.182 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:16:07.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:07.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:07.601 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:16:07.748 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:07.748 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:07.748 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:07.748 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:07.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:07.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:07.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:07.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:07.865 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:16:07.873 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:07.873 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:07.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:07.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:07.875 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:07.875 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:07.875 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:07.875 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:07.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:07.880 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:16:07.880 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:16:07.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:07.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:08.065 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:16:08.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:08.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:08.368 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:08.368 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:08.368 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:16:08.374 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:08.374 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:08.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:08.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:08.375 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:08.375 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:08.375 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:08.376 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:08.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:08.391 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:08.391 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:08.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:08.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:08.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:08.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:08.500 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:08.500 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:08.507 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:08.507 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:08.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:08.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:08.509 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:08.509 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:08.509 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:08.509 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:08.528 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:16:08.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:08.531 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:08.531 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:08.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:08.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:08.749 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:08.749 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:08.749 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:08.749 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:08.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:08.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:08.962 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:08.962 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:08.968 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:08.968 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:08.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:08.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:08.969 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:08.969 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:08.969 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:08.969 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:08.990 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:16:08.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:08.994 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:16:08.994 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:16:08.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:08.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:09.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:09.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:09.378 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:09.378 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:09.378 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:16:09.385 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:09.385 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:09.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:09.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:09.386 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:09.386 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:09.386 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:09.386 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:09.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:09.406 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:16:09.406 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:16:09.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:09.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:09.453 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:16:09.749 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:09.749 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:09.749 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:09.749 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:09.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:09.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:09.839 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:09.839 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:09.839 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:16:09.841 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:09.841 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:09.841 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:09.841 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:09.841 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:16:09.842 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:16:09.842 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:16:09.842 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:16:09.842 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:16:09.842 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:16:09.842 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:16:09.842 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=903 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:16:09.842 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=903 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:16:09.842 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=903 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:16:09.842 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=903 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:16:09.842 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=903 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:16:09.842 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=903 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:16:14.843 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:16:14.843 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:16:14.843 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:16:14.843 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:16:14.843 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:16:14.843 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:16:14.846 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:16:14.847 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:16:14.847 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:14.847 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:16:14.847 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:16:14.848 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:16:14.848 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:16:14.848 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:16:14.848 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:14.848 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:16:14.848 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:16:14.848 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:16:14.848 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:16:14.848 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:14.849 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:16:14.849 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:16:14.849 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:16:14.849 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:14.849 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:16:14.849 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:16:14.849 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:16:14.849 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:16:14.849 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:14.851 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:16:14.851 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:16:14.851 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:16:14.851 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:14.851 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:16:14.851 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:16:14.851 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:16:14.851 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:16:14.851 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:16:14.853 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:16:14.853 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:16:14.853 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:14.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:14.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:14.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:14.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:14.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:14.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:14.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:14.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:14.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:14.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:14.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:14.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:14.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:14.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:14.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:14.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:14.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:14.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:14.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:14.858 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:16:15.320 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:16:15.365 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:16:15.365 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:16:15.366 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:16:15.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:15.372 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:15.372 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:15.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:15.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:15.373 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:15.373 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:15.373 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:15.373 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:15.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:15.412 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:15.412 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:15.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:15.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:15.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:15.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:15.456 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:15.456 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:15.462 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:15.462 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:15.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:15.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:15.463 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:15.463 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:15.463 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:15.463 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:15.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:15.506 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:15.506 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:15.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:15.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:15.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:15.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:15.554 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:15.554 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:15.562 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:15.562 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:15.562 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:15.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:15.563 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:15.563 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:15.563 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:15.563 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:15.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:15.604 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:16:15.604 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:16:15.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:15.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:15.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:15.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:15.697 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:15.697 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:15.697 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:16:15.703 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:15.703 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:15.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:15.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:15.704 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:15.704 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:15.704 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:15.704 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:15.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:15.741 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:16:15.741 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:16:15.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:15.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:15.783 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:16:15.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:15.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:15.807 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:15.807 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:15.807 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:16:15.813 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:15.813 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:15.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:15.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:15.814 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:15.814 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:15.814 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:15.814 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:15.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:15.827 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:15.827 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:15.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:15.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:15.855 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:15.855 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:15.855 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:15.856 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:16.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:16.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:16.006 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:16.006 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:16.012 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:16.013 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:16.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:16.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:16.014 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:16.014 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:16.014 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:16.014 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:16.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:16.062 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:16.062 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:16.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:16.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:16.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:16.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:16.241 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:16.241 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:16.245 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:16:16.247 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:16.247 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:16.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:16.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:16.248 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:16.248 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:16.248 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:16.248 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:16.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:16.288 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:16:16.288 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:16:16.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:16.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:16.708 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:16:16.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:16.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:16.855 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:16.855 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:16.855 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:16:16.856 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:16.856 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:16.856 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:16.856 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:16.861 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:16.861 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:16.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:16.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:16.863 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:16.863 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:16.863 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:16.863 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:16.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:16.889 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:16:16.889 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:16:16.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:16.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:17.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:17.090 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:17.090 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:17.090 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:17.090 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:16:17.093 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:17.093 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:17.093 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:17.093 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:17.093 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:16:17.094 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:16:17.094 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:16:17.094 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:16:17.094 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:16:17.094 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:16:17.094 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:16:22.095 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:16:22.095 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:16:22.095 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:16:22.095 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:16:22.095 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:16:22.095 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:16:22.098 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:16:22.098 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:16:22.098 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:22.099 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:16:22.099 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:16:22.100 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:16:22.100 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:16:22.100 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:16:22.100 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:22.100 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:16:22.100 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:16:22.100 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:16:22.100 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:16:22.100 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:22.101 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:16:22.101 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:16:22.101 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:16:22.101 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:22.101 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:16:22.101 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:16:22.101 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:16:22.101 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:16:22.101 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:22.103 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:16:22.103 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:16:22.103 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:16:22.103 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:22.103 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:16:22.103 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:16:22.103 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:16:22.103 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:16:22.103 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:16:22.107 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:16:22.107 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:16:22.107 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:22.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:22.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:22.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:22.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:22.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:22.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:22.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:22.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:22.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:22.112 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:16:22.575 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:16:22.621 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:16:22.622 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:16:22.622 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:16:22.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:22.629 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:22.629 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:22.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:22.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:22.630 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:22.630 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:22.630 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:22.630 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:22.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:22.668 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:22.668 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:22.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:22.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:23.038 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:16:23.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:23.110 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:23.110 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:23.110 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:23.501 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:16:23.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:23.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:23.515 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:23.515 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:23.524 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:23.524 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:23.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:23.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:23.527 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:23.527 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:23.527 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:23.527 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:23.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:23.544 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:23.544 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:23.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:23.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:23.964 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:16:24.110 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:24.111 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:24.111 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:24.111 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:24.427 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:16:24.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:24.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:24.461 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:24.461 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:24.468 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:24.468 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:24.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:24.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:24.469 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:24.469 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:24.469 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:24.469 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:24.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:24.518 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:16:24.518 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:16:24.518 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:24.518 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:24.889 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:16:25.110 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:25.112 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:25.112 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:25.112 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:25.352 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:16:25.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:25.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:25.644 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:25.644 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:25.644 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:16:25.654 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:25.654 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:25.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:25.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:25.657 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:25.657 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:25.657 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:25.657 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:25.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:25.677 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:16:25.677 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:16:25.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:25.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:25.815 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:16:26.111 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:26.112 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:26.112 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:26.112 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:26.278 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:16:26.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:26.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:26.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:26.589 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:26.589 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:16:26.599 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:26.599 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:26.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:26.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:26.601 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:26.601 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:26.601 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:26.601 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:26.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:26.650 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:26.650 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:26.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:26.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:26.740 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:16:27.112 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:27.112 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:27.112 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:27.112 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:27.203 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:16:27.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:27.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:27.235 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:27.235 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:27.242 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:27.242 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:27.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:27.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:27.244 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:27.244 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:27.244 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:27.244 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:27.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:27.292 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:27.292 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:27.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:27.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:27.666 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:16:28.129 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:16:28.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:28.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:28.350 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:28.350 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:28.357 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:28.357 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:28.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:28.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:28.358 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:28.358 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:28.358 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:28.358 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:28.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:28.411 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:16:28.411 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:16:28.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:28.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:28.810 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:16:29.273 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:16:29.736 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:16:30.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:30.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:30.185 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:30.185 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:30.185 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:16:30.196 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:30.196 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:30.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:30.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:30.198 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:30.198 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:30.199 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:30.199 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:30.199 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:16:30.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:30.205 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:16:30.205 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:16:30.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:30.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:30.662 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:16:31.125 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:16:31.589 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:16:32.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:32.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:32.040 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:32.040 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:32.040 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:16:32.044 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:32.044 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:32.044 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:32.044 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:32.045 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:16:32.045 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:16:32.045 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:16:32.045 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:16:32.045 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:16:32.045 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:16:32.045 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:16:37.046 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:16:37.046 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:16:37.046 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:16:37.046 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:16:37.046 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:16:37.046 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:16:37.052 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:16:37.052 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:16:37.052 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:37.052 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:16:37.052 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:16:37.053 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:16:37.053 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:16:37.053 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:16:37.053 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:37.053 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:16:37.053 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:16:37.053 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:16:37.053 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:16:37.053 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:37.054 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:16:37.054 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:16:37.054 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:16:37.054 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:37.055 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:16:37.055 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:16:37.055 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:16:37.055 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:16:37.055 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:37.056 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:16:37.056 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:16:37.056 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:16:37.056 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:37.056 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:16:37.056 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:16:37.056 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:16:37.056 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:16:37.056 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:16:37.058 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:16:37.058 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:16:37.058 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:37.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:37.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:37.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:37.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:37.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:37.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:37.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:37.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:37.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:37.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:37.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:37.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:37.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:37.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:37.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:37.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:37.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:37.063 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:16:37.527 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:16:37.576 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:16:37.576 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:16:37.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:37.577 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:16:37.583 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:37.583 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:37.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:37.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:37.584 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:37.584 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:37.584 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:37.584 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:37.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:37.619 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:37.620 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:37.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:37.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:37.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:37.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:37.723 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:37.723 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:37.730 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:37.730 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:37.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:37.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:37.731 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:37.731 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:37.731 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:37.731 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:37.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:37.762 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:16:37.762 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:16:37.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:37.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:37.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:37.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:37.904 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:37.904 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:37.904 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:16:37.909 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:37.910 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:37.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:37.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:37.911 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:37.911 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:37.911 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:37.911 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:37.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:37.948 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:37.948 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:37.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:37.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:37.991 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:16:38.061 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:38.062 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:38.063 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:38.066 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:38.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:38.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:38.213 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:38.213 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:38.220 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:38.220 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:38.220 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:38.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:38.221 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:38.221 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:38.221 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:38.221 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:38.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:38.271 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:16:38.271 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:16:38.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:38.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:38.454 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:16:38.917 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:16:39.061 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:39.062 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:39.063 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:39.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:39.067 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:39.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:39.068 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:39.068 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:39.068 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:16:39.071 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:39.071 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:39.071 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:39.071 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:39.072 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:16:39.072 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:16:39.072 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:16:39.072 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:16:39.072 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:16:39.072 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:16:39.072 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:16:44.075 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:16:44.075 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:16:44.075 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:16:44.075 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:16:44.075 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:16:44.075 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:16:44.081 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:16:44.082 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:16:44.082 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:44.082 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:16:44.082 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:16:44.084 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:16:44.084 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:16:44.084 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:16:44.084 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:44.084 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:16:44.084 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:16:44.085 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:16:44.085 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:16:44.085 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:44.087 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:16:44.087 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:16:44.087 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:16:44.087 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:44.088 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:16:44.088 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:16:44.088 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:16:44.088 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:16:44.088 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:44.090 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:16:44.091 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:16:44.091 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:16:44.091 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:44.091 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:16:44.091 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:16:44.091 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:16:44.091 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:16:44.091 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:44.095 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:16:44.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:16:44.095 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:16:44.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:16:44.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:16:44.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:16:44.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:16:44.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:16:44.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:16:44.095 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:16:44.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:44.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:44.095 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:44.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:44.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:44.095 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:16:44.096 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:16:44.096 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:16:44.096 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:16:44.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:44.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:44.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:44.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:16:44.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:44.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:44.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:44.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:44.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:44.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:44.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:44.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:44.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:44.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:44.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:44.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:44.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:44.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:44.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:44.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:44.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:44.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:44.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:44.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:44.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:44.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:44.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:44.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:44.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:44.100 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:16:44.565 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:16:44.616 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:16:44.617 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:16:44.618 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:16:44.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:44.627 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:44.628 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:44.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:44.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:44.629 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:44.629 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:44.629 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:44.629 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:44.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:44.661 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:44.661 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:44.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:44.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:44.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:44.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:44.763 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:44.764 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:44.775 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:44.775 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:44.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:44.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:44.778 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:44.778 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:44.778 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:44.778 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:44.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:44.804 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:16:44.804 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:16:44.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:44.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:44.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:44.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:44.943 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:44.943 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:44.943 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:16:44.954 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:44.954 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:44.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:44.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:44.957 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:44.957 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:44.957 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:44.957 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:44.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:44.988 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:44.988 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:44.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:44.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:45.028 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:16:45.099 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:45.099 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:45.100 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:45.102 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:45.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:45.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:45.252 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:45.252 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:45.264 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:45.264 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:45.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:45.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:45.266 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:45.266 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:45.266 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:45.266 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:45.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:45.311 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:16:45.311 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:16:45.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:45.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:45.492 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:16:45.955 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:16:46.099 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:46.099 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:46.101 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:46.102 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:46.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:46.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:46.106 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:46.106 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:46.106 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:16:46.110 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:46.110 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:46.110 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:46.110 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:46.111 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:16:46.111 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:16:46.111 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:16:46.111 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:16:46.112 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:16:46.112 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:16:46.112 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:16:46.112 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=444 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:16:46.112 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=444 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:16:46.112 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=444 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:16:46.112 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=444 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:16:46.112 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=444 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:16:46.112 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=444 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:16:51.112 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:16:51.112 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:16:51.112 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:16:51.112 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:16:51.112 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:16:51.112 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:16:51.117 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:16:51.117 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:16:51.117 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:51.117 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:16:51.117 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:16:51.119 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:16:51.119 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:16:51.119 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:16:51.119 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:51.119 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:16:51.119 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:16:51.119 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:16:51.119 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:16:51.119 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:51.120 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:16:51.120 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:16:51.120 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:16:51.120 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:51.120 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:16:51.120 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:16:51.121 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:16:51.121 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:16:51.121 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:51.123 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:16:51.123 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:16:51.123 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:16:51.123 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:51.123 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:16:51.123 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:16:51.123 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:16:51.123 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:16:51.123 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:51.127 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:16:51.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:16:51.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:16:51.127 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:16:51.127 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:16:51.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:16:51.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:16:51.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:16:51.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:51.127 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:16:51.127 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:16:51.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:51.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:51.127 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:51.127 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:51.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:51.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:51.127 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:16:51.127 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:16:51.127 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:16:51.127 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:16:51.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:51.127 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:51.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:51.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:16:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:51.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:51.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:51.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:51.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:51.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:51.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:51.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:51.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:51.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:51.132 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:16:51.595 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:16:51.646 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:16:51.647 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:16:51.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:51.648 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:16:51.655 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:51.655 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:51.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:51.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:51.657 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:51.657 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:51.657 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:51.657 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:51.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:51.688 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:51.689 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:51.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:51.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:51.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:51.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:51.794 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:51.794 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:51.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:51.801 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:51.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:51.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:51.802 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:51.803 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:51.803 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:51.803 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:51.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:51.833 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:16:51.833 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:16:51.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:51.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:51.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:51.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:51.973 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:51.973 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:51.973 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:16:51.980 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:51.980 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:51.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:51.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:51.981 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:51.981 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:51.981 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:51.982 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:52.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:52.016 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:52.016 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:52.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:52.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:52.059 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:16:52.131 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:52.131 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:52.131 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:52.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:52.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:52.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:52.282 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:52.282 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:52.289 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:52.289 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:52.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:52.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:52.290 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:52.290 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:52.290 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:52.290 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:52.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:52.341 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:16:52.341 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:16:52.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:52.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:52.521 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:16:52.984 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:16:53.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:53.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:53.132 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:53.132 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:53.132 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:53.132 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:53.132 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:53.132 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:16:53.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:53.135 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:53.135 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:53.135 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:53.135 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:53.136 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:16:53.136 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:16:53.136 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:16:53.136 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:16:53.136 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:16:53.136 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:16:53.136 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:16:58.138 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:16:58.138 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:16:58.138 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:16:58.138 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:16:58.139 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:16:58.139 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:16:58.143 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:16:58.144 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:16:58.144 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:58.144 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:16:58.144 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:16:58.146 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:16:58.146 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:16:58.146 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:16:58.146 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:58.146 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:16:58.146 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:16:58.146 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:16:58.146 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:16:58.147 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:58.148 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:16:58.148 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:16:58.148 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:16:58.148 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:58.148 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:16:58.148 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:16:58.148 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:16:58.148 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:16:58.148 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:58.150 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:16:58.150 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:16:58.150 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:16:58.150 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:16:58.150 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:16:58.150 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:16:58.150 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:16:58.150 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:16:58.150 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:58.152 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:16:58.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:16:58.152 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:16:58.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:16:58.153 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:16:58.153 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:16:58.153 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:58.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:16:58.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:16:58.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:58.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:16:58.158 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:16:58.620 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:16:58.671 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:16:58.672 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:16:58.672 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:16:58.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:58.678 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:58.678 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:58.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:58.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:58.679 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:58.679 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:58.679 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:58.679 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:58.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:58.712 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:58.712 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:58.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:58.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:58.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:58.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:58.816 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:58.816 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:58.822 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:58.822 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:58.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:58.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:58.823 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:58.823 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:58.823 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:58.823 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:58.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:58.854 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:16:58.854 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:16:58.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:58.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:58.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:58.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:58.996 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:58.996 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:58.996 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:16:59.002 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:59.002 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:59.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:59.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:59.003 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:59.004 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:59.004 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:59.004 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:59.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:59.039 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:59.039 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:59.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:59.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:59.083 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:16:59.158 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:16:59.158 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:16:59.159 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:16:59.162 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:16:59.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:59.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:59.305 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:59.305 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:59.425 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:16:59.425 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:16:59.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:16:59.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:59.426 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:16:59.426 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:16:59.426 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:16:59.427 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:16:59.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:16:59.455 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:16:59.455 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:16:59.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:59.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:16:59.546 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:17:00.120 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:17:00.158 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:00.187 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:00.187 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:00.187 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:00.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:00.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:00.271 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:00.271 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:00.271 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:17:00.273 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:00.273 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:00.273 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:00.273 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:00.273 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:00.273 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:00.273 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:00.273 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:00.273 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:17:00.273 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:17:00.274 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:17:05.276 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:17:05.276 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:17:05.276 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:05.276 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:05.276 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:05.276 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:05.279 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:05.279 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:17:05.279 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:05.279 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:17:05.279 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:17:05.281 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:17:05.281 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:17:05.281 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:17:05.281 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:05.281 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:05.281 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:17:05.281 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:17:05.281 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:17:05.281 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:05.282 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:17:05.282 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:17:05.282 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:17:05.282 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:05.282 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:05.282 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:17:05.282 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:17:05.282 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:17:05.282 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:05.283 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:17:05.283 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:17:05.283 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:17:05.283 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:05.284 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:05.284 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:17:05.284 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:17:05.284 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:17:05.284 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:17:05.286 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:17:05.286 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:17:05.286 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:05.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:05.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:05.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:05.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:05.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:05.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:05.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:05.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:05.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:05.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:05.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:05.291 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:17:05.753 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:17:05.801 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:17:05.802 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:17:05.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:05.803 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:17:05.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:05.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:05.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:17:05.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:05.810 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:17:05.810 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:17:05.810 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:17:05.810 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:17:05.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:05.845 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:17:05.845 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:17:05.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:05.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:06.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:06.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:06.148 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:06.148 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:06.154 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:06.154 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:06.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:17:06.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:06.156 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:17:06.156 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:17:06.156 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:17:06.156 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:17:06.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:06.172 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:17:06.172 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:17:06.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:06.173 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:06.216 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:17:06.288 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:06.289 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:06.289 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:06.289 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:06.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:06.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:06.660 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:06.660 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:06.660 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:17:06.666 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:06.666 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:06.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:17:06.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:06.667 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:17:06.667 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:17:06.667 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:17:06.667 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:17:06.678 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:17:06.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:06.681 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:17:06.681 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:17:06.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:06.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:07.141 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:17:07.289 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:07.289 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:07.289 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:07.289 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:07.603 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:17:07.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:07.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:07.754 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:07.754 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:07.760 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:07.760 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:07.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:17:07.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:07.761 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:17:07.761 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:17:07.761 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:17:07.761 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:17:07.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:07.783 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:17:07.783 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:17:07.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:07.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:08.066 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:17:08.289 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:08.289 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:08.289 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:08.289 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:08.528 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:17:08.991 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:17:09.290 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:09.290 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:09.290 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:09.290 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:09.454 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:17:09.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:09.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:09.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:09.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:09.766 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:17:09.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:09.768 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:09.768 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:09.768 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:09.769 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:09.769 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:17:09.769 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:17:09.769 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:17:09.769 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:09.769 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:09.769 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:09.769 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=989 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:17:09.769 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=989 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:17:09.769 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=989 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:17:09.770 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=989 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:17:09.770 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=989 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:17:09.770 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=989 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:17:14.771 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:17:14.771 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:17:14.771 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:14.771 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:14.771 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:14.771 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:14.774 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:14.775 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:17:14.775 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:14.775 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:17:14.775 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:17:14.776 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:17:14.776 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:17:14.776 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:17:14.776 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:14.776 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:14.776 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:17:14.776 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:17:14.776 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:17:14.776 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:14.777 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:17:14.777 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:17:14.777 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:17:14.777 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:14.777 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:14.777 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:17:14.777 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:17:14.777 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:17:14.777 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:14.778 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:17:14.778 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:17:14.778 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:17:14.778 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:14.778 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:14.778 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:17:14.778 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:17:14.778 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:17:14.778 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:14.780 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:17:14.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:17:14.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:17:14.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:17:14.780 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:17:14.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:17:14.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:17:14.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:17:14.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:14.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:17:14.780 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:17:14.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:14.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:14.780 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:14.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:14.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:14.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:14.780 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:17:14.780 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:17:14.780 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:17:14.781 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:14.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:14.785 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:17:15.247 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:17:15.292 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:17:15.292 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:17:15.293 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:17:15.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:15.298 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:15.298 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:15.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:17:15.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:15.300 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:17:15.300 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:17:15.300 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:17:15.300 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:17:15.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:15.340 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:17:15.340 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:17:15.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:15.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:15.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:15.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:15.642 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:15.642 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:15.648 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:15.648 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:15.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:17:15.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:15.650 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:17:15.650 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:17:15.650 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:17:15.650 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:17:15.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:15.666 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:17:15.666 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:17:15.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:15.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:15.710 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:17:15.782 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:15.782 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:15.782 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:15.783 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:16.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:16.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:16.155 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:16.155 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:16.155 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:17:16.161 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:16.161 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:16.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:17:16.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:16.162 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:17:16.162 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:17:16.162 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:17:16.162 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:17:16.173 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:17:16.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:16.176 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:17:16.176 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:17:16.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:16.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:16.635 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:17:16.783 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:16.783 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:16.783 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:16.783 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:17.101 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:17:17.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:17.253 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:17.253 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:17.253 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:17.259 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:17.259 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:17.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:17:17.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:17.261 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:17:17.261 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:17:17.261 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:17:17.261 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:17:17.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:17.282 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:17:17.282 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:17:17.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:17.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:17.564 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:17:17.784 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:17.784 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:17.784 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:17.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:18.028 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:17:18.491 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:17:18.784 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:18.784 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:18.784 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:18.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:18.954 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:17:19.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:19.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:19.265 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:19.265 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:19.265 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:17:19.267 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:19.267 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:19.267 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:19.267 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:19.268 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:19.268 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:19.268 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:19.268 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:19.268 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:17:19.268 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:17:19.268 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:17:19.268 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=989 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:17:19.268 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=989 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:17:19.268 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=989 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:17:19.268 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=989 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:17:19.268 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=989 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:17:19.268 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=989 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:17:24.270 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:17:24.270 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:17:24.270 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:24.270 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:24.270 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:24.270 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:24.273 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:24.273 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:17:24.273 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:24.273 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:17:24.273 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:17:24.276 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:17:24.276 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:17:24.276 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:17:24.276 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:24.276 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:17:24.276 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:24.276 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:17:24.276 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:17:24.276 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:24.277 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:17:24.277 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:17:24.277 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:17:24.278 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:24.278 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:24.278 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:17:24.278 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:17:24.278 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:17:24.278 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:24.279 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:17:24.279 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:17:24.279 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:17:24.279 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:24.279 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:24.279 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:17:24.279 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:17:24.279 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:17:24.279 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:17:24.281 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:17:24.281 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:17:24.281 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:24.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:24.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:24.282 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:24.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:24.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:24.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:24.282 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:24.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:24.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:24.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:24.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:24.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:24.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:24.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:24.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:24.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:24.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:24.286 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:17:24.751 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:17:24.795 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:17:24.795 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:17:24.796 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:17:24.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:24.803 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:24.803 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:24.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:17:24.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:24.805 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:17:24.805 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:17:24.806 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:17:24.806 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:17:24.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:24.845 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:17:24.845 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:17:24.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:24.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:25.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:25.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:25.147 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:25.147 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:25.154 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:25.154 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:25.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:17:25.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:25.155 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:17:25.155 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:17:25.155 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:17:25.155 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:17:25.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:25.171 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:17:25.171 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:17:25.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:25.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:25.215 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:17:25.283 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:25.283 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:25.283 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:25.283 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:25.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:25.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:25.659 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:25.659 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:25.659 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:17:25.665 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:25.665 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:25.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:17:25.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:25.667 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:17:25.667 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:17:25.667 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:17:25.667 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:17:25.680 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:17:25.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:25.683 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:17:25.683 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:17:25.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:25.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:26.145 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:17:26.284 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:26.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:26.284 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:26.284 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:26.610 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:17:26.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:26.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:26.762 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:26.762 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:26.768 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:26.769 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:26.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:17:26.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:26.771 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:17:26.771 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:17:26.771 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:17:26.771 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:17:26.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:26.870 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:17:26.870 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:17:26.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:26.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:27.075 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:17:27.284 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:27.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:27.284 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:27.284 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:27.538 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:17:28.001 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:17:28.284 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:28.285 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:28.285 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:28.285 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:28.464 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:17:28.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:28.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:28.779 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:28.779 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:28.779 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:17:28.782 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:28.782 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:28.782 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:28.782 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:28.783 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:28.783 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:28.783 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:17:28.783 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:17:28.783 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:17:28.783 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:28.783 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:33.785 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:17:33.785 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:17:33.785 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:33.785 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:33.785 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:33.785 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:33.790 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:33.790 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:17:33.790 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:33.790 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:17:33.790 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:17:33.791 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:17:33.791 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:17:33.791 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:17:33.791 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:33.791 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:33.791 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:17:33.791 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:17:33.791 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:17:33.791 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:33.792 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:17:33.792 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:17:33.792 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:17:33.792 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:33.792 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:33.792 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:17:33.792 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:17:33.792 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:17:33.792 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:33.793 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:17:33.793 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:17:33.793 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:17:33.793 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:33.793 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:33.793 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:17:33.793 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:17:33.793 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:17:33.793 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:33.795 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:17:33.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:17:33.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:17:33.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:17:33.795 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:17:33.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:17:33.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:17:33.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:33.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:17:33.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:17:33.795 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:17:33.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:33.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:33.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:17:33.796 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:17:33.796 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:17:33.796 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:33.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:33.800 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:17:34.265 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:17:34.319 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:17:34.320 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:17:34.320 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:17:34.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:34.327 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:34.327 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:34.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:17:34.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:34.329 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:17:34.329 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:17:34.329 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:17:34.329 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:17:34.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:34.357 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:17:34.357 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:17:34.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:34.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:34.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:34.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:34.659 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:34.659 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:34.666 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:34.666 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:34.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:17:34.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:34.668 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:17:34.668 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:17:34.668 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:17:34.668 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:17:34.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:34.686 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:17:34.686 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:17:34.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:34.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:34.728 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:17:34.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:34.799 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:34.800 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:34.802 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:35.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:35.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:35.171 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:35.171 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:35.171 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:17:35.177 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:35.177 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:35.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:17:35.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:35.179 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:17:35.179 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:17:35.179 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:17:35.179 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:17:35.190 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:17:35.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:35.194 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:17:35.194 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:17:35.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:35.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:35.653 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:17:35.800 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:35.800 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:35.801 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:35.803 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:36.116 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:17:36.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:36.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:36.271 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:36.271 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:36.278 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:36.278 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:36.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:17:36.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:36.281 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:17:36.281 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:17:36.281 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:17:36.281 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:17:36.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:36.300 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:17:36.300 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:17:36.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:36.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:36.578 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:17:36.800 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:36.800 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:36.801 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:36.803 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:37.041 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:17:37.503 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:17:37.800 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:37.800 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:37.802 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:37.804 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:37.966 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:17:38.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:38.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:17:38.278 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:38.278 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:38.278 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:17:38.280 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:38.280 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:38.280 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:38.280 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:38.281 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:38.281 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:17:38.281 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:17:38.281 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:17:38.281 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:38.281 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:38.281 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:38.281 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=989 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:17:38.281 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=989 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:17:38.281 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=989 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:17:38.281 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=989 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:17:38.281 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=989 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:17:38.281 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=989 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:17:43.283 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:17:43.283 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:17:43.283 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:43.283 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:43.283 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:43.283 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:43.286 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:43.287 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:17:43.287 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:43.287 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:17:43.287 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:17:43.288 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:17:43.288 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:17:43.288 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:17:43.288 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:43.288 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:43.288 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:17:43.288 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:17:43.288 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:17:43.288 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:43.289 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:17:43.289 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:17:43.289 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:17:43.289 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:43.289 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:43.289 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:17:43.289 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:17:43.289 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:17:43.289 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:43.291 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:17:43.291 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:17:43.291 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:17:43.291 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:43.291 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:43.291 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:17:43.291 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:17:43.291 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:17:43.291 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:43.294 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:17:43.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:17:43.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:17:43.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:17:43.294 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:17:43.295 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:17:43.295 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:43.295 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:43.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:43.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:43.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:43.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:43.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:43.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:43.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:43.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:43.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:43.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:43.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:43.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:43.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:43.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:43.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:43.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:43.300 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:17:43.765 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:17:43.812 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:17:43.813 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:17:43.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:43.814 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:17:43.820 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:43.820 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:43.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:17:43.827 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:43.827 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:43.827 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:43.827 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:43.827 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:43.827 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:43.827 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:43.827 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:43.827 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:17:43.827 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:17:43.828 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:17:48.837 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:17:48.837 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:17:48.837 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:48.837 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:48.837 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:48.837 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:48.845 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:48.846 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:17:48.846 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:48.846 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:17:48.846 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:17:48.848 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:17:48.848 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:17:48.848 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:17:48.848 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:48.848 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:48.849 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:17:48.849 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:17:48.849 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:17:48.849 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:48.852 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:17:48.852 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:17:48.852 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:17:48.852 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:48.852 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:48.852 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:17:48.853 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:17:48.853 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:17:48.853 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:48.855 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:17:48.856 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:17:48.856 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:17:48.856 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:48.856 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:48.856 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:17:48.856 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:17:48.856 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:17:48.856 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:48.859 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:17:48.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:17:48.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:17:48.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:17:48.859 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:17:48.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:17:48.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:17:48.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:48.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:17:48.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:17:48.860 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:17:48.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:48.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:48.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:48.860 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:48.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:48.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:48.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:48.860 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:17:48.860 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:17:48.860 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:17:48.860 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:17:48.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:48.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:48.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:48.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:17:48.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:48.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:48.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:48.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:48.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:48.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:48.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:48.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:48.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:48.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:48.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:48.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:48.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:48.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:48.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:48.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:48.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:48.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:48.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:48.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:48.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:48.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:48.865 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:17:49.331 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:17:49.384 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:17:49.385 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:17:49.386 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:17:49.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:49.397 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:49.397 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:49.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:17:49.404 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:49.404 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:49.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:17:49.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:49.409 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:49.409 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:49.409 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:49.409 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:49.409 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:49.410 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:17:49.410 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:17:49.410 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:17:49.410 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:49.410 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:49.410 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:49.410 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:17:49.410 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:17:49.410 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:17:49.410 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:17:49.410 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:17:49.410 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:17:54.411 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:17:54.411 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:17:54.411 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:54.411 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:54.411 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:54.411 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:54.413 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:54.414 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:17:54.414 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:54.414 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:17:54.414 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:17:54.415 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:17:54.415 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:17:54.415 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:17:54.415 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:54.415 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:54.415 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:17:54.415 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:17:54.415 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:17:54.415 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:54.416 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:17:54.416 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:17:54.416 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:17:54.416 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:54.416 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:54.417 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:17:54.417 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:17:54.417 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:17:54.417 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:54.418 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:17:54.418 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:17:54.418 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:17:54.418 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:54.418 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:54.418 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:17:54.418 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:17:54.418 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:17:54.418 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:17:54.420 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:17:54.420 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:17:54.420 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:54.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:54.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:54.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:54.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:54.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:54.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:54.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:54.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:54.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:54.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:54.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:54.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:54.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:54.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:54.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:54.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:54.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:54.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:54.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:54.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:54.425 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:17:54.888 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:17:54.934 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:17:54.935 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:17:54.935 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:17:54.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:17:54.941 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:17:54.941 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:17:54.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:17:54.946 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:54.946 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:54.946 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:54.946 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:54.947 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:54.947 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:54.947 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:54.947 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:54.947 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:17:54.947 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:17:54.947 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:17:59.949 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:17:59.949 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:17:59.949 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:59.949 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:59.949 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:59.949 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:59.956 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:59.956 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:17:59.956 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:59.957 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:17:59.957 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:17:59.958 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:17:59.958 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:17:59.958 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:17:59.958 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:59.958 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:59.958 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:17:59.958 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:17:59.958 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:17:59.958 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:17:59.960 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:17:59.960 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:17:59.960 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:17:59.960 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:59.960 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:59.960 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:17:59.960 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:17:59.960 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:17:59.960 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:17:59.961 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:17:59.961 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:17:59.961 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:17:59.961 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:17:59.961 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:59.961 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:17:59.961 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:17:59.961 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:17:59.961 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:17:59.963 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:17:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:17:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:17:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:17:59.963 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:17:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:17:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:17:59.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:17:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:17:59.963 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:17:59.964 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:17:59.964 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:17:59.964 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:17:59.965 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:17:59.965 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:17:59.965 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:17:59.965 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:17:59.965 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:17:59.965 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:17:59.965 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:18:04.968 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:18:04.968 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:18:04.968 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:18:04.968 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:18:04.968 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:18:04.968 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:18:04.971 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:18:04.972 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:18:04.972 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:18:04.972 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:18:04.972 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:18:04.973 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:18:04.973 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:18:04.973 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:18:04.973 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:18:04.973 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:18:04.973 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:18:04.973 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:18:04.973 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:18:04.973 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:18:04.974 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:18:04.974 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:18:04.974 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:18:04.974 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:18:04.974 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:18:04.975 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:18:04.975 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:18:04.975 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:18:04.975 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:18:04.976 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:18:04.976 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:18:04.976 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:18:04.976 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:18:04.976 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:18:04.976 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:18:04.976 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:18:04.976 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:18:04.976 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:18:04.978 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:18:04.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:18:04.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:18:04.978 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:18:04.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:18:04.979 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:18:04.979 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:18:04.979 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:18:04.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:18:04.983 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:18:05.447 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:18:05.494 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:18:05.495 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:18:05.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:05.496 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:18:05.502 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:05.502 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:05.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:18:05.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:05.504 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:05.504 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:05.504 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:18:05.504 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:18:05.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:05.539 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:05.539 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:05.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:05.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:05.909 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:18:05.982 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:18:05.982 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:18:05.982 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:18:05.982 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:18:06.372 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:18:06.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:06.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:06.478 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:06.478 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:06.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:06.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:06.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:18:06.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:06.487 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:06.487 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:06.487 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:18:06.487 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:18:06.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:06.528 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:06.528 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:06.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:06.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:06.834 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:18:06.983 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:18:06.983 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:18:06.983 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:18:06.983 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:18:07.297 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:18:07.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:07.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:07.420 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:07.420 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:07.427 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:07.427 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:07.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:18:07.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:07.428 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:07.428 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:07.428 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:18:07.428 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:18:07.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:07.476 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:07.476 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:07.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:07.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:07.759 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:18:07.983 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:18:07.983 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:18:07.983 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:18:07.983 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:18:08.221 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:18:08.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:08.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:08.375 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:08.375 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:08.382 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:08.382 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:08.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:18:08.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:08.383 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:08.383 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:08.383 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:18:08.383 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:18:08.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:08.405 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:08.405 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:08.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:08.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:08.683 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:18:08.984 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:18:08.984 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:18:08.984 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:18:08.984 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:18:09.146 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:18:09.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:09.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:09.317 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:09.317 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:09.324 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:09.324 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:09.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:18:09.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:09.325 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:09.325 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:09.325 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:18:09.325 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:18:09.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:09.378 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:09.379 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:09.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:09.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:09.608 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:18:09.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:09.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:09.921 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:09.921 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:09.928 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:09.928 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:09.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:18:09.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:09.930 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:09.930 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:09.930 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:18:09.930 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:18:09.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:09.978 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:18:09.978 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-06 03:18:09.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:09.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:09.984 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:18:09.984 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:18:09.984 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:18:09.984 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:18:10.071 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:18:10.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:10.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:10.512 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:10.512 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:10.512 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:18:10.518 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:10.518 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:10.518 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:18:10.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:10.519 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:10.519 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:10.519 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:18:10.519 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:18:10.533 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:18:10.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:10.536 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:18:10.536 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-06 03:18:10.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:10.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:10.996 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:18:11.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:11.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:11.079 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:11.079 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:11.079 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:18:11.085 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:11.085 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:11.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:18:11.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:11.086 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:11.087 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:11.087 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:18:11.087 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:18:11.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:11.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:11.132 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:11.132 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:11.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:11.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:11.459 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:18:11.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:11.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:11.726 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:11.726 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:11.731 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:11.732 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:11.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:18:11.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:11.733 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:11.733 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:11.733 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:18:11.733 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:18:11.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:11.736 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:11.736 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:11.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:11.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:11.923 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:18:12.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:12.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:12.326 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:12.326 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:12.332 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:12.332 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:12.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:18:12.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:12.333 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:12.333 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:12.333 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:18:12.333 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:18:12.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:12.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:12.341 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:12.341 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:12.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:12.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:12.385 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:18:12.848 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:18:12.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:12.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:12.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:12.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:12.871 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:12.871 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:12.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:18:12.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:12.872 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:12.872 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:12.872 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:18:12.872 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:18:12.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:12.890 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:18:12.890 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:18:12.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:12.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:13.310 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:18:13.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:13.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:13.452 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:13.452 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:13.452 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:18:13.458 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:13.458 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:13.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:18:13.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:13.459 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:13.459 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:13.459 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:18:13.459 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:18:13.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:13.491 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:18:13.491 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:18:13.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:13.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:13.773 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:18:14.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:14.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:14.089 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:14.089 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:14.089 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:18:14.095 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:14.095 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:14.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:18:14.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:14.096 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:14.096 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:14.096 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:18:14.096 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:18:14.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:14.141 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:18:14.142 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:18:14.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:14.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:14.235 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:18:14.697 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:18:14.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:14.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:14.938 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:14.938 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:14.938 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:18:14.944 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:14.944 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:14.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:18:14.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:14.945 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:14.945 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:14.945 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:18:14.945 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:18:14.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:14.977 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:18:14.977 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:18:14.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:14.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:15.160 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:18:15.623 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:18:15.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:15.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:15.879 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:15.879 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:15.879 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:18:15.885 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:15.885 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:15.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:18:15.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:15.886 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:15.886 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:15.886 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:18:15.886 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:18:15.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:15.900 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:18:15.900 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:18:15.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:15.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:16.085 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:18:16.547 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:18:16.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:16.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:16.825 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:16.825 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:16.825 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:18:16.831 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:16.831 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:16.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:18:16.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:16.832 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:16.832 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:16.832 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:18:16.832 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:18:16.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:16.874 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:18:16.874 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:18:16.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:16.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:17.010 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:18:17.473 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:18:17.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:17.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:17.768 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:17.768 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:17.768 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:18:17.773 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:17.773 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:17.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:18:17.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:17.774 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:17.774 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:17.774 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:18:17.774 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:18:17.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:17.796 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:18:17.796 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:18:17.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:17.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:17.935 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:18:18.397 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:18:18.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:18.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:18.709 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:18.709 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:18.709 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:18:18.716 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:18.716 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:18.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:18:18.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:18.717 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:18.717 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:18.717 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:18:18.717 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:18:18.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:18.766 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:18:18.766 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:18:18.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:18.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:18.860 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:18:19.323 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:18:19.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:19.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:19.655 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:19.655 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:19.655 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:18:19.660 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:19.660 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:19.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:18:19.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:19.661 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:19.661 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:19.661 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:18:19.661 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:18:19.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:19.694 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:18:19.694 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:18:19.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:19.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:19.785 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:18:20.248 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:18:20.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:20.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:20.597 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:20.597 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:20.597 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:18:20.603 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:20.603 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:20.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:18:20.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:20.604 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:20.604 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:20.604 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:18:20.604 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:18:20.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:20.617 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:18:20.617 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:18:20.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:20.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:20.710 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:18:21.173 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:18:21.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:21.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:21.543 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:21.543 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:21.543 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:18:21.545 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:18:21.545 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:18:21.545 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:18:21.545 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:18:21.546 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:18:21.546 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:18:21.546 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:18:21.546 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:18:21.546 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:18:21.546 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:18:21.546 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:18:21.546 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3653 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:18:21.546 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3653 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:18:21.546 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3653 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:18:21.546 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3653 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:18:21.546 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3653 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:18:21.546 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3653 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:18:26.547 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:18:26.547 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:18:26.547 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:18:26.547 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:18:26.547 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:18:26.548 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:18:26.551 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:18:26.551 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:18:26.551 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:18:26.551 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:18:26.551 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:18:26.552 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:18:26.552 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:18:26.552 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:18:26.552 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:18:26.552 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:18:26.552 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:18:26.552 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:18:26.552 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:18:26.552 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:18:26.553 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:18:26.553 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:18:26.553 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:18:26.553 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:18:26.553 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:18:26.553 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:18:26.553 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:18:26.553 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:18:26.553 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:18:26.554 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:18:26.554 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:18:26.555 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:18:26.555 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:18:26.555 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:18:26.555 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:18:26.555 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:18:26.555 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:18:26.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:18:26.556 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:18:26.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:18:26.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:18:26.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:18:26.556 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:18:26.557 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:18:26.557 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:18:26.557 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:26.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:18:26.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:18:26.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:26.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:18:26.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:26.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:18:26.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:18:26.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:26.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:18:26.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:26.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:26.562 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:18:27.027 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:18:27.069 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:18:27.069 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:18:27.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:27.070 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:18:27.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:27.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:27.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:18:27.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:27.076 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:27.076 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:27.076 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:18:27.076 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:18:27.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:27.118 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:27.118 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:27.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:27.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:27.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:27.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:27.370 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:27.371 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:27.376 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:27.376 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:27.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:18:27.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:27.377 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:27.377 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:27.377 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:18:27.377 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:18:27.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:27.400 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:27.400 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:27.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:27.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:27.490 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:18:27.558 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:18:27.559 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:18:27.559 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:18:27.559 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:18:27.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:27.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:27.615 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:27.615 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:27.621 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:27.621 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:27.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:18:27.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:27.622 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:27.622 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:27.622 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:18:27.622 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:18:27.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:27.626 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:27.626 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:27.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:27.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:27.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:27.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:27.878 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:27.878 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:27.885 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:27.885 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:27.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:18:27.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:27.886 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:27.886 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:27.886 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:18:27.886 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:18:27.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:27.907 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:18:27.908 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:18:27.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:27.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:27.952 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:18:28.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:18:28.123 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:18:28.123 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:18:28.123 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:18:28.125 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:18:28.125 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:18:28.125 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:18:28.125 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:18:28.125 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:18:28.125 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:18:28.125 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:18:28.125 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:18:28.125 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:18:28.125 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:18:28.126 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:18:33.127 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:18:33.127 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:18:33.127 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:18:33.127 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:18:33.127 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:18:33.127 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:18:33.129 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:18:33.129 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:18:33.129 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:18:33.129 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:18:33.129 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:18:33.131 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:18:33.131 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:18:33.131 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:18:33.131 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:18:33.131 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:18:33.131 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:18:33.131 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:18:33.131 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:18:33.131 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:18:33.132 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:18:33.133 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:18:33.133 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:18:33.133 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:18:33.133 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:18:33.133 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:18:33.133 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:18:33.133 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:18:33.133 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:18:33.134 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:18:33.134 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:18:33.134 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:18:33.134 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:18:33.134 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:18:33.134 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:18:33.134 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:18:33.134 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:18:33.134 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:18:33.136 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:18:33.136 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:18:33.136 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:33.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:18:33.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:18:33.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:33.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:18:33.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:18:33.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:18:33.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:33.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:18:33.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:18:33.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:33.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:18:33.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:33.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:18:33.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:18:33.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:33.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:18:33.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:33.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:18:33.141 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:18:33.605 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:18:34.067 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:18:34.529 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:18:34.992 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:18:35.454 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:18:35.916 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:18:36.378 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:18:36.841 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:18:37.303 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:18:37.765 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:18:38.227 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:18:38.689 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:18:39.151 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:18:39.614 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:18:40.076 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:18:40.538 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:18:41.000 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:18:41.462 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:18:41.926 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:18:42.392 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:18:42.855 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:18:43.317 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:18:43.781 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:18:44.245 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:18:44.708 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:18:45.173 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:18:45.636 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:18:46.101 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:18:46.564 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:18:47.027 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:18:47.491 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:18:47.954 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:18:48.419 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:18:48.883 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:18:49.347 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:18:49.810 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:18:50.272 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:18:50.735 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:18:51.198 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:18:51.661 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 03:18:52.124 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 03:18:52.586 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 03:18:53.050 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 03:18:53.513 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 03:18:53.976 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 03:18:54.439 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 03:18:54.902 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 03:18:55.364 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 03:18:55.827 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 03:18:56.290 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 03:18:56.753 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 03:18:57.155 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:18:57.156 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:18:57.156 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:18:57.156 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:18:57.156 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:18:57.156 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:18:57.156 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:18:57.156 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5291 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:18:57.156 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5291 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:18:57.156 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5291 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:18:57.156 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5291 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:18:57.156 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5291 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:18:57.156 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5291 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:18:57.156 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=5291 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:19:02.162 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:19:02.162 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:19:02.162 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:19:02.162 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:19:02.162 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:19:02.162 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:19:02.169 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:19:02.170 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:19:02.170 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:19:02.170 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:19:02.170 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:19:02.171 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:19:02.172 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:19:02.172 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:19:02.172 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:19:02.172 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:19:02.172 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:19:02.172 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:19:02.172 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:19:02.172 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:19:02.174 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:19:02.174 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:19:02.174 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:19:02.174 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:19:02.174 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:19:02.174 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:19:02.174 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:19:02.174 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:19:02.174 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:19:02.177 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:19:02.177 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:19:02.177 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:19:02.177 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:19:02.177 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:19:02.177 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:19:02.177 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:19:02.177 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:19:02.177 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:19:02.183 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:19:02.183 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:19:02.183 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:19:02.183 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:19:02.183 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:19:02.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:19:02.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:19:02.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:19:02.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:19:02.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:19:02.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:19:02.184 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:19:02.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:19:02.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:19:02.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:19:02.184 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:19:02.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:19:02.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:19:02.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:19:02.184 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:19:02.184 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:19:02.184 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:19:02.184 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:19:02.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:19:02.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:19:02.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:19:02.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:19:02.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:19:02.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:19:02.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:19:02.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:19:02.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:19:02.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:19:02.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:19:02.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:19:02.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:19:02.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:19:02.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:19:02.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:19:02.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:19:02.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:19:02.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:19:02.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:19:02.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:19:02.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:19:02.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:19:02.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:19:02.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:19:02.189 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:19:02.657 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:19:03.123 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:19:03.587 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:19:04.051 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:19:04.514 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:19:04.979 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:19:05.448 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:19:05.917 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:19:06.386 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:19:06.860 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:19:07.322 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:19:07.786 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:19:08.250 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:19:08.718 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:19:09.182 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:19:09.646 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:19:10.110 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:19:10.575 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:19:11.041 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:19:11.505 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:19:11.971 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:19:12.440 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:19:12.903 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:19:13.366 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:19:13.829 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:19:14.293 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:19:14.757 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:19:15.220 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:19:15.689 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:19:16.153 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:19:16.617 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:19:17.080 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:19:17.549 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:19:18.014 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:19:18.478 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:19:18.943 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:19:19.407 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:19:19.871 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:19:20.337 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:19:20.801 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 03:19:21.265 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 03:19:21.731 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 03:19:22.206 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 03:19:22.670 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 03:19:23.136 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 03:19:23.604 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 03:19:24.067 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 03:19:24.535 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 03:19:24.999 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 03:19:25.464 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 03:19:25.928 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 03:19:26.393 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 03:19:26.858 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 03:19:27.325 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 03:19:27.789 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 03:19:28.255 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 03:19:28.718 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 03:19:29.182 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 03:19:29.646 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 03:19:30.110 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 03:19:30.574 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 03:19:31.037 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 03:19:31.501 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 03:19:31.964 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 03:19:32.428 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 03:19:32.893 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 03:19:33.357 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 03:19:33.821 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 03:19:34.283 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 03:19:34.746 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 03:19:35.210 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 03:19:35.674 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 03:19:36.138 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 03:19:36.602 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-06 03:19:37.065 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-06 03:19:37.530 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-06 03:19:37.994 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-06 03:19:38.457 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-06 03:19:38.921 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-06 03:19:39.212 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:19:39.387 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-06 03:19:39.856 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-06 03:19:40.213 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:19:40.320 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-06 03:19:40.785 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-06 03:19:41.214 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:19:41.249 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-06 03:19:41.714 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-06 03:19:42.178 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-06 03:19:42.215 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:19:42.644 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-06 03:19:43.109 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-06 03:19:43.215 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:19:43.571 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-06 03:19:44.035 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-06 03:19:44.219 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:19:44.219 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:19:44.219 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:19:44.219 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:19:44.219 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:19:44.219 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:19:44.219 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:19:44.219 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:19:49.222 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:19:49.222 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:19:49.222 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:19:49.222 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:19:49.222 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:19:49.222 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:19:49.225 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:19:49.225 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:19:49.225 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:19:49.226 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:19:49.226 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:19:49.226 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:19:49.226 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:19:49.226 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:19:49.226 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:19:49.227 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:19:49.227 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:19:49.227 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:19:49.227 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:19:49.227 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:19:49.228 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:19:49.228 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:19:49.228 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:19:49.228 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:19:49.228 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:19:49.228 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:19:49.228 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:19:49.228 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:19:49.228 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:19:49.229 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:19:49.229 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:19:49.229 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:19:49.229 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:19:49.229 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:19:49.229 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:19:49.229 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:19:49.229 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:19:49.229 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:19:49.231 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:19:49.231 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:19:49.231 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:19:49.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:19:49.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:19:49.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:19:49.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:19:49.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:19:49.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:19:49.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:19:49.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:19:49.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:19:49.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:19:49.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:19:49.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:19:49.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:19:49.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:19:49.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:19:49.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:19:49.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:19:49.236 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:19:49.700 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:19:49.762 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:19:49.765 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:19:49.767 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:19:49.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:19:49.795 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:19:49.795 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:19:49.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:19:49.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:19:49.799 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:19:49.799 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:19:49.799 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:19:49.800 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:19:49.840 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:19:49.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:19:49.855 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:19:49.855 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:19:49.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:19:49.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:19:50.164 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:19:50.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:19:50.234 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:19:50.234 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:19:50.234 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:19:50.627 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:19:51.095 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:19:51.118 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 03:19:51.233 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:19:51.235 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:19:51.235 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:19:51.235 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:19:51.560 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:19:52.025 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:19:52.233 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:19:52.236 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:19:52.236 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:19:52.236 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:19:52.490 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:19:53.045 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:19:53.234 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:19:53.236 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:19:53.236 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:19:53.236 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:19:53.511 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:19:53.980 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:19:54.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:19:54.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:19:54.059 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:19:54.059 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:19:54.069 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:19:54.069 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:19:54.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:19:54.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:19:54.071 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:19:54.071 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:19:54.071 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:19:54.071 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:19:54.113 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:19:54.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:19:54.117 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:19:54.117 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:19:54.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:19:54.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:19:54.235 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:19:54.236 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:19:54.237 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:19:54.237 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:19:54.447 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:19:54.916 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:19:55.381 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:19:55.849 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:19:56.314 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:19:56.782 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:19:57.246 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:19:57.715 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:19:58.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:19:58.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:19:58.105 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:19:58.106 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:19:58.106 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:19:58.113 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:19:58.113 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:19:58.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:19:58.115 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:19:58.115 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:19:58.115 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:19:58.115 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:19:58.115 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:19:58.129 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:19:58.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:19:58.134 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:19:58.134 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:19:58.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:19:58.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:19:58.179 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:19:58.614 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 03:19:58.643 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:19:59.108 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:19:59.573 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:20:00.043 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:20:00.507 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:20:00.975 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:20:01.442 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:20:01.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:20:01.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:01.894 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:20:01.894 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:20:01.902 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:20:01.902 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:20:01.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:20:01.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:01.903 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:20:01.903 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:20:01.903 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:20:01.903 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:20:01.908 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:20:01.908 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:01.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:20:01.912 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:20:01.912 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:20:01.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:01.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:02.371 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:20:02.834 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:20:03.218 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 03:20:03.296 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:20:03.760 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:20:04.146 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 03:20:04.223 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:20:04.607 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 03:20:04.685 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:20:05.149 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:20:05.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:20:05.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:05.537 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:20:05.537 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:20:05.537 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:20:05.539 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:20:05.539 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:20:05.539 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:20:05.539 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:20:05.540 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:20:05.540 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:20:05.540 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:20:05.540 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:20:05.540 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:20:05.541 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:20:05.541 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:20:10.542 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:20:10.542 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:20:10.542 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:20:10.542 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:20:10.542 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:20:10.542 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:20:10.545 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:20:10.545 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:20:10.545 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:20:10.545 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:20:10.545 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:20:10.546 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:20:10.546 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:20:10.546 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:20:10.546 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:20:10.546 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:20:10.546 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:20:10.546 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:20:10.546 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:20:10.546 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:20:10.547 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:20:10.547 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:20:10.547 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:20:10.547 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:20:10.547 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:20:10.547 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:20:10.547 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:20:10.547 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:20:10.548 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:20:10.548 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:20:10.548 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:20:10.549 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:20:10.549 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:20:10.549 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:20:10.549 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:20:10.549 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:20:10.549 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:20:10.549 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:20:10.550 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:20:10.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:20:10.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:20:10.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:20:10.550 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:20:10.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:20:10.551 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:20:10.551 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:20:10.551 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:20:10.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:20:10.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:20:10.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:20:10.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:20:10.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:20:10.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:20:10.555 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:20:11.021 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:20:11.062 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:20:11.063 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:11.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:20:11.063 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:20:11.071 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:20:11.071 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:20:11.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:20:11.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:11.073 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:20:11.073 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:20:11.073 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:20:11.073 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:20:11.110 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:11.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:20:11.114 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:20:11.114 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:20:11.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:11.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:11.484 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:20:11.488 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:11.552 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:20:11.553 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:20:11.553 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:20:11.553 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:20:11.947 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:20:11.958 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:11.959 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 03:20:12.409 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:20:12.429 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:12.553 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:20:12.554 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:20:12.554 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:20:12.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:20:12.876 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:20:12.905 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:13.338 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:20:13.380 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:13.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:20:13.554 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:20:13.554 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:20:13.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:20:13.800 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:20:13.851 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:14.265 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:20:14.322 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:14.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:20:14.554 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:20:14.554 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:20:14.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:20:14.730 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:20:14.797 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:15.192 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:20:15.268 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:15.555 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:20:15.555 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:20:15.555 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:20:15.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:20:15.655 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:20:15.743 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:16.117 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:20:16.214 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:16.579 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:20:16.685 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:17.043 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:20:17.155 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:17.505 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:20:17.626 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:17.967 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:20:18.097 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:18.430 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:20:18.573 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:18.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:20:18.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:18.576 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:20:18.576 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:20:18.582 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:20:18.582 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:20:18.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:20:18.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:18.584 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:20:18.584 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:20:18.584 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:20:18.584 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:20:18.610 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:18.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:20:18.614 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:20:18.614 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:20:18.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:18.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:18.893 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:20:19.284 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:19.355 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:20:19.754 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:19.818 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:20:20.229 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:20.281 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:20:20.700 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:20.745 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:20:21.171 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:21.208 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:20:21.646 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:21.671 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:20:22.117 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:22.133 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:20:22.588 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:22.595 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:20:23.058 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:20:23.060 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:23.521 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:20:23.525 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:23.983 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:20:23.996 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:24.447 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:20:24.466 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:24.909 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:20:24.942 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:25.372 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:20:25.412 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:25.834 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:20:25.883 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:26.296 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:20:26.354 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:26.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:20:26.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:26.357 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:20:26.357 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:20:26.357 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:20:26.364 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:20:26.364 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:20:26.364 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:20:26.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:26.365 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:20:26.365 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:20:26.365 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:20:26.365 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:20:26.382 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:26.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:20:26.386 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:20:26.387 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:20:26.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:26.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:26.728 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:26.761 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:20:27.194 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:27.195 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 03:20:27.224 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:20:27.655 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:27.687 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:20:28.122 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:28.150 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:20:28.583 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:28.615 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:20:29.045 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:29.078 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 03:20:29.511 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:29.541 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 03:20:29.973 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:30.005 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 03:20:30.439 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:30.468 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 03:20:30.900 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:30.930 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 03:20:31.362 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:31.394 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 03:20:31.828 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:31.857 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 03:20:32.290 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:32.319 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 03:20:32.751 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:32.782 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 03:20:33.212 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:33.246 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 03:20:33.679 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:33.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:20:33.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:33.682 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:20:33.682 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:20:33.692 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:20:33.692 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:20:33.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:20:33.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:33.695 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:20:33.695 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:20:33.695 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:20:33.695 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:20:33.709 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 03:20:33.711 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:33.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:20:33.719 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:20:33.719 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:20:33.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:33.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:34.095 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:34.172 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 03:20:34.556 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:34.634 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 03:20:35.022 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:35.022 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 03:20:35.096 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 03:20:35.483 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:35.559 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 03:20:35.945 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:36.022 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 03:20:36.406 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:36.485 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 03:20:36.872 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:36.873 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 03:20:36.949 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 03:20:37.334 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:37.412 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 03:20:37.796 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:37.796 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 03:20:37.874 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 03:20:38.262 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:38.336 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 03:20:38.723 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:38.724 [DEBUG] fake_trx.py:269 (MS@172.18.59.22:6700) Recv SETTA cmd
2026-03-06 03:20:38.799 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 03:20:39.185 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:39.263 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 03:20:39.651 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:39.727 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 03:20:40.113 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:40.190 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 03:20:40.574 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:40.654 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 03:20:41.040 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:41.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:20:41.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:41.043 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:20:41.043 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:20:41.043 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:20:41.046 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:20:41.046 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:20:41.046 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:20:41.046 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:20:41.047 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:20:41.047 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:20:41.047 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:20:41.047 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:20:41.047 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:20:41.047 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:20:41.047 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:20:46.049 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:20:46.049 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:20:46.049 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:20:46.049 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:20:46.049 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:20:46.049 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:20:46.053 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:20:46.054 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:20:46.054 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:20:46.054 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:20:46.054 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:20:46.055 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:20:46.055 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:20:46.055 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:20:46.055 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:20:46.055 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:20:46.055 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:20:46.055 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:20:46.055 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:20:46.055 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:20:46.056 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:20:46.056 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:20:46.056 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:20:46.056 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:20:46.056 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:20:46.056 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:20:46.056 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:20:46.057 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:20:46.057 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:20:46.058 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:20:46.058 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:20:46.058 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:20:46.058 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:20:46.058 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:20:46.058 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:20:46.058 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:20:46.058 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:20:46.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:20:46.060 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:20:46.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:20:46.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:20:46.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:20:46.060 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:20:46.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:20:46.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:20:46.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:20:46.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:20:46.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:20:46.060 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:20:46.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:20:46.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:20:46.060 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:20:46.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:20:46.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:20:46.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:20:46.060 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:20:46.060 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:20:46.060 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:20:46.060 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:20:46.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:20:46.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:20:46.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:20:46.065 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:20:46.529 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:20:46.674 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:20:46.675 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:46.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:20:46.676 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:20:46.683 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:20:46.683 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:20:46.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:20:46.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:46.685 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:20:46.685 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:20:46.685 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:20:46.685 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:20:46.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:20:46.721 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:20:46.721 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:20:46.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:46.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:46.992 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:20:47.063 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:20:47.063 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:20:47.063 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:20:47.063 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:20:47.455 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:20:47.917 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:20:48.064 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:20:48.064 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:20:48.064 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:20:48.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:20:48.380 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:20:48.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:20:48.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:48.813 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:20:48.813 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:20:48.820 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:20:48.820 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:20:48.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:20:48.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:48.821 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:20:48.821 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:20:48.821 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:20:48.821 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:20:48.843 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:20:48.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:20:48.847 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:20:48.847 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:20:48.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:48.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:49.064 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:20:49.064 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:20:49.064 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:20:49.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:20:49.305 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:20:49.769 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:20:50.065 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:20:50.065 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:20:50.065 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:20:50.065 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:20:50.232 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:20:50.695 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:20:50.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:20:50.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:50.930 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:20:50.930 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:20:50.937 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:20:50.937 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:20:50.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:20:50.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:50.938 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:20:50.938 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:20:50.938 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:20:50.938 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:20:50.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:20:50.973 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:20:50.973 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:20:50.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:50.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:51.065 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:20:51.065 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:20:51.065 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:20:51.065 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:20:51.160 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:20:51.623 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:20:52.086 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:20:52.548 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:20:53.011 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:20:53.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:20:53.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:53.053 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:20:53.054 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:20:53.056 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:20:53.056 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:20:53.056 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:20:53.056 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:20:53.057 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:20:53.057 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:20:53.057 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:20:53.057 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:20:53.057 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:20:53.057 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:20:53.057 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:20:58.059 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:20:58.059 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:20:58.059 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:20:58.059 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:20:58.059 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:20:58.059 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:20:58.062 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:20:58.062 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:20:58.062 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:20:58.063 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:20:58.063 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:20:58.063 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:20:58.063 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:20:58.064 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:20:58.064 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:20:58.064 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:20:58.064 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:20:58.064 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:20:58.064 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:20:58.064 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:20:58.065 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:20:58.065 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:20:58.065 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:20:58.065 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:20:58.065 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:20:58.065 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:20:58.065 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:20:58.065 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:20:58.065 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:20:58.066 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:20:58.066 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:20:58.066 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:20:58.066 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:20:58.066 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:20:58.066 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:20:58.066 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:20:58.066 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:20:58.066 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:20:58.068 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:20:58.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:20:58.068 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:20:58.068 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:20:58.068 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:20:58.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:20:58.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:20:58.068 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:20:58.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:20:58.068 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:20:58.068 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:20:58.068 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:20:58.068 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:20:58.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:20:58.068 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:20:58.068 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:20:58.068 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:20:58.068 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:20:58.069 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:20:58.069 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:20:58.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:20:58.073 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:20:58.539 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:20:58.584 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:20:58.585 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:20:58.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:20:58.586 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:20:58.592 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:20:58.592 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:20:58.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:20:58.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:58.593 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:20:58.593 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:20:58.594 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:20:58.594 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:20:58.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:20:58.632 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:20:58.632 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:20:58.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:58.633 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:20:59.003 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:20:59.072 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:20:59.072 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:20:59.072 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:20:59.072 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:20:59.465 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:20:59.928 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:21:00.072 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:00.072 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:00.072 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:00.072 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:00.390 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:21:00.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:00.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:00.717 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:00.717 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:00.717 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:21:00.723 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:00.723 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:00.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:21:00.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:00.725 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:21:00.725 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:21:00.725 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:21:00.725 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:21:00.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:00.764 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:21:00.764 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:21:00.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:00.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:00.853 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:21:01.073 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:01.073 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:01.073 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:01.073 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:01.315 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:21:01.778 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:21:02.074 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:02.074 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:02.074 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:02.074 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:02.240 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:21:02.703 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:21:02.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:02.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:02.861 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:02.861 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:02.861 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:21:02.865 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:02.865 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:02.865 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:02.865 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:02.867 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:21:02.867 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:21:02.867 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:21:02.867 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:21:02.867 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:21:02.867 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:21:02.867 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:21:07.870 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:21:07.870 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:21:07.870 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:21:07.870 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:21:07.870 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:21:07.870 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:21:07.877 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:21:07.877 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:21:07.877 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:07.877 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:21:07.877 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:21:07.880 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:21:07.880 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:21:07.880 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:21:07.880 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:07.880 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:21:07.880 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:21:07.881 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:21:07.881 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:21:07.881 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:07.883 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:21:07.883 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:21:07.883 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:21:07.883 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:07.883 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:21:07.883 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:21:07.883 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:21:07.883 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:21:07.884 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:07.886 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:21:07.886 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:21:07.886 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:21:07.886 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:07.887 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:21:07.887 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:21:07.887 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:21:07.887 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:21:07.887 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:07.896 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:21:07.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:21:07.897 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:21:07.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:21:07.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:21:07.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:21:07.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:21:07.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:21:07.897 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:21:07.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:07.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:21:07.897 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:07.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:07.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:07.897 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:21:07.897 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:21:07.897 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:21:07.897 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:21:07.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:07.898 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:07.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:07.902 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:21:08.366 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:21:08.438 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:21:08.439 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:21:08.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:08.440 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:21:08.453 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:08.453 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:08.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:21:08.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:08.457 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:21:08.457 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:21:08.457 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:21:08.457 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:21:08.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:08.509 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:21:08.510 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:21:08.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:08.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:08.830 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:21:08.903 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:08.904 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:08.906 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:08.918 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:09.293 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:21:09.757 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:21:09.903 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:09.904 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:09.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:09.918 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:10.222 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:21:10.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:10.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:10.597 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:10.597 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:10.609 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:10.609 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:10.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:21:10.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:10.612 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:21:10.612 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:21:10.612 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:21:10.612 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:21:10.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:10.644 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:21:10.645 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:21:10.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:10.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:10.687 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:21:10.904 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:10.905 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:10.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:10.919 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:11.152 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:21:11.617 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:21:11.905 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:11.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:11.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:11.919 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:12.081 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:21:12.544 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:21:12.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:12.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:12.722 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:12.722 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:12.728 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:12.728 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:12.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:21:12.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:12.729 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:21:12.730 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:21:12.730 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:21:12.730 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:21:12.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:12.779 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:21:12.779 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:21:12.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:12.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:12.905 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:12.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:12.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:12.920 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:13.007 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:21:13.472 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:21:13.935 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:21:14.398 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:21:14.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:14.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:14.856 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:14.856 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:14.860 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:14.860 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:14.860 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:14.860 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:14.861 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:21:14.862 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:21:14.862 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:21:14.862 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:21:14.862 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:21:14.862 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:21:14.862 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:21:14.862 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:21:14.862 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1531 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:21:14.862 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1531 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:21:14.862 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1531 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:21:14.862 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1531 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:21:14.862 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1531 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:21:14.862 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1531 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:21:14.862 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1531 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:21:14.862 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1532 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:21:14.862 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1532 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:21:14.862 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1532 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:21:14.862 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1532 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:21:14.862 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1532 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:21:14.862 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1532 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:21:14.862 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1532 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:21:14.862 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1532 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:21:19.862 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:21:19.862 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:21:19.862 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:21:19.862 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:21:19.862 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:21:19.862 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:21:19.866 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:21:19.866 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:21:19.866 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:19.866 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:21:19.866 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:21:19.868 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:21:19.868 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:21:19.868 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:21:19.868 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:19.868 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:21:19.868 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:21:19.868 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:21:19.868 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:21:19.868 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:19.869 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:21:19.869 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:21:19.869 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:21:19.870 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:19.870 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:21:19.870 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:21:19.870 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:21:19.870 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:21:19.870 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:19.871 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:21:19.871 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:21:19.871 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:21:19.871 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:19.871 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:21:19.871 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:21:19.871 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:21:19.871 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:21:19.871 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:21:19.874 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:21:19.874 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:21:19.874 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:19.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:19.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:19.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:19.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:19.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:19.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:19.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:19.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:19.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:19.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:19.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:19.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:19.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:19.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:19.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:19.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:19.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:19.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:19.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:19.879 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:21:20.344 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:21:20.392 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:21:20.393 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:21:20.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:20.394 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:21:20.405 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:20.405 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:20.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:21:20.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:20.406 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:21:20.406 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:21:20.407 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:21:20.407 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:21:20.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:20.437 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:21:20.437 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:21:20.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:20.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:20.807 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:21:20.877 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:20.877 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:20.877 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:20.877 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:21.269 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:21:21.733 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:21:21.877 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:21.877 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:21.878 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:21.878 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:22.196 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:21:22.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:22.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:22.522 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:22.522 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:22.522 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:21:22.529 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:22.529 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:22.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:21:22.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:22.531 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:21:22.531 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:21:22.531 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:21:22.531 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:21:22.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:22.568 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:21:22.568 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:21:22.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:22.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:22.659 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:21:22.878 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:22.878 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:22.878 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:22.878 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:23.122 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:21:23.585 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:21:23.879 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:23.879 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:23.879 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:23.879 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:24.048 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:21:24.511 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:21:24.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:24.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:24.663 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:24.663 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:24.663 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:21:24.666 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:24.666 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:24.666 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:24.666 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:24.667 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:21:24.667 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:21:24.667 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:21:24.667 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:21:24.667 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:21:24.667 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:21:24.667 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:21:29.670 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:21:29.670 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:21:29.670 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:21:29.670 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:21:29.670 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:21:29.670 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:21:29.673 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:21:29.673 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:21:29.673 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:29.673 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:21:29.673 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:21:29.674 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:21:29.674 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:21:29.674 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:21:29.675 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:29.675 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:21:29.675 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:21:29.675 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:21:29.675 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:21:29.675 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:29.676 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:21:29.676 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:21:29.676 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:21:29.676 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:29.676 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:21:29.676 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:21:29.676 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:21:29.676 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:21:29.676 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:29.677 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:21:29.677 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:21:29.677 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:21:29.677 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:29.677 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:21:29.677 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:21:29.677 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:21:29.677 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:21:29.678 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:29.679 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:21:29.679 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:21:29.679 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:21:29.680 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:21:29.680 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:29.680 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:29.680 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:29.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:29.681 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:29.681 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:29.681 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:29.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:29.681 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:29.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:29.681 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:29.681 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:29.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:29.681 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:29.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:29.681 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:29.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:29.685 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:21:30.147 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:21:30.198 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:21:30.199 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:21:30.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:30.200 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:21:30.214 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:30.214 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:30.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:21:30.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:30.219 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:21:30.219 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:21:30.219 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:21:30.219 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:21:30.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:30.244 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:21:30.245 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:21:30.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:30.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:30.610 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:21:30.682 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:30.682 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:30.683 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:30.685 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:31.073 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:21:31.536 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:21:31.683 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:31.683 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:31.683 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:31.685 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:31.998 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:21:32.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:32.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:32.386 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:32.386 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:32.389 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:32.389 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:32.389 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:32.389 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:32.390 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:21:32.390 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:21:32.390 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:21:32.390 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:21:32.390 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:21:32.390 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:21:32.390 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:21:37.392 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:21:37.392 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:21:37.392 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:21:37.392 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:21:37.392 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:21:37.392 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:21:37.399 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:21:37.400 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:21:37.400 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:37.400 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:21:37.400 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:21:37.402 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:21:37.402 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:21:37.402 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:21:37.402 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:37.402 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:21:37.402 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:21:37.402 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:21:37.402 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:21:37.402 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:37.404 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:21:37.404 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:21:37.404 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:21:37.404 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:37.404 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:21:37.404 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:21:37.404 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:21:37.405 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:21:37.405 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:37.405 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:21:37.406 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:21:37.406 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:21:37.406 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:37.406 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:21:37.406 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:21:37.406 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:21:37.406 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:21:37.406 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:37.407 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:21:37.407 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:21:37.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:21:37.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:21:37.407 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:21:37.408 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:21:37.408 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:21:37.408 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:37.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:37.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:37.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:37.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:37.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:37.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:37.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:37.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:37.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:37.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:37.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:37.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:37.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:37.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:37.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:37.413 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:21:37.876 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:21:37.920 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:21:37.921 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:21:37.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:37.922 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:21:37.927 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:37.927 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:37.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:21:37.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:37.929 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:21:37.929 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:21:37.929 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:21:37.929 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:21:37.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:37.969 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:21:37.969 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:21:37.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:37.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:38.340 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:21:38.410 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:38.410 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:38.410 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:38.411 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:38.803 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:21:39.266 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:21:39.410 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:39.410 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:39.410 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:39.411 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:39.803 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:21:40.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:40.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:40.130 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:40.130 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:40.130 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:21:40.132 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:40.132 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:40.132 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:40.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:40.133 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:21:40.133 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:21:40.133 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:21:40.133 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:21:40.133 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:21:40.133 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:21:40.133 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:21:45.135 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:21:45.135 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:21:45.135 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:21:45.135 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:21:45.135 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:21:45.135 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:21:45.138 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:21:45.138 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:21:45.138 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:45.139 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:21:45.139 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:21:45.139 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:21:45.140 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:21:45.140 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:21:45.140 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:45.140 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:21:45.140 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:21:45.140 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:21:45.140 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:21:45.140 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:45.141 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:21:45.141 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:21:45.141 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:21:45.141 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:45.141 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:21:45.141 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:21:45.141 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:21:45.141 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:21:45.141 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:45.142 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:21:45.142 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:21:45.142 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:21:45.142 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:45.142 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:21:45.142 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:21:45.142 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:21:45.142 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:21:45.142 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:45.144 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:21:45.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:21:45.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:21:45.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:21:45.144 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:21:45.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:21:45.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:21:45.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:45.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:21:45.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:21:45.144 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:21:45.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:45.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:45.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:45.144 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:45.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:45.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:45.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:45.144 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:21:45.144 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:21:45.144 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:21:45.145 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:45.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:45.149 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:21:45.613 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:21:45.660 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:21:45.661 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:21:45.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:45.661 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:21:45.667 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:45.667 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:45.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:21:45.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:45.678 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:21:45.678 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:21:45.678 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:21:45.678 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:21:45.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:45.704 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:21:45.704 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:21:45.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:45.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:46.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:46.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:46.069 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:46.069 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:46.076 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:46.076 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:46.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:21:46.077 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:21:46.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:46.086 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:21:46.086 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:21:46.086 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:21:46.086 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:21:46.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:46.119 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:21:46.119 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:21:46.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:46.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:46.147 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:46.147 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:46.148 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:46.151 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:46.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:46.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:46.479 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:46.479 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:46.482 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:46.482 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:46.482 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:46.482 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:46.483 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:21:46.483 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:21:46.483 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:21:46.483 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:21:46.483 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:21:46.483 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:21:46.483 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:21:51.485 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:21:51.485 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:21:51.485 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:21:51.485 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:21:51.485 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:21:51.485 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:21:51.492 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:21:51.492 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:21:51.492 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:51.492 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:21:51.492 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:21:51.493 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:21:51.493 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:21:51.493 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:21:51.493 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:51.493 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:21:51.493 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:21:51.493 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:21:51.493 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:21:51.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:51.494 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:21:51.494 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:21:51.495 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:21:51.495 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:51.495 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:21:51.495 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:21:51.495 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:21:51.495 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:21:51.495 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:51.496 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:21:51.496 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:21:51.496 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:21:51.496 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:51.496 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:21:51.496 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:21:51.496 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:21:51.496 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:21:51.496 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:51.498 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:21:51.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:21:51.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:21:51.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:21:51.498 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:21:51.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:21:51.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:21:51.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:51.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:21:51.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:21:51.498 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:21:51.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:51.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:51.498 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:51.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:51.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:51.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:51.498 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:21:51.498 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:21:51.498 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:21:51.499 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:51.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:51.503 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:21:51.968 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:21:52.014 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:21:52.015 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:21:52.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:52.015 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:21:52.022 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:52.022 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:52.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:21:52.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:52.034 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:21:52.034 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:21:52.034 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:21:52.034 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:21:52.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:52.059 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:21:52.059 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:21:52.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:52.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:52.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:52.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:52.423 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:52.423 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:52.429 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:52.429 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:52.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:21:52.431 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:21:52.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:52.440 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:21:52.440 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:21:52.440 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:21:52.440 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:21:52.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:52.473 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:21:52.473 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:21:52.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:52.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:52.501 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:52.502 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:52.505 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:52.506 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:52.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:52.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:52.834 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:52.834 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:52.837 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:52.837 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:52.837 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:52.837 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:52.838 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:21:52.838 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:21:52.838 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:21:52.838 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:21:52.838 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:21:52.838 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:21:52.838 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:21:57.839 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:21:57.840 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:21:57.840 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:21:57.840 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:21:57.840 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:21:57.840 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:21:57.845 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:21:57.845 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:21:57.845 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:57.845 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:21:57.845 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:21:57.846 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:21:57.846 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:21:57.846 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:21:57.846 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:57.846 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:21:57.846 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:21:57.846 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:21:57.846 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:21:57.846 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:57.847 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:21:57.847 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:21:57.847 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:21:57.847 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:57.847 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:21:57.847 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:21:57.847 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:21:57.848 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:21:57.848 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:57.849 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:21:57.849 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:21:57.849 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:21:57.849 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:21:57.849 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:21:57.849 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:21:57.849 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:21:57.849 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:21:57.849 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:21:57.851 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:21:57.851 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:21:57.851 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:57.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:57.852 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:57.852 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:57.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:57.852 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:57.852 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:57.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:57.852 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:21:57.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:57.852 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:57.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:21:57.852 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:21:57.856 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:21:58.322 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:21:58.364 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:21:58.365 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:21:58.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:58.366 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:21:58.373 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:58.373 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:58.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:21:58.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:58.384 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:21:58.384 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:21:58.384 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:21:58.384 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:21:58.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:58.412 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:21:58.412 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:21:58.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:58.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:58.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:58.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:58.778 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:58.778 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:58.783 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:58.783 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:58.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:21:58.785 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:21:58.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:58.793 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:21:58.793 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:21:58.793 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:21:58.793 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:21:58.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:58.828 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:21:58.828 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:21:58.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:58.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:58.853 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:58.854 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:58.855 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:58.855 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:59.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:21:59.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:21:59.230 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:21:59.230 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:21:59.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:21:59.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:21:59.232 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:21:59.232 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:21:59.233 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:21:59.233 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:21:59.233 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:21:59.233 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:21:59.233 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:21:59.233 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:21:59.233 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:22:04.235 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:22:04.235 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:22:04.235 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:22:04.235 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:22:04.235 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:22:04.235 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:22:04.238 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:22:04.239 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:22:04.239 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:04.239 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:22:04.239 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:22:04.240 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:22:04.240 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:22:04.240 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:22:04.240 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:04.240 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:22:04.240 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:22:04.241 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:22:04.241 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:22:04.241 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:04.241 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:22:04.242 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:22:04.242 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:22:04.242 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:04.242 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:22:04.242 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:22:04.242 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:22:04.242 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:22:04.242 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:04.243 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:22:04.243 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:22:04.243 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:22:04.243 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:04.243 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:22:04.243 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:22:04.243 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:22:04.243 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:22:04.243 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:04.245 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:22:04.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:22:04.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:22:04.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:22:04.245 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:22:04.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:22:04.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:22:04.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:04.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:22:04.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:22:04.245 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:22:04.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:04.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:04.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:04.245 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:04.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:04.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:04.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:04.245 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:22:04.245 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:22:04.245 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:22:04.245 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:22:04.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:04.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:04.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:04.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:22:04.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:04.246 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:04.246 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:04.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:04.246 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:04.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:04.246 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:04.246 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:04.246 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:04.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:04.246 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:04.246 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:04.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:04.246 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:04.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:04.246 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:04.246 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:04.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:04.246 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:04.246 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:04.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:04.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:04.250 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:22:04.715 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:22:04.756 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:22:04.756 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:22:04.757 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:22:04.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:22:04.762 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:22:04.762 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:22:04.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:22:04.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:04.772 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:22:04.772 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:22:04.772 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:22:04.772 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:22:04.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:22:04.805 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:22:04.805 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:22:04.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:04.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:05.181 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:22:05.247 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:05.247 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:05.248 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:05.248 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:05.648 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:22:06.111 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:22:06.247 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:06.247 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:06.248 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:06.248 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:06.577 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:22:07.044 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:22:07.248 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:07.248 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:07.249 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:07.249 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:07.510 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:22:07.977 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:22:08.249 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:08.249 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:08.249 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:08.249 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:08.443 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:22:08.807 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:22:08.807 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:22:08.807 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:22:08.807 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:08.807 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:08.807 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:08.807 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:08.808 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:22:08.808 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:22:08.808 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:22:08.808 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:22:08.808 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:22:08.808 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:22:08.808 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:22:13.810 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:22:13.810 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:22:13.810 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:22:13.810 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:22:13.810 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:22:13.810 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:22:13.813 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:22:13.813 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:22:13.813 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:13.813 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:22:13.813 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:22:13.814 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:22:13.814 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:22:13.814 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:22:13.814 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:13.814 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:22:13.814 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:22:13.815 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:22:13.815 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:22:13.815 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:13.816 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:22:13.816 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:22:13.816 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:22:13.816 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:13.816 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:22:13.816 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:22:13.816 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:22:13.816 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:22:13.816 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:13.817 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:22:13.817 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:22:13.817 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:22:13.817 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:13.817 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:22:13.817 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:22:13.817 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:22:13.817 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:22:13.817 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:13.821 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:22:13.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:22:13.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:22:13.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:22:13.821 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:22:13.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:22:13.822 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:22:13.822 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:22:13.822 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:13.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:13.826 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:22:14.292 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:22:14.333 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:22:14.334 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:22:14.334 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:22:14.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:22:14.340 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:22:14.340 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:22:14.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:22:14.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:14.349 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:22:14.349 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:22:14.349 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:22:14.349 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:22:14.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:22:14.385 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:22:14.385 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:22:14.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:14.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:14.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:14.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:22:14.586 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:22:14.586 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:22:14.592 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:22:14.592 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:22:14.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:22:14.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:14.602 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:22:14.602 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:22:14.602 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:22:14.602 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:22:14.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:22:14.618 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:22:14.618 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:22:14.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:14.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:14.755 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:22:14.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:14.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:22:14.817 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:22:14.817 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:22:14.819 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:14.819 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:14.819 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:14.819 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:14.820 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:22:14.820 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:22:14.820 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:22:14.820 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:22:14.820 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:22:14.820 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:22:14.820 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:22:19.821 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:22:19.821 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:22:19.822 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:22:19.822 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:22:19.822 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:22:19.822 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:22:19.825 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:22:19.825 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:22:19.826 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:19.826 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:22:19.826 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:22:19.826 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:22:19.827 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:22:19.827 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:22:19.827 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:19.827 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:22:19.827 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:22:19.827 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:22:19.827 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:22:19.827 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:19.828 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:22:19.828 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:22:19.828 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:22:19.828 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:19.828 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:22:19.828 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:22:19.828 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:22:19.828 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:22:19.828 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:19.829 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:22:19.829 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:22:19.829 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:22:19.829 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:19.829 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:22:19.829 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:22:19.829 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:22:19.829 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:22:19.829 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:19.831 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:22:19.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:22:19.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:22:19.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:22:19.831 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:22:19.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:22:19.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:22:19.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:19.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:22:19.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:22:19.831 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:22:19.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:19.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:19.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:19.831 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:19.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:19.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:19.831 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:22:19.831 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:22:19.831 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:22:19.831 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:22:19.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:19.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:19.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:19.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:22:19.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:19.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:19.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:19.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:19.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:19.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:19.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:19.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:19.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:19.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:19.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:19.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:19.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:19.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:19.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:19.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:19.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:19.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:19.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:19.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:19.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:19.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:19.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:19.836 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:22:20.299 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:22:20.346 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:22:20.346 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:22:20.346 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:22:20.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:22:20.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:22:20.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:22:20.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:22:20.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:20.361 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:22:20.361 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:22:20.361 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:22:20.361 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:22:20.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:22:20.389 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:22:20.389 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:22:20.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:20.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:20.761 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:22:20.833 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:20.833 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:20.834 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:20.834 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:21.224 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:22:21.686 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:22:21.833 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:21.834 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:21.835 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:21.835 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:22.149 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:22:22.611 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:22:22.834 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:22.834 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:22.835 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:22.835 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:23.073 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:22:23.536 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:22:23.834 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:23.835 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:23.836 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:23.836 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:23.999 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:22:24.391 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:22:24.391 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:22:24.391 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:22:24.391 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:24.391 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:24.391 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:24.391 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:24.392 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:22:24.392 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:22:24.392 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:22:24.392 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:22:24.392 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:22:24.392 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:22:24.392 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:22:29.394 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:22:29.394 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:22:29.394 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:22:29.394 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:22:29.394 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:22:29.394 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:22:29.398 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:22:29.398 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:22:29.398 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:29.398 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:22:29.398 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:22:29.399 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:22:29.399 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:22:29.399 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:22:29.399 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:29.399 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:22:29.399 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:22:29.400 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:22:29.400 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:22:29.400 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:29.401 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:22:29.401 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:22:29.401 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:22:29.401 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:29.401 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:22:29.401 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:22:29.401 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:22:29.401 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:22:29.401 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:29.402 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:22:29.402 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:22:29.402 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:22:29.402 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:29.402 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:22:29.402 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:22:29.402 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:22:29.402 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:22:29.402 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:29.404 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:22:29.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:22:29.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:22:29.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:22:29.404 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:22:29.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:22:29.405 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:22:29.405 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:22:29.405 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:29.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:29.409 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:22:29.876 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:22:29.917 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:22:29.917 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:22:29.917 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:22:29.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:22:29.923 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:22:29.923 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:22:29.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:22:29.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:29.932 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:22:29.933 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:22:29.933 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:22:29.933 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:22:29.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:22:29.966 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:22:29.966 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:22:29.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:29.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:30.339 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:22:30.407 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:30.408 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:30.408 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:30.408 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:30.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:30.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:22:30.683 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:22:30.683 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:22:30.685 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:30.685 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:30.685 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:30.685 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:30.685 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:22:30.686 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:22:30.686 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:22:30.686 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:22:30.686 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:22:30.686 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:22:30.686 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:22:35.688 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:22:35.688 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:22:35.688 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:22:35.688 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:22:35.688 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:22:35.688 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:22:35.695 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:22:35.695 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:22:35.695 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:35.695 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:22:35.695 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:22:35.697 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:22:35.697 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:22:35.697 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:22:35.697 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:35.697 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:22:35.697 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:22:35.697 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:22:35.697 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:22:35.698 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:35.700 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:22:35.700 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:22:35.700 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:22:35.700 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:35.700 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:22:35.700 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:22:35.700 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:22:35.700 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:22:35.700 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:35.702 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:22:35.702 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:22:35.702 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:22:35.702 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:35.702 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:22:35.702 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:22:35.702 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:22:35.702 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:22:35.702 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:35.706 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:22:35.706 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:22:35.706 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:22:35.706 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:22:35.706 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:22:35.706 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:22:35.706 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:22:35.706 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:22:35.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:22:35.706 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:35.706 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:35.706 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:22:35.706 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:35.706 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:35.706 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:35.706 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:35.706 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:35.706 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:35.706 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:22:35.706 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:22:35.706 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:22:35.706 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:35.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:35.711 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:22:36.176 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:22:36.226 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:22:36.227 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:22:36.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:22:36.228 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:22:36.239 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:22:36.239 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:22:36.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:22:36.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:36.259 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:22:36.259 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:22:36.259 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:22:36.259 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:22:36.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:22:36.270 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:22:36.270 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:22:36.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:36.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:36.641 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:22:36.710 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:36.710 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:36.711 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:36.714 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:36.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:36.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:22:36.985 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:22:36.985 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:22:36.988 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:36.988 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:36.988 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:36.988 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:36.989 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:22:36.989 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:22:36.989 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:22:36.989 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:22:36.989 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:22:36.989 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:22:36.990 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:22:36.990 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=282 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:22:36.990 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=282 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:22:36.990 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=282 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:22:36.990 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=282 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:22:36.990 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=282 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:22:36.990 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=282 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:22:41.992 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:22:41.992 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:22:41.992 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:22:41.992 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:22:41.992 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:22:41.992 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:22:42.000 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:22:42.001 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:22:42.001 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:42.001 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:22:42.001 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:22:42.003 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:22:42.003 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:22:42.003 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:22:42.003 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:42.003 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:22:42.003 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:22:42.004 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:22:42.004 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:22:42.004 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:42.006 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:22:42.006 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:22:42.006 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:22:42.006 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:42.006 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:22:42.006 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:22:42.006 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:22:42.006 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:22:42.007 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:42.009 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:22:42.009 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:22:42.009 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:22:42.009 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:42.009 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:22:42.009 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:22:42.010 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:22:42.010 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:22:42.010 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:42.014 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:22:42.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:22:42.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:22:42.014 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:22:42.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:22:42.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:22:42.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:22:42.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:22:42.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:42.015 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:22:42.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:42.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:22:42.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:42.015 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:42.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:42.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:42.015 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:22:42.015 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:22:42.015 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:22:42.015 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:22:42.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:42.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:42.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:42.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:22:42.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:42.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:42.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:42.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:42.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:42.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:42.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:42.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:42.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:42.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:42.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:42.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:42.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:42.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:42.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:42.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:42.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:42.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:42.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:42.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:42.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:42.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:42.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:42.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:42.020 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:22:42.485 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:22:42.539 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:22:42.541 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:22:42.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:22:42.542 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:22:42.554 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:22:42.554 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:22:42.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:22:42.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:42.580 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:22:42.580 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:22:42.580 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:22:42.580 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:22:42.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:22:42.627 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:22:42.627 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:22:42.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:42.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:42.950 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:22:43.019 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:43.019 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:43.020 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:43.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:43.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:43.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:22:43.336 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:22:43.336 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:22:43.341 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:43.341 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:43.341 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:43.341 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:43.342 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:22:43.342 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:22:43.343 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:22:43.343 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:22:43.343 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:22:43.343 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:22:43.343 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:22:48.344 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:22:48.344 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:22:48.344 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:22:48.344 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:22:48.344 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:22:48.344 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:22:48.351 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:22:48.352 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:22:48.352 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:48.352 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:22:48.352 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:22:48.354 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:22:48.354 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:22:48.354 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:22:48.354 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:48.354 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:22:48.354 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:22:48.355 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:22:48.355 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:22:48.355 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:48.357 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:22:48.357 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:22:48.357 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:22:48.357 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:48.357 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:22:48.357 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:22:48.358 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:22:48.358 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:22:48.358 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:48.360 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:22:48.360 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:22:48.361 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:22:48.361 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:48.361 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:22:48.361 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:22:48.361 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:22:48.361 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:22:48.361 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:48.365 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:22:48.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:22:48.366 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:22:48.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:22:48.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:22:48.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:22:48.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:22:48.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:48.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:22:48.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:22:48.366 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:22:48.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:48.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:48.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:48.366 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:48.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:48.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:48.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:48.366 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:22:48.366 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:22:48.366 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:22:48.366 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:48.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:48.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:48.371 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:22:48.836 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:22:48.890 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:22:48.891 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:22:48.891 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:22:48.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:22:48.903 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:22:48.903 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:22:48.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:22:48.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:48.927 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:22:48.927 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:22:48.927 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:22:48.927 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:22:48.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:22:48.978 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:22:48.978 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:22:48.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:48.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:49.302 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:22:49.371 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:49.371 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:49.372 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:49.377 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:49.765 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:22:49.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:49.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:22:49.814 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:22:49.814 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:22:49.815 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:22:49.817 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:49.817 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:49.817 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:49.817 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:49.818 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:22:49.818 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:22:49.818 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:22:49.818 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:22:49.818 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:22:49.818 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:22:49.818 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:22:54.820 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:22:54.820 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:22:54.820 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:22:54.820 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:22:54.820 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:22:54.820 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:22:54.826 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:22:54.827 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:22:54.827 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:54.827 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:22:54.827 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:22:54.829 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:22:54.829 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:22:54.829 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:22:54.829 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:54.829 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:22:54.829 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:22:54.829 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:22:54.829 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:22:54.829 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:54.831 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:22:54.831 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:22:54.832 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:22:54.832 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:54.832 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:22:54.832 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:22:54.832 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:22:54.832 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:22:54.832 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:54.834 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:22:54.834 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:22:54.834 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:22:54.834 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:22:54.834 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:22:54.834 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:22:54.834 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:22:54.834 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:22:54.834 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:22:54.838 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:22:54.838 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:22:54.838 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:54.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:54.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:54.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:54.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:54.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:54.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:54.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:54.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:54.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:54.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:54.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:54.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:22:54.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:54.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:54.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:54.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:54.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:22:54.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:54.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:54.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:22:54.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:22:54.843 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:22:55.308 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:22:55.365 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:22:55.366 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:22:55.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:22:55.367 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:22:55.374 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:22:55.375 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:22:55.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:22:55.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:55.384 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:22:55.384 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:22:55.384 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:22:55.384 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:22:55.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:22:55.398 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:22:55.398 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:22:55.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:55.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:55.772 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:22:55.841 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:55.842 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:55.842 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:55.842 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:56.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:22:56.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:22:56.116 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:22:56.116 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:22:56.119 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:22:56.120 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:22:56.120 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:22:56.120 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:22:56.123 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:22:56.124 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:22:56.124 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:22:56.124 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:22:56.124 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:22:56.124 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:22:56.124 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:22:56.124 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=282 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:22:56.124 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=282 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:22:56.124 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=282 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:22:56.124 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=282 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:22:56.124 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=282 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:22:56.124 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=282 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:23:01.126 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:23:01.126 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:23:01.126 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:23:01.126 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:23:01.126 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:23:01.126 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:23:01.135 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:23:01.136 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:23:01.136 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:23:01.136 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:23:01.137 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:23:01.141 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:23:01.141 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:23:01.142 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:23:01.142 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:23:01.142 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:23:01.143 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:23:01.143 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:23:01.143 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:23:01.143 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:01.146 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:23:01.146 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:23:01.147 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:23:01.147 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:23:01.147 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:23:01.147 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:23:01.148 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:23:01.148 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:23:01.148 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:01.150 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:23:01.150 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:23:01.151 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:23:01.151 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:23:01.151 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:23:01.151 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:23:01.151 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:23:01.151 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:23:01.151 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:01.156 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:23:01.157 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:23:01.157 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:23:01.157 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:23:01.157 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:23:01.157 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:23:01.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:23:01.157 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:01.157 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:23:01.157 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:23:01.157 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:23:01.157 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:01.157 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:01.157 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:01.157 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:01.157 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:01.158 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:01.158 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:01.158 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:23:01.158 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:23:01.158 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:23:01.158 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:23:01.158 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:01.158 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:01.158 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:01.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:23:01.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:01.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:01.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:01.159 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:01.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:01.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:01.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:01.159 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:01.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:01.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:01.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:01.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:01.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:01.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:01.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:01.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:01.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:01.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:01.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:01.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:01.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:01.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:01.163 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:23:01.642 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:23:01.687 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:23:01.688 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:23:01.690 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:23:01.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:23:01.705 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:23:01.705 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:23:01.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:23:01.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:23:01.734 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:23:01.734 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:23:01.734 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:23:01.734 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:23:01.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:23:01.791 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:23:01.791 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:23:01.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:23:01.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:23:02.114 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:23:02.163 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:02.163 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:02.163 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:02.163 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:02.586 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:23:02.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:23:02.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:23:02.642 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:23:02.642 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:23:02.642 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:23:02.650 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:02.650 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:02.650 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:02.650 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:02.651 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:23:02.651 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:23:02.651 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:23:02.651 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:23:02.651 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:23:02.651 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:23:02.651 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:23:07.658 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:23:07.658 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:23:07.658 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:23:07.658 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:23:07.658 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:23:07.658 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:23:07.665 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:23:07.666 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:23:07.666 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:23:07.666 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:23:07.667 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:23:07.669 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:23:07.670 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:23:07.670 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:23:07.670 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:23:07.670 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:23:07.671 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:23:07.671 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:23:07.671 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:23:07.671 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:07.672 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:23:07.672 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:23:07.672 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:23:07.672 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:23:07.672 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:23:07.673 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:23:07.673 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:23:07.673 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:23:07.673 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:07.674 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:23:07.674 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:23:07.675 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:23:07.675 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:23:07.675 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:23:07.675 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:23:07.675 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:23:07.675 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:23:07.675 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:07.677 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:23:07.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:23:07.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:23:07.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:23:07.677 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:23:07.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:23:07.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:23:07.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:07.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:23:07.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:23:07.677 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:23:07.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:07.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:07.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:07.677 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:23:07.678 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:23:07.678 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:23:07.678 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:07.682 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:23:08.161 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:23:08.203 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:23:08.205 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:23:08.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:23:08.208 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:23:08.226 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:23:08.226 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:23:08.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:23:08.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:23:08.232 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:23:08.232 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:23:08.232 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:23:08.232 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:23:08.632 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:23:08.679 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:08.680 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:08.680 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:08.681 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:09.104 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:23:09.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:23:09.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:23:09.378 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:23:09.378 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:23:09.396 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:23:09.396 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:23:09.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:23:09.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:23:09.397 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:23:09.397 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:23:09.397 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:23:09.397 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:23:09.577 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:23:09.680 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:09.681 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:09.681 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:09.681 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:10.049 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:23:10.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 03:23:10.521 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:23:10.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 03:23:10.560 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:23:10.560 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:23:10.569 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:10.569 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:10.569 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:10.569 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:10.573 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:23:10.573 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:23:10.573 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:23:10.573 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:23:10.573 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:23:10.573 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:23:10.573 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:23:10.573 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=625 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:23:10.573 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=625 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:23:10.573 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=625 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:23:10.573 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=625 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:23:10.573 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=625 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:23:10.573 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=625 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:23:10.573 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=625 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:23:15.577 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:23:15.577 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:23:15.577 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:23:15.577 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:23:15.577 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:23:15.577 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:23:15.583 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:23:15.584 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:23:15.584 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:23:15.585 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:23:15.585 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:23:15.588 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:23:15.588 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:23:15.589 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:23:15.589 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:23:15.589 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:23:15.590 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:23:15.590 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:23:15.590 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:23:15.591 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:15.593 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:23:15.593 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:23:15.593 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:23:15.594 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:23:15.594 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:23:15.594 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:23:15.595 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:23:15.595 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:23:15.595 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:15.598 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:23:15.598 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:23:15.599 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:23:15.599 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:23:15.599 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:23:15.599 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:23:15.599 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:23:15.599 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:23:15.600 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:15.605 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:23:15.605 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:23:15.605 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:23:15.605 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:23:15.605 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:23:15.605 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:23:15.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:23:15.605 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:15.605 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:23:15.605 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:23:15.605 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:23:15.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:15.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:15.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:15.606 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:15.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:15.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:15.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:15.606 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:23:15.606 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:23:15.606 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:23:15.606 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:23:15.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:15.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:15.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:15.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:23:15.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:15.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:15.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:15.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:15.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:15.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:15.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:15.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:15.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:15.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:15.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:15.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:15.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:15.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:15.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:15.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:15.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:15.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:15.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:15.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:15.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:15.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:15.611 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:23:16.088 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:23:16.133 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:23:16.134 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:23:16.136 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:23:16.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:23:16.150 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:23:16.150 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:23:16.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:23:16.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:23:16.153 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:23:16.153 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:23:16.153 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:23:16.153 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:23:16.560 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:23:16.610 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:16.610 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:16.611 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:16.611 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:17.031 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:23:17.504 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:23:17.612 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:17.612 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:17.612 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:17.612 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:17.977 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:23:18.449 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:23:18.613 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:18.613 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:18.613 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:18.613 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:18.923 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:23:19.395 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:23:19.613 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:19.614 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:19.614 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:19.614 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:19.867 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:23:20.338 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:23:20.614 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:20.614 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:20.615 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:20.615 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:20.811 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:23:21.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 03:23:21.071 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:23:21.071 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:23:21.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:23:21.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:23:21.284 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:23:21.750 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:23:22.217 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:23:22.681 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:23:23.145 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:23:23.616 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:23:24.035 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:23:24.035 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:23:24.039 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:24.039 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:24.039 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:24.039 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:24.039 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:23:24.040 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:23:24.040 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:23:24.040 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:23:24.040 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:23:24.040 [WARNING] transceiver.py:257 (TRX2@172.18.59.20:5700/2) RX TRXD message (ver=1 fn=1828 tn=0 bl=148 pwr=8), but transceiver is not running => dropping...
2026-03-06 03:23:24.040 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:23:24.040 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:23:24.040 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1828 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:23:24.040 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1828 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:23:24.040 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1828 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:23:24.040 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1828 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:23:24.040 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1828 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:23:24.040 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1828 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:23:29.049 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:23:29.050 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:23:29.050 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:23:29.050 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:23:29.050 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:23:29.050 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:23:29.059 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:23:29.061 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:23:29.061 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:23:29.062 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:23:29.062 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:23:29.068 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:23:29.068 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:23:29.069 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:23:29.069 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:23:29.069 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:23:29.070 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:23:29.070 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:23:29.070 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:23:29.071 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:29.072 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:23:29.072 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:23:29.073 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:23:29.073 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:23:29.073 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:23:29.073 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:23:29.074 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:23:29.074 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:23:29.074 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:29.076 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:23:29.076 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:23:29.076 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:23:29.076 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:23:29.077 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:23:29.077 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:23:29.077 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:23:29.077 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:23:29.077 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:29.080 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:23:29.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:23:29.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:23:29.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:23:29.080 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:23:29.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:23:29.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:23:29.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:29.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:23:29.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:23:29.080 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:23:29.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:29.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:29.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:29.080 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:29.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:29.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:29.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:29.080 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:23:29.080 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:23:29.080 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:23:29.081 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:23:29.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:29.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:29.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:29.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:23:29.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:29.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:29.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:29.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:29.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:29.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:29.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:29.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:29.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:29.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:29.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:29.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:29.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:29.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:29.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:29.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:29.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:29.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:29.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:29.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:29.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:29.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:29.085 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:23:29.562 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:23:29.606 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:23:29.608 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:23:29.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:23:29.610 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:23:29.631 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:23:29.631 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:23:29.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:23:29.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:23:29.636 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:23:29.637 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:23:29.637 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:23:29.637 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:23:30.034 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:23:30.083 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:30.083 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:30.084 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:30.084 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:30.505 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:23:30.979 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:23:31.085 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:31.085 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:31.085 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:31.085 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:31.451 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:23:31.923 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:23:32.086 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:32.086 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:32.086 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:32.087 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:32.394 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:23:32.867 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:23:33.086 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:33.087 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:33.087 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:33.088 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:33.340 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:23:33.811 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:23:34.088 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:34.088 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:34.088 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:34.088 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:34.283 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:23:34.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 03:23:34.545 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:23:34.545 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:23:34.545 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:23:34.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:23:34.757 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:23:35.229 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:23:35.698 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:23:36.162 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:23:36.626 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:23:37.090 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:23:37.509 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:23:37.510 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:23:37.514 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:37.514 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:37.514 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:37.514 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:37.515 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:23:37.515 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:23:37.515 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:23:37.515 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:23:37.515 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:23:37.515 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:23:37.515 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:23:42.522 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:23:42.522 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:23:42.522 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:23:42.522 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:23:42.522 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:23:42.522 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:23:42.529 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:23:42.531 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:23:42.531 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:23:42.531 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:23:42.531 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:23:42.535 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:23:42.535 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:23:42.535 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:23:42.535 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:23:42.535 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:23:42.535 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:23:42.535 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:23:42.535 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:23:42.536 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:42.539 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:23:42.539 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:23:42.540 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:23:42.540 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:23:42.540 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:23:42.540 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:23:42.540 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:23:42.540 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:23:42.540 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:42.543 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:23:42.544 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:23:42.544 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:23:42.544 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:23:42.544 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:23:42.544 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:23:42.544 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:23:42.544 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:23:42.545 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:42.550 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:23:42.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:23:42.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:23:42.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:23:42.550 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:23:42.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:23:42.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:23:42.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:42.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:23:42.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:23:42.550 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:23:42.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:42.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:42.551 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:42.551 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:23:42.551 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:23:42.551 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:23:42.551 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:23:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:42.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:23:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:42.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:42.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:42.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:42.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:42.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:42.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:42.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:42.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:42.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:42.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:42.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:42.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:42.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:42.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:42.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:42.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:42.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:42.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:42.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:42.556 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:23:43.032 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:23:43.078 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:23:43.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:23:43.082 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:23:43.084 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:23:43.100 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:23:43.100 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:23:43.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:23:43.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:23:43.102 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:23:43.102 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:23:43.102 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:23:43.102 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:23:43.504 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:23:43.557 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:43.557 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:43.557 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:43.557 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:43.975 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:23:44.449 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:23:44.558 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:44.558 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:44.559 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:44.559 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:44.921 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:23:45.393 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:23:45.559 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:45.559 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:45.559 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:45.560 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:45.864 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:23:46.335 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:23:46.560 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:46.561 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:46.561 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:46.561 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:46.808 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:23:47.280 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:23:47.562 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:47.562 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:47.562 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:47.563 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:47.752 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:23:48.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 03:23:48.013 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:23:48.014 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:23:48.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:23:48.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:23:48.223 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:23:48.692 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:23:49.161 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:23:49.625 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:23:50.089 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:23:50.553 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:23:50.978 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:23:50.978 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:23:50.982 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:50.982 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:50.982 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:50.982 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:50.983 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:23:50.983 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:23:50.983 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:23:50.983 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:23:50.983 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:23:50.983 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:23:50.983 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:23:55.988 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:23:55.988 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:23:55.989 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:23:55.989 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:23:55.989 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:23:55.989 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:23:55.999 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:23:56.000 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:23:56.000 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:23:56.001 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:23:56.001 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:23:56.004 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:23:56.004 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:23:56.004 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:23:56.004 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:23:56.005 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:23:56.005 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:23:56.006 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:23:56.006 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:23:56.006 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:56.007 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:23:56.007 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:23:56.007 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:23:56.007 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:23:56.007 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:23:56.007 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:23:56.008 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:23:56.008 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:23:56.008 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:56.009 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:23:56.010 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:23:56.010 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:23:56.010 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:23:56.010 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:23:56.010 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:23:56.010 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:23:56.010 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:23:56.010 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:56.013 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:23:56.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:23:56.013 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:23:56.013 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:23:56.013 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:23:56.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:23:56.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:23:56.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:56.013 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:23:56.013 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:23:56.013 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:23:56.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:56.013 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:56.013 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:56.013 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:56.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:56.013 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:56.013 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:56.013 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:23:56.013 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:23:56.013 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:23:56.013 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:23:56.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:56.013 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:56.013 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:56.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:23:56.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:56.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:56.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:56.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:56.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:56.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:56.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:56.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:56.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:56.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:56.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:56.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:56.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:56.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:23:56.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:56.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:56.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:56.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:23:56.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:56.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:23:56.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:56.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:23:56.018 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:23:56.495 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:23:56.537 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:23:56.538 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:23:56.540 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:23:56.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:23:56.564 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:23:56.564 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:23:56.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:23:56.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:23:56.569 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:23:56.569 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:23:56.570 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:23:56.570 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:23:56.967 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:23:57.016 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:57.016 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:57.016 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:57.016 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:57.439 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:23:57.910 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:23:58.017 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:58.017 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:58.017 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:58.018 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:58.383 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:23:58.855 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:23:59.018 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:23:59.018 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:23:59.018 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:23:59.018 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:23:59.327 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:23:59.798 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:24:00.019 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:00.019 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:00.019 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:00.019 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:00.272 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:24:00.744 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:24:01.020 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:01.020 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:01.020 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:01.020 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:01.215 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:24:01.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 03:24:01.476 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:24:01.477 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:24:01.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:24:01.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:24:01.687 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:24:02.161 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:24:02.633 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:24:03.107 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:24:03.579 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:24:04.048 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:24:04.440 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:24:04.441 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:24:04.445 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:04.445 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:04.445 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:04.445 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:04.445 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:24:04.445 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:24:04.445 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:24:04.446 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:24:04.446 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:24:04.446 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:24:04.446 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:24:09.452 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:24:09.452 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:24:09.452 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:24:09.452 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:24:09.452 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:24:09.452 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:24:09.460 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:24:09.462 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:24:09.462 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:24:09.463 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:24:09.463 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:24:09.468 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:24:09.469 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:24:09.469 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:24:09.469 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:24:09.469 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:24:09.469 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:24:09.469 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:24:09.470 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:24:09.470 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:09.474 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:24:09.474 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:24:09.474 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:24:09.474 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:24:09.474 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:24:09.474 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:24:09.474 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:24:09.474 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:24:09.475 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:09.478 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:24:09.478 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:24:09.479 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:24:09.479 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:24:09.479 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:24:09.479 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:24:09.479 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:24:09.479 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:24:09.479 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:09.485 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:24:09.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:24:09.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:24:09.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:24:09.485 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:24:09.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:24:09.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:24:09.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:24:09.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:24:09.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:09.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:09.485 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:24:09.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:09.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:09.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:09.486 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:09.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:09.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:09.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:09.486 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:24:09.486 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:24:09.486 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:24:09.486 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:24:09.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:09.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:09.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:09.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:24:09.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:09.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:09.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:09.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:09.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:09.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:09.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:09.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:09.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:09.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:09.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:09.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:09.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:09.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:09.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:09.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:09.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:09.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:09.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:09.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:09.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:09.491 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:24:09.970 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:24:10.023 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:24:10.025 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:24:10.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:24:10.028 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:24:10.047 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:24:10.047 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:24:10.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:24:10.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:24:10.050 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:24:10.050 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:24:10.050 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:24:10.050 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:24:10.442 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:24:10.490 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:10.490 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:10.490 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:10.492 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:10.913 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:24:11.386 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:24:11.492 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:11.492 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:11.492 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:11.492 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:11.859 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:24:12.331 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:24:12.492 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:12.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:12.493 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:12.493 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:12.802 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:24:13.275 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:24:13.493 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:13.494 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:13.494 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:13.494 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:13.748 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:24:14.219 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:24:14.494 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:14.495 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:14.495 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:14.495 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:14.690 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:24:14.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD NOHANDOVER
2026-03-06 03:24:14.951 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:24:14.951 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:24:14.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:24:14.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:24:15.164 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:24:15.637 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:24:16.109 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:24:16.583 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:24:17.055 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:24:17.527 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:24:17.915 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:24:17.915 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:24:17.920 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:17.921 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:17.921 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:17.921 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:17.923 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:24:17.923 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:24:17.923 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:24:17.923 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:24:17.923 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:24:17.923 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:24:17.923 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:24:17.923 [WARNING] transceiver.py:257 (TRX2@172.18.59.20:5700/2) RX TRXD message (ver=1 fn=1822 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:24:17.923 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1821 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:24:17.923 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1821 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:24:17.923 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1822 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:24:17.923 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1822 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:24:17.923 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1822 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:24:17.923 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1822 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:24:17.923 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1822 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:24:17.923 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1822 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:24:17.923 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1822 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:24:17.923 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1822 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:24:22.928 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:24:22.928 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:24:22.928 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:24:22.928 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:24:22.928 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:24:22.928 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:24:22.935 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:24:22.936 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:24:22.936 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:24:22.937 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:24:22.937 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:24:22.939 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:24:22.939 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:24:22.939 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:24:22.939 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:24:22.940 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:24:22.940 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:24:22.940 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:24:22.940 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:24:22.940 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:22.941 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:24:22.941 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:24:22.942 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:24:22.942 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:24:22.942 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:24:22.942 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:24:22.942 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:24:22.942 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:24:22.942 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:22.944 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:24:22.944 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:24:22.944 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:24:22.944 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:24:22.944 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:24:22.944 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:24:22.944 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:24:22.944 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:24:22.944 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:22.946 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:24:22.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:24:22.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:24:22.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:24:22.946 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:24:22.947 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:24:22.947 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:24:22.947 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:22.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:22.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:22.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:22.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:22.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:22.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:22.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:22.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:22.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:22.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:22.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:22.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:22.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:22.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:22.952 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:24:23.429 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:24:23.470 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:24:23.472 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:24:23.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:24:23.474 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:24:23.901 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:24:23.949 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:23.950 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:23.950 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:23.950 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:24.375 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:24:24.843 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:24:24.951 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:24.951 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:24.951 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:24.952 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:25.322 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:24:25.794 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:24:25.952 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:25.953 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:25.953 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:25.953 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:26.265 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:24:26.740 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:24:26.954 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:26.954 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:26.954 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:26.954 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:27.216 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:24:27.687 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:24:27.955 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:27.955 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:27.955 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:27.956 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:28.159 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:24:28.625 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:24:29.089 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:24:29.562 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:24:30.034 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:24:30.505 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:24:30.980 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:24:31.452 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:24:31.928 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:24:32.399 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:24:32.873 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:24:33.342 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:24:33.489 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:33.490 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:33.490 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:33.490 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:33.491 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:24:33.491 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:24:33.491 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:24:33.491 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:24:33.491 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:24:33.491 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:24:33.491 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:24:38.497 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:24:38.497 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:24:38.497 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:24:38.497 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:24:38.497 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:24:38.497 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:24:38.505 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:24:38.507 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:24:38.507 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:24:38.507 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:24:38.507 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:24:38.512 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:24:38.513 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:24:38.513 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:24:38.513 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:24:38.513 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:24:38.514 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:24:38.514 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:24:38.514 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:24:38.514 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:38.516 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:24:38.516 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:24:38.516 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:24:38.516 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:24:38.516 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:24:38.516 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:24:38.517 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:24:38.517 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:24:38.517 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:38.519 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:24:38.519 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:24:38.519 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:24:38.519 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:24:38.519 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:24:38.519 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:24:38.519 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:24:38.519 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:24:38.519 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:38.522 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:24:38.522 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:24:38.522 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:24:38.522 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:24:38.522 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:24:38.522 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:24:38.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:24:38.522 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:38.522 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:24:38.522 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:24:38.522 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:24:38.522 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:38.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:38.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:38.523 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:38.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:38.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:38.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:38.523 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:24:38.523 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:24:38.523 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:24:38.523 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:24:38.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:38.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:38.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:38.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:24:38.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:38.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:38.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:38.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:38.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:38.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:38.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:38.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:38.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:38.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:38.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:38.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:38.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:38.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:38.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:38.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:38.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:38.524 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:24:38.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:38.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:38.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:38.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:38.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:38.524 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:24:38.524 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:24:38.524 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:24:38.524 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:24:38.524 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:24:38.524 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:24:43.532 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:24:43.532 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:24:43.532 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:24:43.532 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:24:43.532 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:24:43.532 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:24:43.543 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:24:43.543 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:24:43.543 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:24:43.543 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:24:43.543 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:24:43.544 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:24:43.545 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:24:43.545 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:24:43.545 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:24:43.545 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:24:43.545 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:24:43.545 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:24:43.545 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:24:43.546 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:43.547 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:24:43.547 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:24:43.547 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:24:43.547 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:24:43.547 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:24:43.547 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:24:43.547 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:24:43.547 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:24:43.547 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:43.549 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:24:43.549 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:24:43.549 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:24:43.549 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:24:43.549 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:24:43.549 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:24:43.549 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:24:43.549 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:24:43.549 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:24:43.551 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:24:43.551 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:24:43.551 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:43.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:43.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:43.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:43.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:43.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:43.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:43.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:43.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:43.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:43.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:43.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:43.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:43.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:43.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:43.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:43.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:43.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:43.556 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:24:44.035 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:24:44.077 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:24:44.078 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:24:44.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:24:44.078 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:24:44.079 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:24:44.079 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:24:44.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:24:44.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:24:44.081 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:24:44.082 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:24:44.082 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:24:44.082 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:24:44.507 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:24:44.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:44.554 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:44.555 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:44.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:44.978 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:24:45.452 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:24:45.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:45.555 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:45.555 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:45.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:45.924 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:24:46.396 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:24:46.555 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:46.556 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:46.556 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:46.556 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:46.867 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:24:47.340 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:24:47.557 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:47.557 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:47.557 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:47.557 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:47.812 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:24:48.284 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:24:48.558 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:48.559 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:48.559 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:48.559 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:48.755 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:24:49.229 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:24:49.701 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:24:50.173 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:24:50.644 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:24:51.118 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:24:51.590 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:24:52.062 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:24:52.131 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:24:52.131 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:24:52.135 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:52.136 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:52.136 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:52.136 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:52.137 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:24:52.137 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:24:52.137 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:24:52.137 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:24:52.137 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:24:52.137 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:24:52.137 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:24:52.137 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1854 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:24:57.147 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:24:57.148 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:24:57.148 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:24:57.148 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:24:57.148 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:24:57.148 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:24:57.158 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:24:57.158 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:24:57.158 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:24:57.158 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:24:57.158 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:24:57.160 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:24:57.160 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:24:57.160 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:24:57.160 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:24:57.161 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:24:57.161 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:24:57.161 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:24:57.161 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:24:57.161 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:24:57.161 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:24:57.162 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:24:57.162 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:24:57.162 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:24:57.162 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:24:57.162 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:24:57.162 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:24:57.162 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:24:57.162 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:24:57.163 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:24:57.163 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:24:57.163 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:24:57.163 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:24:57.163 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:24:57.163 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:24:57.163 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:24:57.163 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:24:57.163 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:24:57.165 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:24:57.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:24:57.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:24:57.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:24:57.165 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:24:57.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:24:57.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:24:57.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:57.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:24:57.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:24:57.165 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:24:57.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:57.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:57.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:57.165 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:24:57.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:57.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:57.165 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:24:57.165 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:24:57.165 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:24:57.165 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:24:57.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:57.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:57.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:57.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:24:57.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:57.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:57.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:57.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:57.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:57.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:57.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:57.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:57.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:57.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:57.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:57.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:24:57.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:57.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:57.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:57.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:57.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:57.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:24:57.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:57.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:57.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:57.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:24:57.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:24:57.167 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:24:57.167 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:24:57.167 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:24:57.167 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:24:57.167 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:24:57.167 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:24:57.167 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:25:02.180 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:25:02.180 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:25:02.180 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:25:02.180 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:25:02.180 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:25:02.180 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:25:02.187 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:25:02.188 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:25:02.188 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:02.188 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:25:02.188 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:25:02.190 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:25:02.190 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:25:02.190 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:25:02.190 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:02.190 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:25:02.190 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:25:02.190 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:25:02.190 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:25:02.190 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:02.192 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:25:02.192 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:25:02.192 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:25:02.192 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:02.192 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:25:02.192 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:25:02.192 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:25:02.192 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:25:02.192 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:02.194 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:25:02.194 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:25:02.194 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:25:02.194 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:02.194 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:25:02.194 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:25:02.194 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:25:02.194 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:25:02.194 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:02.197 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:25:02.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:25:02.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:25:02.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:25:02.197 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:25:02.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:25:02.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:25:02.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:02.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:25:02.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:25:02.197 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:25:02.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:02.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:02.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:02.197 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:02.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:02.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:02.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:02.197 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:25:02.197 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:25:02.197 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:25:02.197 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:02.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:02.202 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:25:02.682 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:25:02.724 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:25:02.726 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:25:02.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:25:02.729 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:25:02.732 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:25:02.732 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:25:02.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:25:02.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:25:02.733 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:25:02.733 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:25:02.733 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:25:02.733 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:25:03.154 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:25:03.200 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:03.200 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:03.201 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:03.201 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:03.625 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:25:04.099 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:25:04.202 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:04.202 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:04.202 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:04.202 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:04.571 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:25:05.043 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:25:05.203 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:05.203 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:05.203 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:05.204 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:05.514 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:25:05.987 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:25:06.204 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:06.205 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:06.205 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:06.205 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:06.460 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:25:06.932 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:25:07.206 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:07.206 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:07.206 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:07.206 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:07.406 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:25:07.878 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:25:08.349 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:25:08.821 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:25:09.294 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:25:09.766 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:25:10.239 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:25:10.709 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:25:10.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:25:10.777 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:25:10.779 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:10.779 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:10.779 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:10.779 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:10.780 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:25:10.780 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:25:10.780 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:25:10.780 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:25:10.780 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:25:10.780 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:25:10.780 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:25:15.786 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:25:15.786 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:25:15.786 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:25:15.786 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:25:15.786 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:25:15.786 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:25:15.795 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:25:15.797 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:25:15.797 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:15.797 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:25:15.797 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:25:15.803 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:25:15.803 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:25:15.804 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:25:15.804 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:15.804 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:25:15.804 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:25:15.805 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:25:15.805 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:25:15.805 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:15.807 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:25:15.808 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:25:15.808 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:25:15.808 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:15.808 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:25:15.809 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:25:15.809 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:25:15.809 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:25:15.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:15.811 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:25:15.811 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:25:15.811 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:25:15.811 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:15.811 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:25:15.811 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:25:15.811 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:25:15.811 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:25:15.811 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:15.815 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:25:15.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:25:15.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:25:15.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:25:15.815 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:25:15.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:25:15.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:25:15.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:15.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:25:15.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:25:15.815 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:25:15.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:15.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:15.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:15.815 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:15.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:15.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:15.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:15.815 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:25:15.815 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:25:15.815 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:25:15.815 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:25:15.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:15.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:15.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:15.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:25:15.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:15.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:15.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:15.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:15.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:15.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:15.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:15.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:15.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:15.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:15.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:15.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:15.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:15.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:15.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:15.817 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:25:15.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:15.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:15.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:15.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:15.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:15.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:15.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:15.817 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:25:15.817 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:25:15.817 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:25:15.817 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:25:15.817 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:25:15.817 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:25:20.825 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:25:20.825 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:25:20.825 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:25:20.825 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:25:20.825 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:25:20.825 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:25:20.833 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:25:20.835 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:25:20.835 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:20.835 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:25:20.835 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:25:20.838 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:25:20.839 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:25:20.839 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:25:20.839 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:20.839 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:25:20.840 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:25:20.840 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:25:20.840 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:25:20.840 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:20.842 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:25:20.842 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:25:20.842 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:25:20.842 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:20.842 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:25:20.842 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:25:20.842 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:25:20.842 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:25:20.842 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:20.844 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:25:20.844 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:25:20.844 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:25:20.844 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:20.844 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:25:20.844 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:25:20.845 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:25:20.845 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:25:20.845 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:20.847 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:25:20.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:25:20.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:25:20.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:25:20.847 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:25:20.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:25:20.848 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:25:20.848 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:25:20.848 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:20.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:20.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:20.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:20.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:20.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:20.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:20.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:20.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:20.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:20.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:20.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:20.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:20.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:20.853 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:25:21.331 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:25:21.376 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:25:21.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:25:21.380 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:25:21.382 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:25:21.385 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:25:21.385 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:25:21.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:25:21.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:25:21.386 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:25:21.386 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:25:21.386 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:25:21.386 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:25:21.803 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:25:21.850 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:21.850 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:21.850 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:21.851 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:22.274 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:25:22.748 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:25:22.851 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:22.851 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:22.851 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:22.852 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:23.221 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:25:23.693 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:25:23.852 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:23.852 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:23.853 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:23.853 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:24.166 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:25:24.639 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:25:24.854 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:24.854 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:24.854 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:24.854 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:25.110 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:25:25.582 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:25:25.855 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:25.856 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:25.856 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:25.856 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:26.055 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:25:26.527 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:25:26.999 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:25:27.473 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:25:27.945 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:25:28.417 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:25:28.888 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:25:29.362 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:25:29.425 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:25:29.425 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:25:29.430 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:29.430 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:29.431 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:29.431 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:29.433 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:25:29.433 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:25:29.433 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:25:29.433 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:25:29.433 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:25:29.433 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:25:29.433 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:25:29.433 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1854 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:25:29.433 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1854 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:25:29.433 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1854 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:25:29.433 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1854 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:25:29.433 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1854 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:25:29.433 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1854 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:25:34.437 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:25:34.437 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:25:34.437 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:25:34.437 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:25:34.437 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:25:34.437 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:25:34.449 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:25:34.449 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:25:34.450 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:34.450 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:25:34.450 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:25:34.452 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:25:34.452 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:25:34.452 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:25:34.452 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:34.452 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:25:34.453 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:25:34.453 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:25:34.453 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:25:34.453 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:34.455 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:25:34.455 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:25:34.455 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:25:34.455 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:34.455 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:25:34.455 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:25:34.455 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:25:34.455 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:25:34.455 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:34.457 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:25:34.457 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:25:34.457 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:25:34.457 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:34.457 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:25:34.457 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:25:34.457 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:25:34.457 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:25:34.457 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:34.459 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:25:34.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:25:34.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:25:34.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:25:34.459 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:25:34.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:25:34.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:25:34.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:34.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:25:34.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:25:34.459 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:25:34.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:34.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:34.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:34.459 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:34.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:34.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:34.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:34.459 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:25:34.459 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:25:34.459 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:25:34.459 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:25:34.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:34.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:34.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:34.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:25:34.460 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:34.460 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:34.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:34.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:34.460 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:34.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:34.460 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:34.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:34.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:34.460 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:34.460 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:34.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:34.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:34.460 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:34.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:34.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:34.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:34.461 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:25:34.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:34.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:34.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:34.461 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:25:34.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:34.461 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:25:34.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:34.461 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:25:34.461 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:25:34.461 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:25:34.461 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:25:39.467 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:25:39.467 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:25:39.467 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:25:39.467 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:25:39.467 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:25:39.467 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:25:39.478 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:25:39.479 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:25:39.479 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:39.480 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:25:39.480 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:25:39.483 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:25:39.483 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:25:39.483 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:25:39.483 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:39.484 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:25:39.484 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:25:39.484 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:25:39.484 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:25:39.485 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:39.486 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:25:39.486 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:25:39.486 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:25:39.486 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:39.486 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:25:39.486 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:25:39.486 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:25:39.486 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:25:39.486 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:39.488 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:25:39.488 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:25:39.488 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:25:39.488 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:39.488 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:25:39.488 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:25:39.488 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:25:39.488 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:25:39.489 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:39.491 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:25:39.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:25:39.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:25:39.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:25:39.491 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:25:39.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:25:39.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:25:39.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:39.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:25:39.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:25:39.491 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:25:39.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:39.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:39.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:39.491 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:39.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:39.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:39.491 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:25:39.491 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:25:39.491 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:25:39.491 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:25:39.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:39.496 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:25:39.974 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:25:40.019 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:25:40.022 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:25:40.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:25:40.024 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:25:40.025 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:25:40.025 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:25:40.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:25:40.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:25:40.026 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:25:40.026 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:25:40.027 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:25:40.027 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:25:40.445 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:25:40.494 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:40.494 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:40.494 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:40.494 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:40.917 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:25:41.388 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:25:41.495 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:41.495 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:41.495 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:41.496 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:41.861 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:25:42.333 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:25:42.496 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:42.497 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:42.497 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:42.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:42.805 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:25:43.276 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:25:43.497 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:43.497 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:43.498 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:43.498 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:43.750 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:25:44.222 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:25:44.497 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:44.498 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:44.498 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:44.498 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:44.694 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:25:45.165 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:25:45.638 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:25:46.111 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:25:46.583 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:25:47.054 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:25:47.527 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:25:47.999 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:25:48.068 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:25:48.068 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:25:48.071 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:48.071 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:48.071 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:48.071 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:48.072 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:25:48.072 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:25:48.072 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:25:48.072 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:25:48.072 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:25:48.072 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:25:48.072 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:25:53.079 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:25:53.079 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:25:53.079 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:25:53.079 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:25:53.079 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:25:53.079 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:25:53.087 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:25:53.089 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:25:53.089 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:53.090 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:25:53.090 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:25:53.094 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:25:53.094 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:25:53.095 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:25:53.095 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:53.095 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:25:53.096 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:25:53.096 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:25:53.096 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:25:53.096 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:53.098 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:25:53.098 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:25:53.098 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:25:53.098 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:53.098 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:25:53.098 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:25:53.098 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:25:53.098 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:25:53.099 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:53.101 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:25:53.101 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:25:53.101 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:25:53.101 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:53.101 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:25:53.101 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:25:53.101 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:25:53.101 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:25:53.101 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:53.104 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:25:53.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:25:53.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:25:53.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:25:53.104 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:25:53.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:25:53.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:25:53.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:53.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:25:53.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:25:53.104 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:25:53.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:53.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:53.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:53.104 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:53.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:53.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:53.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:53.105 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:25:53.105 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:25:53.105 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:25:53.105 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:25:53.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:53.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:53.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:53.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:25:53.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:53.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:53.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:53.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:53.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:53.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:53.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:53.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:53.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:53.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:53.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:53.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:53.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:53.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:53.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:53.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:53.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:53.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:53.106 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:25:53.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:53.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:53.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:53.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:53.106 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:25:53.106 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:25:53.106 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:25:53.106 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:25:53.106 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:25:53.106 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:25:58.113 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:25:58.113 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:25:58.113 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:25:58.113 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:25:58.113 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:25:58.113 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:25:58.120 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:25:58.121 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:25:58.121 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:58.122 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:25:58.122 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:25:58.125 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:25:58.125 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:25:58.125 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:25:58.126 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:58.126 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:25:58.126 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:25:58.127 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:25:58.127 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:25:58.127 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:58.128 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:25:58.128 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:25:58.128 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:25:58.128 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:58.128 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:25:58.129 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:25:58.129 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:25:58.129 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:25:58.129 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:58.131 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:25:58.131 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:25:58.131 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:25:58.131 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:25:58.131 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:25:58.131 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:25:58.132 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:25:58.132 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:25:58.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:58.135 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:25:58.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:25:58.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:25:58.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:25:58.135 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:25:58.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:25:58.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:25:58.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:58.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:25:58.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:25:58.136 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:25:58.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:58.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:58.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:58.136 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:58.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:58.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:58.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:58.136 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:25:58.136 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:25:58.136 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:25:58.136 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:25:58.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:58.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:58.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:58.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:25:58.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:58.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:58.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:58.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:58.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:58.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:58.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:58.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:58.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:58.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:58.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:58.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:58.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:58.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:58.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:25:58.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:58.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:58.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:58.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:25:58.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:25:58.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:58.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:25:58.141 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:25:58.619 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:25:58.667 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:25:58.670 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:25:58.672 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:25:58.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:25:58.675 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:25:58.675 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:25:58.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:25:58.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:25:58.676 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:25:58.676 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:25:58.676 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:25:58.676 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:25:59.091 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:25:59.140 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:25:59.140 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:25:59.140 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:25:59.140 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:25:59.562 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:26:00.035 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:26:00.141 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:26:00.142 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:26:00.142 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:26:00.142 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:26:00.508 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:26:00.980 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:26:01.143 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:26:01.143 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:26:01.143 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:26:01.143 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:26:01.451 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:26:01.924 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:26:02.144 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:26:02.145 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:26:02.145 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:26:02.145 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:26:02.396 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:26:02.868 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:26:03.145 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:26:03.145 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:26:03.146 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:26:03.146 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:26:03.339 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:26:03.813 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:26:04.285 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:26:04.757 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:26:05.228 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:26:05.701 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:26:06.174 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:26:06.646 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:26:07.116 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:26:07.587 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:26:08.060 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:26:08.533 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:26:09.005 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:26:09.476 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:26:09.949 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:26:10.422 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:26:10.893 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:26:11.364 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:26:11.838 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:26:12.310 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:26:12.713 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:26:12.713 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:26:12.718 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:26:12.718 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:26:12.718 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:26:12.718 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:26:12.722 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:26:12.723 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:26:12.723 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:26:12.723 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:26:12.723 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:26:12.723 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:26:12.723 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:26:12.723 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3151 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:26:12.723 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3151 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:26:12.723 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3151 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:26:12.723 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3151 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:26:12.723 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3151 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:26:12.723 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3151 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:26:17.724 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:26:17.725 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:26:17.725 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:26:17.725 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:26:17.725 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:26:17.725 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:26:17.728 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:26:17.728 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:26:17.728 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:26:17.728 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:26:17.728 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:26:17.729 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:26:17.729 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:26:17.729 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:26:17.729 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:26:17.729 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:26:17.729 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:26:17.730 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:26:17.730 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:26:17.730 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:26:17.730 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:26:17.730 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:26:17.730 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:26:17.730 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:26:17.730 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:26:17.730 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:26:17.730 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:26:17.730 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:26:17.730 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:26:17.732 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:26:17.732 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:26:17.732 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:26:17.732 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:26:17.732 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:26:17.732 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:26:17.732 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:26:17.732 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:26:17.732 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:26:17.734 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:26:17.734 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:26:17.734 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:17.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:17.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:17.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:17.735 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:26:17.735 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:26:17.735 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:26:17.735 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:26:17.736 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:26:17.736 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:26:17.736 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:26:22.744 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:26:22.744 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:26:22.744 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:26:22.744 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:26:22.744 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:26:22.744 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:26:22.750 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:26:22.751 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:26:22.751 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:26:22.752 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:26:22.752 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:26:22.755 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:26:22.756 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:26:22.756 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:26:22.756 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:26:22.756 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:26:22.757 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:26:22.757 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:26:22.757 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:26:22.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:26:22.759 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:26:22.759 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:26:22.759 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:26:22.759 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:26:22.759 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:26:22.759 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:26:22.759 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:26:22.759 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:26:22.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:26:22.761 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:26:22.761 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:26:22.762 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:26:22.762 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:26:22.762 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:26:22.762 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:26:22.762 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:26:22.762 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:26:22.762 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:26:22.765 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:26:22.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:26:22.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:26:22.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:26:22.765 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:26:22.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:26:22.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:26:22.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:22.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:26:22.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:26:22.765 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:26:22.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:22.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:22.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:22.765 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:26:22.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:22.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:22.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:22.765 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:26:22.765 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:26:22.765 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:26:22.765 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:22.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:22.770 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:26:23.249 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:26:23.297 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:26:23.299 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:26:23.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:26:23.302 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:26:23.305 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:26:23.305 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:26:23.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:26:23.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:26:23.306 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:26:23.306 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:26:23.306 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:26:23.306 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:26:23.721 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:26:23.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:26:23.768 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:26:23.769 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:26:23.769 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:26:24.192 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:26:24.664 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:26:24.769 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:26:24.769 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:26:24.770 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:26:24.770 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:26:25.137 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:26:25.609 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:26:25.770 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:26:25.770 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:26:25.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:26:25.771 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:26:26.081 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:26:26.552 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:26:26.772 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:26:26.772 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:26:26.772 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:26:26.772 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:26:27.023 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:26:27.496 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:26:27.773 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:26:27.773 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:26:27.774 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:26:27.774 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:26:27.968 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:26:28.440 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:26:28.911 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:26:29.385 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:26:29.857 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:26:30.329 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:26:30.802 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:26:31.274 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:26:31.344 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:26:31.344 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:26:31.346 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:26:31.346 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:26:31.346 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:26:31.346 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:26:31.347 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:26:31.347 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:26:31.347 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:26:31.347 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:26:31.347 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:26:31.347 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:26:31.347 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:26:36.354 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:26:36.354 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:26:36.354 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:26:36.354 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:26:36.354 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:26:36.355 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:26:36.363 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:26:36.365 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:26:36.365 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:26:36.365 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:26:36.365 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:26:36.369 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:26:36.369 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:26:36.369 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:26:36.369 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:26:36.370 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:26:36.370 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:26:36.371 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:26:36.371 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:26:36.371 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:26:36.372 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:26:36.372 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:26:36.373 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:26:36.373 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:26:36.373 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:26:36.373 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:26:36.373 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:26:36.373 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:26:36.373 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:26:36.375 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:26:36.375 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:26:36.375 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:26:36.375 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:26:36.375 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:26:36.375 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:26:36.376 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:26:36.376 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:26:36.376 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:26:36.379 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:26:36.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:26:36.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:26:36.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:26:36.379 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:26:36.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:26:36.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:26:36.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:36.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:26:36.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:26:36.379 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:26:36.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:36.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:36.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:36.379 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:26:36.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:36.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:36.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:36.379 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:26:36.379 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:26:36.379 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:26:36.379 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:26:36.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:36.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:36.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:36.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:26:36.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:36.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:36.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:36.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:36.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:36.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:36.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:36.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:36.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:36.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:36.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:36.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:36.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:36.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:36.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:36.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:36.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:36.381 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:26:36.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:36.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:36.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:36.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:36.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:36.381 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:26:36.381 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:26:36.381 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:26:36.381 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:26:36.381 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:26:36.381 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:26:41.388 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:26:41.388 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:26:41.388 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:26:41.389 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:26:41.389 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:26:41.389 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:26:41.396 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:26:41.397 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:26:41.397 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:26:41.398 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:26:41.398 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:26:41.400 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:26:41.401 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:26:41.401 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:26:41.401 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:26:41.401 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:26:41.402 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:26:41.402 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:26:41.402 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:26:41.402 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:26:41.403 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:26:41.403 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:26:41.403 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:26:41.403 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:26:41.403 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:26:41.403 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:26:41.404 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:26:41.404 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:26:41.404 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:26:41.405 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:26:41.405 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:26:41.405 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:26:41.405 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:26:41.406 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:26:41.406 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:26:41.406 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:26:41.406 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:26:41.406 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:26:41.408 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:26:41.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:26:41.408 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:26:41.408 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:26:41.408 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:26:41.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:26:41.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:26:41.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:41.408 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:26:41.408 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:26:41.408 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:26:41.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:41.408 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:41.408 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:41.408 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:26:41.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:26:41.409 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:26:41.409 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:26:41.409 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:41.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:41.413 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:26:41.892 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:26:41.933 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:26:41.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:26:41.937 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:26:41.940 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:26:41.944 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:26:41.944 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:26:41.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:26:41.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:26:41.945 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:26:41.945 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:26:41.945 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:26:41.945 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:26:42.364 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:26:42.410 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:26:42.411 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:26:42.411 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:26:42.411 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:26:42.835 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:26:43.309 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:26:43.411 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:26:43.412 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:26:43.412 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:26:43.412 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:26:43.781 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:26:44.253 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:26:44.412 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:26:44.412 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:26:44.413 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:26:44.413 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:26:44.724 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:26:45.198 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:26:45.413 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:26:45.414 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:26:45.414 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:26:45.414 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:26:45.670 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:26:46.142 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:26:46.414 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:26:46.414 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:26:46.415 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:26:46.415 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:26:46.613 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:26:47.084 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:26:47.557 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:26:48.030 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:26:48.502 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:26:48.973 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:26:49.446 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:26:49.918 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:26:50.390 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:26:50.861 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:26:51.335 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:26:51.807 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:26:51.992 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:26:51.992 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:26:51.997 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:26:51.997 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:26:51.998 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:26:51.998 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:26:52.001 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:26:52.002 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:26:52.002 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:26:52.002 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:26:52.002 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:26:52.002 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:26:52.002 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:26:52.003 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2288 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:26:52.003 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2288 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:26:52.003 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2288 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:26:52.003 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2288 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:26:52.003 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2288 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:26:52.003 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2288 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:26:57.006 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:26:57.007 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:26:57.007 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:26:57.007 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:26:57.007 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:26:57.007 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:26:57.015 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:26:57.017 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:26:57.017 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:26:57.018 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:26:57.018 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:26:57.022 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:26:57.022 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:26:57.022 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:26:57.022 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:26:57.023 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:26:57.023 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:26:57.023 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:26:57.023 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:26:57.023 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:26:57.026 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:26:57.026 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:26:57.027 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:26:57.027 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:26:57.027 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:26:57.027 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:26:57.027 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:26:57.027 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:26:57.027 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:26:57.030 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:26:57.030 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:26:57.030 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:26:57.030 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:26:57.030 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:26:57.030 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:26:57.031 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:26:57.031 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:26:57.031 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:26:57.034 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:26:57.034 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:26:57.034 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:26:57.034 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:26:57.034 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:26:57.034 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:26:57.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:26:57.034 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:57.034 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:26:57.034 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:26:57.034 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:26:57.034 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:57.034 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:57.034 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:26:57.034 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:57.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:57.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:57.035 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:26:57.035 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:26:57.035 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:26:57.035 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:26:57.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:57.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:57.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:57.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:26:57.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:57.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:57.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:57.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:57.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:57.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:57.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:57.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:57.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:57.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:57.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:57.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:57.036 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:26:57.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:57.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:57.036 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:26:57.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:57.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:57.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:57.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:57.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:26:57.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:26:57.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:26:57.036 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:26:57.036 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:26:57.036 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:26:57.036 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:26:57.037 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:26:57.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:02.043 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:27:02.043 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:27:02.043 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:27:02.043 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:27:02.043 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:27:02.043 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:27:02.050 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:27:02.051 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:27:02.052 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:27:02.052 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:27:02.052 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:27:02.056 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:27:02.056 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:27:02.056 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:27:02.056 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:27:02.056 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:27:02.057 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:27:02.057 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:27:02.057 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:27:02.057 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:27:02.060 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:27:02.060 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:27:02.060 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:27:02.061 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:27:02.061 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:27:02.061 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:27:02.061 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:27:02.062 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:27:02.062 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:27:02.063 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:27:02.063 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:27:02.063 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:27:02.063 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:27:02.063 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:27:02.063 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:27:02.063 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:27:02.063 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:27:02.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:27:02.067 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:27:02.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:27:02.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:27:02.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:27:02.067 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:27:02.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:27:02.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:27:02.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:02.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:27:02.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:27:02.067 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:27:02.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:02.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:02.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:02.067 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:27:02.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:02.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:02.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:02.067 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:27:02.067 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:27:02.067 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:27:02.067 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:02.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:02.072 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:27:02.550 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:27:02.591 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:27:02.592 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:27:02.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:27:02.594 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:27:02.596 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:27:02.597 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:27:02.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:27:02.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:27:02.598 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:27:02.598 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:27:02.599 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:27:02.599 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:27:03.022 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:27:03.070 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:27:03.070 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:27:03.071 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:27:03.071 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:27:03.493 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:27:03.966 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:27:04.071 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:27:04.072 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:27:04.072 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:27:04.072 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:27:04.439 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:27:04.911 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:27:05.072 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:27:05.084 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:27:05.084 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:27:05.084 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:27:05.382 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:27:05.855 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:27:06.085 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:27:06.085 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:27:06.085 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:27:06.085 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:27:06.328 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:27:06.799 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:27:07.086 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:27:07.086 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:27:07.086 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:27:07.086 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:27:07.271 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:27:07.744 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:27:08.216 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:27:08.688 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:27:09.161 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:27:09.634 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:27:10.106 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:27:10.577 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:27:11.050 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:27:11.523 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:27:11.995 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:27:12.466 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:27:12.939 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:27:13.411 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:27:13.643 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:27:13.643 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:27:13.646 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:27:13.646 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:27:13.646 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:27:13.646 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:27:13.648 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:27:13.649 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:27:13.649 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:27:13.649 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:27:13.649 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:27:13.649 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:27:13.649 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:27:13.650 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2501 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:27:13.650 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2501 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:27:13.650 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2501 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:27:13.650 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2501 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:27:13.650 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2501 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:27:13.650 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2501 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:27:18.652 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:27:18.652 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:27:18.652 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:27:18.652 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:27:18.652 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:27:18.652 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:27:18.659 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:27:18.659 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:27:18.659 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:27:18.660 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:27:18.660 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:27:18.662 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:27:18.662 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:27:18.662 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:27:18.662 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:27:18.663 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:27:18.663 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:27:18.663 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:27:18.663 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:27:18.663 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:27:18.665 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:27:18.665 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:27:18.665 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:27:18.665 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:27:18.665 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:27:18.665 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:27:18.666 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:27:18.666 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:27:18.666 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:27:18.668 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:27:18.668 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:27:18.668 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:27:18.668 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:27:18.668 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:27:18.668 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:27:18.668 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:27:18.668 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:27:18.669 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:27:18.672 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:27:18.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:27:18.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:27:18.672 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:27:18.672 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:27:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:27:18.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:27:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:27:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:27:18.673 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:27:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:18.673 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:27:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:18.673 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:27:18.673 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:27:18.673 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:27:18.673 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:27:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:18.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:18.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:27:18.674 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:18.674 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:18.674 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:18.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:18.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:18.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:18.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:18.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:18.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:18.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:18.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:18.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:18.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:18.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:18.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:18.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:18.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:18.675 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:27:18.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:18.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:18.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:18.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:18.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:18.675 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:27:18.675 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:27:18.675 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:27:18.675 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:27:18.675 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:27:18.675 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:27:23.684 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:27:23.684 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:27:23.684 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:27:23.684 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:27:23.684 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:27:23.684 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:27:23.691 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:27:23.692 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:27:23.692 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:27:23.692 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:27:23.692 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:27:23.694 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:27:23.695 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:27:23.695 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:27:23.695 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:27:23.696 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:27:23.696 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:27:23.696 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:27:23.696 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:27:23.697 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:27:23.697 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:27:23.698 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:27:23.698 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:27:23.698 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:27:23.698 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:27:23.698 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:27:23.698 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:27:23.698 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:27:23.699 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:27:23.700 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:27:23.700 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:27:23.700 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:27:23.700 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:27:23.700 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:27:23.700 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:27:23.700 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:27:23.700 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:27:23.700 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:27:23.703 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:27:23.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:27:23.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:27:23.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:27:23.703 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:27:23.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:27:23.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:27:23.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:23.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:27:23.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:27:23.703 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:27:23.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:23.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:23.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:23.703 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:27:23.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:23.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:23.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:23.703 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:27:23.703 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:27:23.703 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:27:23.703 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:27:23.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:23.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:23.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:23.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:27:23.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:23.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:23.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:23.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:23.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:23.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:23.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:23.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:23.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:23.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:23.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:23.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:23.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:23.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:23.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:23.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:23.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:23.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:23.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:23.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:23.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:23.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:23.708 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:27:24.186 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:27:24.229 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:27:24.231 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:27:24.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:27:24.233 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:27:24.237 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:27:24.237 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:27:24.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:27:24.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:27:24.238 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:27:24.238 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:27:24.239 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:27:24.239 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:27:24.659 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:27:24.705 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:27:24.705 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:27:24.706 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:27:24.706 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:27:25.130 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:27:25.603 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:27:25.706 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:27:25.707 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:27:25.707 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:27:25.707 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:27:26.076 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:27:26.548 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:27:26.707 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:27:26.707 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:27:26.708 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:27:26.708 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:27:27.021 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:27:27.493 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:27:27.708 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:27:27.709 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:27:27.709 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:27:27.709 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:27:27.965 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:27:28.436 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:27:28.710 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:27:28.710 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:27:28.710 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:27:28.710 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:27:28.907 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:27:29.380 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:27:29.853 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:27:30.324 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:27:30.796 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:27:31.269 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:27:31.742 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:27:32.213 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:27:32.685 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:27:33.158 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:27:33.630 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:27:34.103 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:27:34.576 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:27:35.049 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:27:35.521 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:27:35.992 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:27:36.465 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:27:36.937 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:27:37.409 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:27:37.880 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:27:38.353 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:27:38.826 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:27:39.298 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:27:39.769 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:27:40.243 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:27:40.715 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:27:41.187 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:27:41.658 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:27:42.129 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:27:42.602 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 03:27:43.074 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 03:27:43.547 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 03:27:44.017 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 03:27:44.288 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:27:44.288 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:27:44.289 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:27:44.289 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:27:44.289 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:27:44.289 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:27:44.290 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:27:44.290 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:27:44.290 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:27:44.290 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:27:44.290 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:27:44.290 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:27:44.290 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:27:49.297 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:27:49.297 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:27:49.297 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:27:49.297 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:27:49.297 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:27:49.297 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:27:49.305 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:27:49.305 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:27:49.306 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:27:49.306 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:27:49.306 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:27:49.311 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:27:49.311 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:27:49.312 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:27:49.312 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:27:49.312 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:27:49.313 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:27:49.313 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:27:49.313 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:27:49.314 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:27:49.316 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:27:49.316 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:27:49.316 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:27:49.317 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:27:49.317 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:27:49.317 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:27:49.318 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:27:49.318 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:27:49.318 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:27:49.321 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:27:49.321 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:27:49.322 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:27:49.322 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:27:49.322 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:27:49.322 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:27:49.322 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:27:49.322 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:27:49.323 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:27:49.328 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:27:49.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:27:49.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:27:49.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:27:49.328 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:27:49.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:27:49.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:27:49.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:49.329 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:27:49.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:27:49.329 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:27:49.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:49.329 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:49.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:49.329 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:27:49.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:49.329 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:49.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:49.329 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:27:49.329 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:27:49.329 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:27:49.329 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:27:49.330 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:49.330 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:49.330 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:49.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:27:49.330 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:49.330 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:49.330 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:49.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:49.331 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:49.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:49.331 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:49.331 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:49.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:49.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:49.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:49.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:49.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:49.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:49.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:49.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:49.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:49.332 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:27:49.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:49.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:49.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:49.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:49.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:49.332 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:27:49.332 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:27:49.332 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:27:49.332 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:27:49.332 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:27:49.332 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:27:54.339 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:27:54.339 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:27:54.339 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:27:54.339 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:27:54.339 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:27:54.339 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:27:54.350 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:27:54.352 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:27:54.352 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:27:54.353 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:27:54.353 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:27:54.360 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:27:54.360 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:27:54.361 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:27:54.361 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:27:54.362 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:27:54.362 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:27:54.363 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:27:54.363 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:27:54.364 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:27:54.367 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:27:54.367 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:27:54.368 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:27:54.368 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:27:54.368 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:27:54.369 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:27:54.369 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:27:54.369 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:27:54.370 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:27:54.373 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:27:54.373 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:27:54.374 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:27:54.374 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:27:54.374 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:27:54.374 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:27:54.375 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:27:54.375 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:27:54.375 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:27:54.379 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:27:54.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:27:54.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:27:54.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:27:54.379 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:27:54.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:27:54.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:27:54.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:54.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:27:54.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:27:54.379 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:27:54.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:54.380 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:27:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:54.380 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:27:54.380 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:27:54.380 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:27:54.380 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:27:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:54.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:27:54.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:54.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:54.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:54.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:54.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:54.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:54.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:54.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:54.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:54.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:54.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:54.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:54.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:27:54.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:54.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:54.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:54.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:54.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:54.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:27:54.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:27:54.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:54.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:27:54.385 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:27:54.863 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:27:54.915 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:27:54.917 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:27:54.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:27:54.920 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:27:55.335 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:27:55.386 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:27:55.386 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:27:55.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:27:55.390 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:27:55.809 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:27:56.281 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:27:56.387 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:27:56.388 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:27:56.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:27:56.391 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:27:56.753 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:27:57.228 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:27:57.389 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:27:57.389 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:27:57.389 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:27:57.393 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:27:57.700 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:27:58.175 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:27:58.390 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:27:58.390 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:27:58.390 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:27:58.394 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:27:58.647 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:27:59.123 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:27:59.392 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:27:59.392 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:27:59.392 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:27:59.396 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:27:59.595 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:28:00.069 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:28:00.541 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:28:01.012 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:28:01.483 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:28:01.957 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:28:02.428 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:28:02.892 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:28:03.356 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:28:03.828 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:28:04.300 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:28:04.775 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:28:04.931 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:28:04.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:28:04.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:28:04.931 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:28:04.934 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:28:04.934 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:28:04.934 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:28:04.934 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:28:04.934 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:28:04.934 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:28:04.934 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:28:04.934 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2280 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:28:04.934 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2280 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:28:04.934 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2280 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:28:04.934 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2280 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:28:04.934 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2280 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:28:04.934 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2280 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:28:09.938 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:28:09.938 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:28:09.938 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:28:09.938 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:28:09.938 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:28:09.938 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:28:09.944 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:28:09.945 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:28:09.945 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:28:09.945 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:28:09.945 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:28:09.948 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:28:09.949 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:28:09.949 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:28:09.949 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:28:09.949 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:28:09.950 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:28:09.950 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:28:09.950 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:28:09.950 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:28:09.952 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:28:09.952 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:28:09.952 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:28:09.952 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:28:09.952 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:28:09.952 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:28:09.952 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:28:09.952 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:28:09.952 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:28:09.954 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:28:09.954 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:28:09.954 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:28:09.954 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:28:09.955 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:28:09.955 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:28:09.955 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:28:09.955 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:28:09.955 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:28:09.958 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:28:09.958 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:28:09.958 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:09.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:09.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:09.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:09.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:09.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:09.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:09.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:09.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:09.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:09.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:09.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:09.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:09.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:09.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:09.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:09.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:09.959 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:28:09.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:09.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:09.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:09.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:09.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:09.960 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:28:09.960 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:28:09.960 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:28:09.960 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:28:09.960 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:28:09.960 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:28:14.967 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:28:14.967 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:28:14.967 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:28:14.967 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:28:14.967 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:28:14.967 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:28:14.972 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:28:14.973 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:28:14.973 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:28:14.974 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:28:14.974 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:28:14.976 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:28:14.976 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:28:14.977 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:28:14.977 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:28:14.977 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:28:14.978 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:28:14.978 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:28:14.978 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:28:14.979 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:28:14.981 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:28:14.981 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:28:14.981 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:28:14.981 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:28:14.982 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:28:14.982 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:28:14.983 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:28:14.983 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:28:14.983 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:28:14.985 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:28:14.985 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:28:14.985 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:28:14.985 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:28:14.985 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:28:14.986 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:28:14.986 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:28:14.986 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:28:14.986 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:28:14.991 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:28:14.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:28:14.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:28:14.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:28:14.991 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:28:14.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:28:14.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:28:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:28:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:28:14.992 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:28:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:14.992 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:28:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:14.992 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:28:14.992 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:28:14.992 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:28:14.992 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:28:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:14.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:14.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:14.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:28:14.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:14.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:14.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:14.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:14.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:14.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:14.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:14.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:14.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:14.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:14.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:14.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:14.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:14.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:14.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:14.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:14.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:14.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:14.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:14.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:14.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:14.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:14.997 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:28:15.475 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:28:15.524 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:28:15.526 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:28:15.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:28:15.528 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:28:15.947 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:28:15.996 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:28:15.997 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:28:15.997 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:28:15.997 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:28:16.421 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:28:16.890 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:28:16.998 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:28:16.998 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:28:16.998 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:28:16.998 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:28:17.359 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:28:17.822 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:28:18.000 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:28:18.000 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:28:18.000 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:28:18.000 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:28:18.292 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:28:18.767 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:28:19.001 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:28:19.001 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:28:19.002 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:28:19.002 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:28:19.239 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:28:19.714 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:28:20.003 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:28:20.003 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:28:20.003 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:28:20.003 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:28:20.186 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:28:20.661 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:28:21.133 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:28:21.609 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:28:22.081 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:28:22.556 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:28:23.029 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:28:23.503 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:28:23.975 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:28:24.451 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:28:24.922 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:28:25.393 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:28:25.869 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:28:26.341 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:28:26.816 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:28:27.288 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:28:27.540 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:28:27.540 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:28:27.540 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:28:27.540 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:28:27.541 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:28:27.541 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:28:27.541 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:28:27.541 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:28:27.541 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:28:27.541 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:28:27.541 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:28:32.548 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:28:32.548 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:28:32.548 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:28:32.548 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:28:32.548 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:28:32.548 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:28:32.551 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:28:32.551 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:28:32.551 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:28:32.551 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:28:32.551 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:28:32.552 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:28:32.552 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:28:32.552 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:28:32.552 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:28:32.552 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:28:32.553 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:28:32.553 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:28:32.553 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:28:32.553 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:28:32.553 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:28:32.553 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:28:32.553 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:28:32.553 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:28:32.553 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:28:32.553 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:28:32.553 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:28:32.554 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:28:32.554 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:28:32.555 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:28:32.555 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:28:32.555 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:28:32.555 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:28:32.555 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:28:32.555 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:28:32.555 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:28:32.555 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:28:32.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:28:32.557 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:28:32.557 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:28:32.557 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:32.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:32.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:32.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:32.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:32.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:32.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:32.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:32.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:32.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:32.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:32.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:32.559 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:28:32.559 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:28:32.559 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:28:32.559 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:28:32.559 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:28:32.559 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:28:32.559 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:28:37.567 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:28:37.567 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:28:37.567 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:28:37.567 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:28:37.567 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:28:37.567 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:28:37.574 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:28:37.575 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:28:37.575 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:28:37.576 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:28:37.576 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:28:37.578 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:28:37.578 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:28:37.578 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:28:37.579 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:28:37.579 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:28:37.579 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:28:37.579 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:28:37.580 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:28:37.580 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:28:37.581 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:28:37.581 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:28:37.581 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:28:37.581 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:28:37.581 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:28:37.581 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:28:37.581 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:28:37.581 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:28:37.581 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:28:37.583 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:28:37.583 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:28:37.583 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:28:37.583 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:28:37.583 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:28:37.583 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:28:37.583 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:28:37.583 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:28:37.583 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:28:37.586 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:28:37.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:28:37.586 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:28:37.586 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:28:37.586 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:28:37.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:28:37.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:28:37.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:37.586 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:28:37.586 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:28:37.586 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:28:37.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:37.586 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:37.586 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:37.586 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:28:37.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:37.586 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:37.586 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:37.586 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:28:37.586 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:28:37.586 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:28:37.586 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:28:37.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:37.586 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:37.586 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:37.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:28:37.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:37.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:37.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:37.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:37.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:37.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:37.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:37.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:37.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:37.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:37.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:37.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:37.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:37.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:37.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:37.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:37.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:37.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:37.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:37.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:37.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:37.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:37.591 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:28:38.069 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:28:38.111 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:28:38.114 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:28:38.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:28:38.116 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:28:38.120 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:28:38.120 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:28:38.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:28:38.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:28:38.121 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:28:38.121 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:28:38.121 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:28:38.122 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:28:38.159 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:28:38.159 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-06 03:28:38.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:28:38.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:28:38.541 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:28:38.589 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:28:38.589 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:28:38.590 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:28:38.590 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:28:39.012 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:28:39.486 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:28:39.591 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:28:39.591 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:28:39.591 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:28:39.591 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:28:39.958 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:28:40.431 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:28:40.592 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:28:40.592 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:28:40.592 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:28:40.592 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:28:40.904 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:28:41.377 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:28:41.593 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:28:41.593 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:28:41.593 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:28:41.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:28:41.849 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:28:42.320 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:28:42.594 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:28:42.594 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:28:42.595 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:28:42.595 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:28:42.793 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:28:43.265 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:28:43.737 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:28:44.209 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:28:44.682 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:28:45.155 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:28:45.627 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:28:46.099 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:28:46.163 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:28:46.163 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:28:46.164 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:28:46.168 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:28:46.168 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:28:46.168 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:28:46.168 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:28:46.169 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:28:46.169 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:28:46.169 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:28:46.169 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:28:46.169 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:28:46.169 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:28:46.169 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:28:51.177 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:28:51.177 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:28:51.177 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:28:51.177 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:28:51.177 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:28:51.177 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:28:51.183 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:28:51.184 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:28:51.184 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:28:51.185 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:28:51.185 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:28:51.189 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:28:51.189 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:28:51.189 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:28:51.189 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:28:51.190 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:28:51.190 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:28:51.190 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:28:51.190 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:28:51.190 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:28:51.193 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:28:51.194 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:28:51.194 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:28:51.194 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:28:51.194 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:28:51.194 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:28:51.194 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:28:51.194 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:28:51.194 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:28:51.197 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:28:51.197 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:28:51.197 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:28:51.197 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:28:51.197 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:28:51.197 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:28:51.197 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:28:51.197 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:28:51.197 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:28:51.201 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:28:51.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:28:51.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:28:51.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:28:51.201 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:28:51.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:28:51.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:28:51.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:51.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:28:51.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:28:51.201 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:28:51.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:51.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:51.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:51.201 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:28:51.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:51.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:51.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:51.201 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:28:51.201 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:28:51.201 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:28:51.201 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:28:51.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:51.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:51.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:51.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:28:51.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:51.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:51.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:51.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:51.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:51.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:51.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:51.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:51.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:51.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:51.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:51.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:51.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:51.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:51.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:51.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:51.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:51.203 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:28:51.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:51.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:51.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:51.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:51.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:51.203 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:28:51.203 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:28:51.203 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:28:51.203 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:28:51.203 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:28:51.203 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:28:56.210 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:28:56.210 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:28:56.210 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:28:56.210 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:28:56.210 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:28:56.210 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:28:56.220 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:28:56.222 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:28:56.222 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:28:56.223 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:28:56.223 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:28:56.228 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:28:56.228 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:28:56.229 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:28:56.229 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:28:56.229 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:28:56.230 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:28:56.230 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:28:56.230 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:28:56.230 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:28:56.233 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:28:56.233 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:28:56.233 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:28:56.233 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:28:56.233 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:28:56.234 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:28:56.234 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:28:56.234 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:28:56.234 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:28:56.237 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:28:56.237 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:28:56.237 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:28:56.237 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:28:56.237 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:28:56.237 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:28:56.237 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:28:56.237 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:28:56.237 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:28:56.241 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:28:56.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:28:56.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:28:56.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:28:56.241 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:28:56.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:28:56.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:28:56.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:56.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:28:56.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:28:56.242 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:28:56.242 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:56.242 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:56.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:56.242 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:28:56.242 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:56.242 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:56.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:56.242 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:28:56.242 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:28:56.242 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:28:56.242 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:28:56.242 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:56.242 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:56.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:56.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:28:56.242 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:56.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:56.242 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:56.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:56.242 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:56.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:56.243 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:56.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:56.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:56.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:56.243 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:28:56.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:56.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:56.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:56.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:56.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:56.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:56.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:56.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:28:56.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:28:56.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:56.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:28:56.247 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:28:56.724 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:28:56.773 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:28:56.775 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:28:56.777 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:28:56.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:28:56.780 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:28:56.780 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:28:56.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:28:56.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:28:56.781 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:28:56.781 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:28:56.782 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:28:56.782 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:28:56.815 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:28:56.815 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-06 03:28:56.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:28:56.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:28:57.196 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:28:57.244 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:28:57.245 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:28:57.245 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:28:57.245 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:28:57.668 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:28:58.141 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:28:58.246 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:28:58.246 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:28:58.246 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:28:58.246 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:28:58.613 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:28:59.085 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:28:59.246 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:28:59.247 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:28:59.247 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:28:59.247 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:28:59.557 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:29:00.031 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:29:00.248 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:00.248 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:00.248 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:00.248 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:00.502 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:29:00.974 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:29:01.249 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:01.249 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:01.249 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:01.249 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:01.447 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:29:01.919 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:29:02.391 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:29:02.863 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:29:03.336 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:29:03.808 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:29:04.281 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:29:04.755 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:29:04.820 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:29:04.820 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:29:04.820 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:29:04.825 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:04.826 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:04.826 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:04.826 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:04.828 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:29:04.828 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:29:04.828 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:29:04.828 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:29:04.828 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:29:04.828 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:29:04.828 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:29:09.833 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:29:09.833 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:29:09.833 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:29:09.833 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:29:09.833 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:29:09.833 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:29:09.841 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:29:09.842 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:29:09.842 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:29:09.842 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:29:09.842 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:29:09.846 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:29:09.847 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:29:09.847 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:29:09.847 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:29:09.847 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:29:09.847 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:29:09.847 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:29:09.847 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:29:09.848 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:09.851 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:29:09.851 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:29:09.851 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:29:09.851 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:29:09.851 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:29:09.851 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:29:09.851 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:29:09.851 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:29:09.852 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:09.854 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:29:09.854 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:29:09.854 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:29:09.854 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:29:09.854 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:29:09.854 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:29:09.855 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:29:09.855 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:29:09.855 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:09.858 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:29:09.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:29:09.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:29:09.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:29:09.858 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:29:09.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:29:09.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:29:09.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:29:09.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:29:09.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:09.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:09.858 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:29:09.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:09.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:09.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:09.858 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:09.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:09.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:09.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:09.858 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:29:09.858 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:29:09.858 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:29:09.858 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:29:09.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:09.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:09.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:09.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:29:09.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:09.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:09.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:09.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:09.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:09.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:09.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:09.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:09.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:09.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:09.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:09.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:09.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:09.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:09.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:09.860 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:29:09.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:09.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:09.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:09.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:09.860 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:29:09.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:09.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:09.860 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:29:09.860 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:29:09.860 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:29:09.860 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:29:09.860 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:29:14.867 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:29:14.867 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:29:14.867 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:29:14.867 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:29:14.867 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:29:14.867 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:29:14.876 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:29:14.877 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:29:14.877 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:29:14.877 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:29:14.877 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:29:14.880 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:29:14.881 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:29:14.881 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:29:14.881 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:29:14.881 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:29:14.881 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:29:14.881 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:29:14.881 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:29:14.881 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:14.884 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:29:14.884 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:29:14.884 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:29:14.884 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:29:14.885 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:29:14.885 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:29:14.885 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:29:14.885 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:29:14.885 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:14.888 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:29:14.888 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:29:14.889 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:29:14.889 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:29:14.889 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:29:14.889 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:29:14.889 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:29:14.889 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:29:14.889 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:14.894 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:29:14.894 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:29:14.894 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:29:14.894 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:29:14.894 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:29:14.894 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:29:14.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:29:14.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:14.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:29:14.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:29:14.895 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:29:14.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:14.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:14.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:14.895 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:14.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:14.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:14.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:14.895 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:29:14.895 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:29:14.895 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:29:14.895 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:29:14.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:14.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:14.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:14.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:29:14.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:14.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:14.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:14.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:14.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:14.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:14.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:14.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:14.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:14.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:14.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:14.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:14.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:14.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:14.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:14.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:14.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:14.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:14.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:14.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:14.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:14.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:14.900 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:29:15.377 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:29:15.427 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:29:15.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:29:15.431 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:29:15.433 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:29:15.436 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:29:15.436 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:29:15.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:29:15.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:29:15.437 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:29:15.437 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:29:15.437 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:29:15.437 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:29:15.467 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:29:15.467 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-06 03:29:15.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:29:15.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:29:15.861 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:29:15.899 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:15.899 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:15.900 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:15.901 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:16.334 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:29:16.807 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:29:16.900 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:16.900 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:16.901 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:16.902 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:17.279 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:29:17.751 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:29:17.901 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:17.902 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:17.902 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:17.903 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:18.223 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:29:18.697 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:29:18.903 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:18.903 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:18.903 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:18.903 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:19.169 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:29:19.641 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:29:19.904 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:19.904 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:19.904 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:19.904 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:20.115 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:29:20.587 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:29:21.059 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:29:21.532 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:29:22.004 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:29:22.477 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:29:22.950 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:29:23.422 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:29:23.471 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:29:23.471 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:29:23.471 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:29:23.476 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:23.477 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:23.477 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:23.477 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:23.478 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:29:23.478 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:29:23.478 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:29:23.478 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:29:23.478 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:29:23.478 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:29:23.479 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:29:28.484 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:29:28.484 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:29:28.484 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:29:28.484 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:29:28.484 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:29:28.485 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:29:28.497 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:29:28.498 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:29:28.498 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:29:28.498 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:29:28.498 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:29:28.503 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:29:28.503 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:29:28.503 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:29:28.503 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:29:28.504 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:29:28.504 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:29:28.504 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:29:28.504 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:29:28.504 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:28.508 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:29:28.508 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:29:28.508 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:29:28.508 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:29:28.508 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:29:28.509 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:29:28.509 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:29:28.509 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:29:28.509 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:28.513 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:29:28.513 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:29:28.513 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:29:28.513 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:29:28.513 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:29:28.513 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:29:28.513 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:29:28.513 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:29:28.513 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:28.517 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:29:28.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:29:28.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:29:28.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:29:28.517 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:29:28.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:29:28.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:29:28.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:29:28.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:29:28.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:28.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:28.517 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:29:28.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:28.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:28.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:28.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:28.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:28.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:28.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:28.518 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:29:28.518 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:29:28.518 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:29:28.518 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:29:28.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:28.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:28.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:28.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:29:28.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:28.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:28.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:28.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:28.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:28.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:28.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:28.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:28.519 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:29:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:28.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:28.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:28.519 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:29:28.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:28.519 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:29:28.519 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:29:28.519 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:29:28.519 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:29:28.520 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:29:33.527 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:29:33.527 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:29:33.527 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:29:33.527 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:29:33.527 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:29:33.527 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:29:33.535 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:29:33.536 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:29:33.537 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:29:33.537 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:29:33.537 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:29:33.540 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:29:33.540 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:29:33.541 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:29:33.541 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:29:33.541 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:29:33.542 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:29:33.542 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:29:33.542 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:29:33.542 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:33.544 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:29:33.544 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:29:33.544 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:29:33.544 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:29:33.545 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:29:33.545 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:29:33.545 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:29:33.545 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:29:33.545 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:33.546 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:29:33.546 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:29:33.547 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:29:33.547 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:29:33.547 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:29:33.547 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:29:33.547 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:29:33.547 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:29:33.547 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:33.550 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:29:33.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:29:33.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:29:33.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:29:33.550 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:29:33.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:29:33.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:29:33.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:33.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:29:33.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:29:33.550 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:29:33.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:33.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:33.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:33.550 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:33.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:33.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:33.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:33.550 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:29:33.550 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:29:33.550 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:29:33.550 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:33.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:33.555 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:29:34.034 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:29:34.078 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:29:34.080 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:29:34.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:29:34.082 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:29:34.086 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:29:34.086 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:29:34.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:29:34.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:29:34.088 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:29:34.088 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:29:34.088 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:29:34.088 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:29:34.124 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:29:34.124 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-06 03:29:34.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:29:34.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:29:34.506 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:29:34.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:34.554 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:34.555 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:34.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:34.978 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:29:35.452 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:29:35.555 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:35.555 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:35.556 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:35.556 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:35.923 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:29:36.395 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:29:36.556 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:36.556 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:36.556 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:36.557 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:36.869 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:29:37.340 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:29:37.557 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:37.558 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:37.558 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:37.558 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:37.813 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:29:38.287 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:29:38.559 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:38.559 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:38.559 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:38.559 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:38.759 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:29:39.231 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:29:39.704 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:29:40.176 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:29:40.650 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:29:41.121 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:29:41.594 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:29:42.067 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:29:42.128 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:29:42.129 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:29:42.129 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:29:42.133 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:42.133 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:42.133 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:42.133 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:42.133 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:29:42.133 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:29:42.133 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:29:42.133 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:29:42.133 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:29:42.133 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:29:42.133 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:29:47.140 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:29:47.141 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:29:47.141 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:29:47.141 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:29:47.141 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:29:47.141 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:29:47.148 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:29:47.149 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:29:47.149 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:29:47.150 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:29:47.150 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:29:47.152 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:29:47.152 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:29:47.153 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:29:47.153 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:29:47.153 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:29:47.153 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:29:47.154 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:29:47.154 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:29:47.154 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:47.155 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:29:47.155 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:29:47.155 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:29:47.155 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:29:47.155 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:29:47.155 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:29:47.155 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:29:47.155 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:29:47.155 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:47.157 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:29:47.157 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:29:47.157 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:29:47.157 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:29:47.157 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:29:47.157 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:29:47.157 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:29:47.157 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:29:47.157 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:47.160 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:29:47.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:29:47.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:29:47.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:29:47.160 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:29:47.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:29:47.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:29:47.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:47.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:29:47.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:29:47.160 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:29:47.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:47.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:47.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:47.160 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:47.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:47.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:47.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:47.160 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:29:47.160 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:29:47.160 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:29:47.160 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:29:47.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:47.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:47.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:47.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:29:47.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:47.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:47.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:47.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:47.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:47.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:47.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:47.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:47.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:47.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:47.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:47.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:47.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:47.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:47.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:47.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:47.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:47.161 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:29:47.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:47.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:47.162 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:47.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:47.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:47.162 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:29:47.162 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:29:47.162 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:29:47.162 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:29:47.162 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:29:47.162 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:29:52.168 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:29:52.168 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:29:52.168 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:29:52.168 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:29:52.168 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:29:52.168 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:29:52.176 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:29:52.177 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:29:52.177 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:29:52.177 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:29:52.177 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:29:52.182 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:29:52.182 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:29:52.182 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:29:52.182 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:29:52.183 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:29:52.183 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:29:52.183 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:29:52.183 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:29:52.183 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:52.187 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:29:52.187 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:29:52.187 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:29:52.187 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:29:52.188 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:29:52.188 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:29:52.188 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:29:52.188 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:29:52.188 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:52.191 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:29:52.192 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:29:52.192 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:29:52.192 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:29:52.192 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:29:52.192 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:29:52.192 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:29:52.192 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:29:52.192 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:52.198 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:29:52.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:29:52.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:29:52.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:29:52.198 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:29:52.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:29:52.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:29:52.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:52.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:29:52.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:29:52.198 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:29:52.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:52.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:52.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:52.199 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:52.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:52.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:52.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:52.199 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:29:52.199 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:29:52.199 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:29:52.199 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:29:52.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:52.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:52.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:52.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:29:52.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:52.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:52.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:52.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:52.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:52.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:52.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:52.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:52.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:52.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:52.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:52.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:29:52.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:52.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:52.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:52.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:52.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:29:52.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:52.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:52.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:29:52.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:52.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:29:52.204 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:29:52.682 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:29:52.731 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:29:52.733 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:29:52.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:29:52.735 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:29:52.737 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:29:52.737 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:29:52.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:29:52.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:29:52.738 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:29:52.738 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:29:52.738 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:29:52.738 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:29:52.771 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:29:52.771 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-06 03:29:52.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:29:52.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:29:53.152 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:29:53.203 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:53.203 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:53.203 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:53.203 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:53.624 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:29:54.096 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:29:54.204 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:54.205 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:54.205 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:54.205 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:54.568 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:29:55.042 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:29:55.205 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:55.205 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:55.205 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:55.205 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:55.514 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:29:55.985 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:29:56.205 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:56.206 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:56.206 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:56.206 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:56.459 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:29:56.931 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:29:57.207 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:29:57.208 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:29:57.208 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:29:57.208 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:29:57.403 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:29:57.875 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:29:58.349 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:29:58.821 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:29:59.295 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:29:59.767 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:30:00.239 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:30:00.711 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:30:01.184 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:30:01.649 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:30:02.117 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:30:02.585 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:30:03.051 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:30:03.522 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:30:03.988 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:30:04.451 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:30:04.914 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:30:05.381 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:30:05.847 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:30:06.318 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:30:06.777 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:30:06.777 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:30:06.777 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:30:06.782 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:30:06.782 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:30:06.783 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:30:06.783 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:30:06.783 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:30:06.784 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:30:06.784 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:30:06.784 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:30:06.784 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:30:06.784 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:30:06.784 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:30:06.784 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3163 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:30:06.784 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3163 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:30:06.784 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3163 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:30:06.784 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3163 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:30:06.784 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3163 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:30:06.784 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3163 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:30:11.914 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:30:11.914 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:30:11.914 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:30:11.914 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:30:11.914 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:30:11.914 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:30:11.917 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:30:11.917 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:30:11.917 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:30:11.917 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:30:11.917 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:30:11.918 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:30:11.918 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:30:11.918 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:30:11.918 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:30:11.918 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:30:11.918 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:30:11.918 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:30:11.918 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:30:11.918 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:30:11.919 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:30:11.919 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:30:11.919 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:30:11.920 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:30:11.920 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:30:11.920 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:30:11.920 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:30:11.920 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:30:11.920 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:30:11.921 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:30:11.921 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:30:11.921 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:30:11.921 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:30:11.921 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:30:11.921 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:30:11.921 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:30:11.921 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:30:11.921 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:30:11.923 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:30:11.923 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:30:11.923 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:11.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:30:11.924 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:30:11.924 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:30:11.924 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:30:16.927 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:30:16.927 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:30:16.927 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:30:16.927 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:30:16.927 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:30:16.927 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:30:16.931 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:30:16.931 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:30:16.931 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:30:16.931 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:30:16.931 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:30:16.932 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:30:16.932 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:30:16.932 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:30:16.932 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:30:16.932 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:30:16.932 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:30:16.932 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:30:16.932 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:30:16.932 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:30:16.933 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:30:16.933 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:30:16.933 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:30:16.933 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:30:16.933 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:30:16.933 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:30:16.933 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:30:16.933 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:30:16.933 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:30:16.934 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:30:16.934 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:30:16.934 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:30:16.934 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:30:16.934 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:30:16.934 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:30:16.934 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:30:16.934 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:30:16.935 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:30:16.936 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:30:16.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:30:16.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:30:16.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:30:16.936 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:30:16.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:30:16.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:30:16.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:16.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:30:16.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:30:16.937 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:30:16.937 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:30:16.937 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:16.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:16.941 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:30:17.406 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:30:17.448 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:30:17.449 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:30:17.449 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:30:17.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:30:17.450 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:30:17.450 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:30:17.450 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:30:17.450 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:30:17.450 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:30:17.450 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:30:17.451 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:30:17.451 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:30:17.494 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:30:17.494 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-06 03:30:17.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:30:17.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:30:17.869 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:30:17.939 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:30:17.940 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:30:17.940 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:30:17.940 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:30:18.339 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:30:18.807 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:30:18.940 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:30:18.941 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:30:18.941 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:30:18.941 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:30:19.272 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:30:19.740 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:30:19.941 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:30:19.942 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:30:19.942 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:30:19.942 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:30:20.209 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:30:20.678 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:30:20.943 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:30:20.943 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:30:20.943 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:30:20.943 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:30:21.145 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:30:21.617 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:30:21.944 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:30:21.944 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:30:21.944 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:30:21.944 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:30:22.082 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:30:22.550 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:30:23.019 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:30:23.490 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:30:23.961 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:30:24.431 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:30:24.903 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:30:25.372 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:30:25.498 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:30:25.498 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:30:25.499 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:30:25.503 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:30:25.504 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:30:25.504 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:30:25.504 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:30:25.507 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:30:25.507 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:30:25.507 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:30:25.507 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:30:25.507 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:30:25.507 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:30:25.507 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:30:25.507 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1867 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:30:25.507 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1867 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:30:25.507 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1867 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:30:25.507 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1867 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:30:25.507 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1867 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:30:25.507 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1867 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:30:30.510 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:30:30.510 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:30:30.510 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:30:30.510 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:30:30.510 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:30:30.510 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:30:30.520 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:30:30.521 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:30:30.521 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:30:30.521 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:30:30.521 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:30:30.524 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:30:30.524 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:30:30.524 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:30:30.524 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:30:30.525 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:30:30.525 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:30:30.525 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:30:30.525 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:30:30.525 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:30:30.527 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:30:30.528 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:30:30.528 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:30:30.528 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:30:30.528 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:30:30.528 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:30:30.528 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:30:30.528 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:30:30.528 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:30:30.530 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:30:30.530 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:30:30.530 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:30:30.530 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:30:30.530 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:30:30.530 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:30:30.530 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:30:30.530 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:30:30.531 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:30:30.533 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:30:30.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:30:30.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:30:30.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:30:30.533 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:30:30.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:30:30.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:30:30.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:30:30.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:30.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:30:30.533 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:30:30.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:30.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:30.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:30.533 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:30:30.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:30.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:30.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:30.533 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:30:30.533 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:30:30.534 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:30:30.534 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:30:30.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:30.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:30.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:30.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:30:30.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:30.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:30.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:30.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:30.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:30.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:30.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:30.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:30.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:30.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:30.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:30.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:30.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:30.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:30.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:30.535 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:30:30.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:30.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:30.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:30.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:30.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:30.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:30.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:30.535 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:30:30.535 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:30:30.535 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:30:30.535 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:30:30.535 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:30:30.535 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:30:35.538 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:30:35.538 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:30:35.538 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:30:35.538 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:30:35.538 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:30:35.538 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:30:35.541 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:30:35.541 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:30:35.541 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:30:35.541 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:30:35.541 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:30:35.542 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:30:35.542 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:30:35.542 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:30:35.542 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:30:35.542 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:30:35.542 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:30:35.542 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:30:35.542 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:30:35.542 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:30:35.543 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:30:35.543 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:30:35.543 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:30:35.543 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:30:35.543 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:30:35.543 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:30:35.543 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:30:35.543 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:30:35.543 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:30:35.544 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:30:35.544 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:30:35.544 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:30:35.544 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:30:35.545 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:30:35.545 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:30:35.545 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:30:35.545 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:30:35.545 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:30:35.546 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:30:35.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:30:35.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:30:35.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:30:35.546 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:30:35.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:30:35.547 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:30:35.547 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:30:35.547 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:35.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:35.552 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:30:36.018 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:30:36.058 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:30:36.059 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:30:36.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:30:36.059 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:30:36.060 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:30:36.060 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:30:36.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:30:36.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:30:36.060 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:30:36.060 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:30:36.060 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:30:36.060 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:30:36.483 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:30:36.549 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:30:36.549 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:30:36.549 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:30:36.550 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:30:36.947 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:30:37.413 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:30:37.551 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:30:37.551 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:30:37.551 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:30:37.551 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:30:37.883 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:30:38.355 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:30:38.552 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:30:38.552 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:30:38.552 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:30:38.552 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:30:38.827 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:30:39.300 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:30:39.553 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:30:39.553 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:30:39.554 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:30:39.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:30:39.772 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:30:40.244 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:30:40.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:30:40.554 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:30:40.554 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:30:40.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:30:40.715 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:30:41.187 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:30:41.660 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:30:42.129 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:30:42.601 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:30:43.073 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:30:43.543 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:30:44.013 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:30:44.480 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:30:44.945 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:30:45.415 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:30:45.884 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:30:46.116 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:30:46.116 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:30:46.121 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:30:46.121 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:30:46.121 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:30:46.121 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:30:46.123 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:30:46.123 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:30:46.123 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:30:46.123 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:30:46.123 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:30:46.123 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:30:46.123 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:30:51.132 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:30:51.132 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:30:51.132 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:30:51.132 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:30:51.132 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:30:51.133 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:30:51.142 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:30:51.143 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:30:51.143 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:30:51.143 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:30:51.143 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:30:51.144 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:30:51.144 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:30:51.145 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:30:51.145 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:30:51.145 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:30:51.145 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:30:51.145 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:30:51.145 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:30:51.145 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:30:51.146 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:30:51.146 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:30:51.146 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:30:51.146 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:30:51.146 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:30:51.146 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:30:51.146 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:30:51.146 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:30:51.146 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:30:51.147 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:30:51.147 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:30:51.148 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:30:51.148 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:30:51.148 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:30:51.148 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:30:51.148 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:30:51.148 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:30:51.148 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:30:51.150 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:30:51.150 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:30:51.150 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:51.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:51.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:51.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:51.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:51.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:51.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:51.152 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:30:51.152 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:30:51.152 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:30:51.152 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:30:51.152 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:30:51.152 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:30:51.152 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:30:56.158 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:30:56.158 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:30:56.158 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:30:56.158 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:30:56.158 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:30:56.158 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:30:56.167 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:30:56.169 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:30:56.169 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:30:56.170 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:30:56.170 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:30:56.175 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:30:56.175 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:30:56.176 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:30:56.176 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:30:56.176 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:30:56.177 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:30:56.177 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:30:56.177 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:30:56.178 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:30:56.179 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:30:56.179 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:30:56.180 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:30:56.180 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:30:56.180 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:30:56.180 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:30:56.181 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:30:56.181 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:30:56.181 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:30:56.182 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:30:56.182 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:30:56.182 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:30:56.183 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:30:56.183 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:30:56.183 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:30:56.183 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:30:56.183 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:30:56.183 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:30:56.186 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:30:56.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:30:56.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:30:56.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:30:56.186 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:30:56.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:30:56.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:30:56.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:56.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:30:56.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:30:56.186 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:30:56.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:56.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:56.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:56.187 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:30:56.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:56.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:56.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:56.187 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:30:56.187 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:30:56.187 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:30:56.187 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:30:56.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:56.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:56.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:56.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:30:56.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:56.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:56.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:56.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:56.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:56.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:56.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:56.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:56.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:56.188 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:56.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:56.188 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:56.188 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:56.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:56.188 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:30:56.188 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:56.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:56.188 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:56.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:56.188 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:30:56.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:30:56.188 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:30:56.191 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:30:56.669 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:30:56.707 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:30:56.708 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:30:56.709 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:30:56.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:30:56.711 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:30:56.711 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:30:56.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:30:56.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:30:56.711 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:30:56.711 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:30:56.711 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:30:56.711 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:30:56.758 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:30:56.759 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-06 03:30:56.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:30:56.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:30:57.141 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:30:57.189 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:30:57.190 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:30:57.190 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:30:57.190 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:30:57.611 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:30:58.080 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:30:58.191 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:30:58.191 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:30:58.191 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:30:58.191 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:30:58.553 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:30:59.025 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:30:59.192 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:30:59.192 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:30:59.192 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:30:59.192 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:30:59.492 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:30:59.956 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:31:00.193 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:31:00.193 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:31:00.193 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:31:00.193 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:31:00.419 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:31:00.887 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:31:01.194 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:31:01.194 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:31:01.194 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:31:01.195 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:31:01.360 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:31:01.831 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:31:02.303 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:31:02.775 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:31:03.248 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:31:03.720 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:31:04.189 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:31:04.657 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:31:05.129 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:31:05.601 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:31:06.065 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:31:06.535 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:31:07.007 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:31:07.480 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:31:07.764 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:31:07.764 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:31:07.764 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:31:07.769 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:31:07.770 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:31:07.770 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:31:07.770 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:31:07.775 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:31:07.776 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:31:07.776 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:31:07.776 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:31:07.776 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:31:07.776 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:31:07.776 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:31:07.776 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2513 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:31:07.777 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2514 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:31:07.777 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2514 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:31:07.777 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2514 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:31:07.777 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2514 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:31:07.777 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2514 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:31:07.777 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2514 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:31:07.777 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2514 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:31:07.777 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2514 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:31:12.777 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:31:12.777 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:31:12.777 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:31:12.777 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:31:12.777 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:31:12.777 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:31:12.786 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:31:12.787 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:31:12.787 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:31:12.788 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:31:12.788 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:31:12.792 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:31:12.792 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:31:12.792 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:31:12.792 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:31:12.792 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:31:12.793 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:31:12.793 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:31:12.793 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:31:12.793 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:31:12.796 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:31:12.796 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:31:12.797 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:31:12.797 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:31:12.797 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:31:12.797 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:31:12.798 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:31:12.798 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:31:12.798 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:31:12.799 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:31:12.800 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:31:12.800 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:31:12.800 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:31:12.800 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:31:12.800 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:31:12.800 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:31:12.800 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:31:12.800 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:31:12.803 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:31:12.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:31:12.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:31:12.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:31:12.804 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:31:12.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:31:12.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:31:12.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:12.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:31:12.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:31:12.804 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:31:12.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:12.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:12.804 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:31:12.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:12.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:12.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:12.804 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:31:12.804 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:31:12.804 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:31:12.804 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:31:12.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:12.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:12.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:12.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:31:12.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:12.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:12.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:12.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:12.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:12.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:12.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:12.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:12.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:12.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:12.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:12.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:12.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:12.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:12.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:12.806 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:31:12.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:12.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:12.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:12.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:12.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:12.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:12.806 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:31:12.806 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:31:12.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:12.806 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:31:12.806 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:31:12.806 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:31:12.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:17.812 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:31:17.812 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:31:17.812 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:31:17.812 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:31:17.812 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:31:17.812 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:31:17.819 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:31:17.819 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:31:17.819 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:31:17.819 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:31:17.819 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:31:17.820 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:31:17.820 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:31:17.820 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:31:17.820 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:31:17.820 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:31:17.821 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:31:17.821 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:31:17.821 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:31:17.821 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:31:17.823 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:31:17.823 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:31:17.823 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:31:17.823 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:31:17.824 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:31:17.824 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:31:17.824 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:31:17.824 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:31:17.824 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:31:17.826 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:31:17.826 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:31:17.827 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:31:17.827 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:31:17.827 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:31:17.827 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:31:17.827 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:31:17.827 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:31:17.827 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:31:17.831 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:31:17.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:31:17.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:31:17.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:31:17.831 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:31:17.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:31:17.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:31:17.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:17.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:31:17.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:31:17.831 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:31:17.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:17.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:17.831 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:31:17.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:17.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:17.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:17.832 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:31:17.832 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:31:17.832 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:31:17.832 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:31:17.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:17.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:17.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:17.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:31:17.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:17.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:17.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:17.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:17.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:17.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:17.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:17.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:17.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:17.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:17.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:17.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:17.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:17.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:17.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:17.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:17.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:17.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:17.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:17.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:17.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:17.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:17.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:17.836 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:31:18.314 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:31:18.361 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:31:18.364 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:31:18.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:31:18.366 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:31:18.786 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:31:18.837 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:31:18.837 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:31:18.837 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:31:18.837 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:31:19.259 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:31:19.725 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:31:19.837 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:31:19.837 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:31:19.837 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:31:19.837 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:31:20.194 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:31:20.657 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:31:20.838 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:31:20.839 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:31:20.839 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:31:20.839 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:31:21.126 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:31:21.590 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:31:21.840 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:31:21.840 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:31:21.841 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:31:21.841 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:31:22.063 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:31:22.526 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:31:22.841 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:31:22.842 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:31:22.842 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:31:22.842 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:31:22.998 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:31:23.467 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:31:23.937 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:31:24.407 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:31:24.875 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:31:25.340 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:31:25.807 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:31:26.274 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:31:26.744 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:31:27.216 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:31:27.680 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:31:28.143 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:31:28.377 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:31:28.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:31:28.377 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:31:28.377 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:31:28.378 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:31:28.378 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:31:28.378 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:31:28.378 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:31:28.378 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:31:28.378 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:31:28.378 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:31:28.378 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2297 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:31:28.378 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2297 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:31:28.378 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2297 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:31:28.378 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2297 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:31:28.378 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2297 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:31:33.384 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:31:33.384 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:31:33.384 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:31:33.384 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:31:33.384 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:31:33.384 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:31:33.392 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:31:33.392 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:31:33.392 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:31:33.393 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:31:33.393 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:31:33.395 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:31:33.395 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:31:33.395 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:31:33.395 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:31:33.396 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:31:33.396 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:31:33.396 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:31:33.396 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:31:33.396 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:31:33.397 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:31:33.397 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:31:33.397 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:31:33.397 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:31:33.398 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:31:33.398 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:31:33.398 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:31:33.398 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:31:33.398 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:31:33.399 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:31:33.399 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:31:33.399 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:31:33.399 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:31:33.399 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:31:33.399 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:31:33.399 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:31:33.399 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:31:33.399 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:31:33.401 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:31:33.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:31:33.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:31:33.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:31:33.401 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:31:33.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:31:33.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:31:33.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:31:33.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:33.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:31:33.401 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:31:33.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:33.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:33.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:33.401 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:31:33.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:33.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:33.401 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:31:33.401 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:31:33.401 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:31:33.402 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:33.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:33.403 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:31:33.403 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:31:33.403 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:31:33.403 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:31:33.403 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:31:33.403 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:31:33.403 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:31:38.411 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:31:38.411 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:31:38.411 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:31:38.411 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:31:38.411 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:31:38.411 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:31:38.419 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:31:38.420 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:31:38.420 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:31:38.420 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:31:38.420 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:31:38.422 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:31:38.422 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:31:38.423 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:31:38.423 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:31:38.423 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:31:38.423 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:31:38.423 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:31:38.423 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:31:38.423 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:31:38.425 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:31:38.425 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:31:38.425 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:31:38.425 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:31:38.425 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:31:38.425 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:31:38.426 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:31:38.426 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:31:38.426 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:31:38.427 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:31:38.427 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:31:38.427 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:31:38.427 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:31:38.428 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:31:38.428 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:31:38.428 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:31:38.428 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:31:38.428 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:31:38.430 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:31:38.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:31:38.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:31:38.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:31:38.430 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:31:38.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:31:38.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:31:38.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:38.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:31:38.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:31:38.430 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:31:38.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:38.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:38.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:38.430 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:31:38.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:38.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:38.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:31:38.431 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:31:38.431 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:31:38.431 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:38.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:38.435 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:31:38.907 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:31:38.956 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:31:38.958 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:31:38.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:31:38.960 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:31:39.378 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:31:39.433 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:31:39.434 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:31:39.434 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:31:39.434 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:31:39.848 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:31:40.312 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:31:40.435 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:31:40.436 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:31:40.436 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:31:40.436 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:31:40.782 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:31:41.254 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:31:41.437 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:31:41.437 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:31:41.437 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:31:41.437 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:31:41.725 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:31:42.197 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:31:42.438 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:31:42.439 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:31:42.439 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:31:42.439 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:31:42.668 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:31:43.139 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:31:43.439 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:31:43.440 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:31:43.440 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:31:43.440 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:31:43.605 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:31:44.071 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:31:44.542 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:31:45.012 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:31:45.484 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:31:45.950 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:31:46.421 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:31:46.887 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:31:47.351 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:31:47.819 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:31:48.282 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:31:48.747 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:31:49.215 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:31:49.682 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:31:50.145 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:31:50.609 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:31:50.973 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:31:50.973 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:31:50.973 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:31:50.973 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:31:50.976 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:31:50.976 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:31:50.976 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:31:50.976 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:31:50.976 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:31:50.976 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:31:50.976 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:31:55.980 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:31:55.980 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:31:55.980 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:31:55.980 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:31:55.980 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:31:55.980 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:31:55.986 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:31:55.986 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:31:55.987 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:31:55.987 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:31:55.987 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:31:55.989 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:31:55.989 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:31:55.990 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:31:55.990 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:31:55.990 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:31:55.990 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:31:55.990 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:31:55.990 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:31:55.990 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:31:55.991 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:31:55.992 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:31:55.992 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:31:55.992 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:31:55.992 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:31:55.992 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:31:55.992 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:31:55.992 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:31:55.992 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:31:55.994 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:31:55.994 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:31:55.994 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:31:55.994 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:31:55.994 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:31:55.994 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:31:55.994 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:31:55.994 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:31:55.994 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:31:55.996 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:31:55.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:31:55.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:31:55.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:31:55.996 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:31:55.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:31:55.997 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:31:55.997 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:31:55.997 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:55.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:55.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:31:55.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:55.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:55.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:55.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:55.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:31:55.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:55.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:31:55.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:31:56.001 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:31:56.472 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:31:56.523 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:31:56.524 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:31:56.525 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:31:56.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:31:56.526 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:31:56.526 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:31:56.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:31:56.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:31:56.526 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:31:56.526 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:31:56.527 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:31:56.527 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:31:56.938 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:31:56.999 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:31:56.999 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:31:56.999 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:31:57.000 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:31:57.409 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:31:57.880 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:31:58.000 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:31:58.000 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:31:58.000 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:31:58.000 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:31:58.351 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:31:58.822 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:31:59.001 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:31:59.002 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:31:59.002 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:31:59.002 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:31:59.293 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:31:59.763 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:32:00.003 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:32:00.003 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:32:00.003 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:32:00.003 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:32:00.235 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:32:00.702 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:32:01.003 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:32:01.004 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:32:01.004 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:32:01.004 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:32:01.167 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:32:01.637 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:32:02.108 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:32:02.579 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:32:03.048 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:32:03.512 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:32:03.982 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:32:04.453 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:32:04.923 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:32:05.395 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:32:05.865 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:32:06.336 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:32:06.806 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:32:07.277 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:32:07.567 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:07.568 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:07.572 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:32:07.572 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:32:07.572 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:32:07.572 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:32:07.576 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:32:07.576 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:32:07.576 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:32:07.576 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:32:07.577 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:32:07.577 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:32:07.577 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:32:07.577 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2515 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:07.577 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2515 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:07.577 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2515 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:07.577 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2515 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:07.578 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2515 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:07.578 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2515 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:07.578 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2515 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:07.578 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2515 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:12.579 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:32:12.579 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:32:12.579 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:32:12.579 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:32:12.579 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:32:12.579 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:32:12.590 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:32:12.591 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:32:12.591 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:32:12.591 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:32:12.591 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:32:12.593 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:32:12.593 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:32:12.593 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:32:12.593 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:32:12.594 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:32:12.594 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:32:12.594 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:32:12.594 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:32:12.594 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:32:12.596 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:32:12.596 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:32:12.596 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:32:12.596 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:32:12.596 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:32:12.596 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:32:12.596 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:32:12.596 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:32:12.596 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:32:12.598 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:32:12.598 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:32:12.598 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:32:12.598 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:32:12.598 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:32:12.598 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:32:12.598 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:32:12.598 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:32:12.598 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:32:12.600 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:32:12.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:32:12.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:32:12.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:32:12.600 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:32:12.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:32:12.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:32:12.601 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:32:12.601 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:32:12.601 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:12.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:12.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:12.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:12.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:12.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:12.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:12.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:12.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:12.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:12.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:12.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:12.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:12.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:12.606 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:32:13.069 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:32:13.127 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:32:13.129 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:32:13.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:32:13.132 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:32:13.135 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:13.135 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:13.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:32:13.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:13.136 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:32:13.136 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:32:13.136 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:32:13.136 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:32:13.539 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:32:13.604 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:32:13.605 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:32:13.605 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:32:13.605 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:32:14.011 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:32:14.482 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:32:14.606 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:32:14.606 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:32:14.606 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:32:14.607 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:32:14.953 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:32:15.424 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:32:15.607 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:32:15.608 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:32:15.608 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:32:15.608 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:32:15.895 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:32:16.366 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:32:16.609 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:32:16.609 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:32:16.609 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:32:16.610 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:32:16.837 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:32:17.307 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:32:17.611 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:32:17.611 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:32:17.611 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:32:17.611 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:32:17.779 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:32:18.250 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:32:18.721 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:32:19.192 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:32:19.659 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:32:20.132 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:32:20.604 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:32:21.075 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:32:21.546 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:32:22.017 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:32:22.488 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:32:22.959 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:32:23.432 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:32:23.905 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:32:24.376 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:32:24.845 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:32:25.318 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:32:25.790 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:32:26.261 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:32:26.734 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:32:27.206 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:32:27.678 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:32:28.148 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:32:28.162 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:28.163 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:28.167 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:32:28.167 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:32:28.167 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:32:28.167 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:32:28.170 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:32:28.170 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:32:28.170 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:32:28.170 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:32:28.170 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:32:28.170 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:32:28.170 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:32:33.174 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:32:33.174 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:32:33.174 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:32:33.174 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:32:33.174 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:32:33.174 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:32:33.181 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:32:33.182 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:32:33.182 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:32:33.182 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:32:33.182 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:32:33.185 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:32:33.185 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:32:33.185 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:32:33.185 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:32:33.185 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:32:33.185 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:32:33.185 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:32:33.185 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:32:33.186 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:32:33.188 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:32:33.188 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:32:33.188 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:32:33.188 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:32:33.188 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:32:33.188 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:32:33.188 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:32:33.188 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:32:33.188 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:32:33.190 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:32:33.190 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:32:33.191 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:32:33.191 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:32:33.191 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:32:33.191 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:32:33.191 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:32:33.191 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:32:33.191 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:32:33.193 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:32:33.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:32:33.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:32:33.194 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:32:33.194 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:32:33.194 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:33.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:33.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:33.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:33.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:33.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:33.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:33.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:33.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:33.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:33.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:33.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:33.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:33.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:33.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:33.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:33.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:33.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:33.199 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:32:33.664 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:32:33.724 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:32:33.726 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:32:33.728 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:32:33.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:32:33.734 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:33.734 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:33.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:32:33.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:33.736 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:32:33.736 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:32:33.736 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:32:33.736 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:32:33.760 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:33.760 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:33.766 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:32:33.766 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:32:33.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:32:33.766 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:32:33.770 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:32:33.770 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:32:33.771 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:32:33.771 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:32:33.771 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:32:33.771 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:32:33.771 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:32:33.771 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:33.772 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:33.772 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:33.772 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:33.772 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=127 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:33.772 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=127 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:33.772 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=127 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:33.772 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=127 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:33.772 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=127 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:33.772 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=127 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:33.772 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=127 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:33.772 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=127 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:38.777 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:32:38.777 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:32:38.777 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:32:38.777 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:32:38.777 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:32:38.777 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:32:38.785 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:32:38.785 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:32:38.785 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:32:38.785 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:32:38.785 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:32:38.786 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:32:38.786 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:32:38.786 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:32:38.786 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:32:38.786 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:32:38.786 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:32:38.786 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:32:38.786 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:32:38.786 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:32:38.787 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:32:38.787 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:32:38.788 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:32:38.788 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:32:38.788 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:32:38.788 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:32:38.788 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:32:38.788 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:32:38.788 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:32:38.789 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:32:38.789 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:32:38.789 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:32:38.789 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:32:38.789 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:32:38.789 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:32:38.789 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:32:38.789 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:32:38.789 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:32:38.791 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:32:38.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:32:38.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:32:38.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:32:38.791 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:32:38.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:32:38.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:32:38.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:38.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:32:38.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:32:38.791 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:32:38.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:38.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:38.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:38.791 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:32:38.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:38.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:38.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:38.791 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:32:38.791 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:32:38.791 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:32:38.791 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:32:38.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:38.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:38.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:38.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:32:38.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:38.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:38.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:38.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:38.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:38.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:38.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:38.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:38.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:38.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:38.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:38.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:38.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:38.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:38.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:38.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:38.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:38.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:38.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:38.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:38.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:38.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:38.796 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:32:39.268 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:32:39.318 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:32:39.320 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:32:39.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:32:39.322 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:32:39.340 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:39.340 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:39.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:32:39.356 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:39.356 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:39.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:32:39.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:32:39.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:39.361 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:32:39.361 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:32:39.362 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:32:39.362 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:32:39.405 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:32:39.406 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:32:39.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:39.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:39.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:39.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:32:39.530 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:39.531 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:39.547 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:39.548 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:39.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:32:39.554 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:39.554 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:39.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:32:39.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:32:39.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:39.556 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:32:39.556 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:32:39.556 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:32:39.556 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:32:39.596 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:32:39.596 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:32:39.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:39.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:39.738 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:32:39.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:39.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:32:39.783 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:39.783 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:39.783 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:32:39.793 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:32:39.794 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:32:39.794 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:32:39.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:32:39.800 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:39.800 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:39.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:32:39.805 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:39.805 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:39.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:32:39.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:32:39.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:39.807 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:32:39.807 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:32:39.807 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:32:39.807 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:32:39.824 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:32:39.824 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:32:39.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:39.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:40.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:40.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:32:40.130 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:40.130 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:40.145 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:40.146 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:40.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:32:40.151 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:40.151 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:40.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:32:40.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:32:40.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:40.153 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:32:40.153 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:32:40.154 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:32:40.154 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:32:40.204 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:32:40.205 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:32:40.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:40.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:40.205 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:32:40.672 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:32:40.794 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:32:40.794 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:32:40.794 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:32:40.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:32:40.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:40.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:32:40.991 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:40.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:40.991 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:32:41.001 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:32:41.002 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:32:41.002 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:32:41.002 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:32:41.004 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:32:41.004 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:32:41.004 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:32:41.004 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:32:41.004 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:32:41.004 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:32:41.004 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:32:41.004 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=482 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:41.005 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=482 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:41.005 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=482 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:41.005 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=482 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:41.005 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=482 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:41.005 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=482 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:32:46.007 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:32:46.007 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:32:46.007 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:32:46.007 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:32:46.007 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:32:46.007 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:32:46.019 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:32:46.020 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:32:46.020 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:32:46.020 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:32:46.020 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:32:46.023 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:32:46.023 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:32:46.023 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:32:46.023 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:32:46.023 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:32:46.023 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:32:46.024 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:32:46.024 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:32:46.024 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:32:46.026 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:32:46.026 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:32:46.026 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:32:46.026 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:32:46.026 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:32:46.026 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:32:46.026 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:32:46.026 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:32:46.027 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:32:46.029 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:32:46.029 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:32:46.029 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:32:46.029 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:32:46.029 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:32:46.029 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:32:46.029 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:32:46.029 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:32:46.029 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:32:46.032 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:32:46.032 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:32:46.032 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:32:46.032 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:32:46.032 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:32:46.032 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:32:46.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:32:46.032 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:46.032 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:32:46.032 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:32:46.032 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:32:46.032 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:46.032 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:46.032 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:46.032 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:32:46.032 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:46.032 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:46.032 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:46.032 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:32:46.032 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:32:46.032 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:32:46.032 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:32:46.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:32:46.037 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:32:46.503 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:32:46.556 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:32:46.557 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:32:46.558 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:32:46.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:32:46.577 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:46.577 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:46.577 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:32:46.593 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:46.593 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:46.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:32:46.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:32:46.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:46.597 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:32:46.597 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:32:46.597 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:32:46.597 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:32:46.641 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:32:46.641 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:32:46.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:46.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:46.970 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:32:47.035 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:32:47.035 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:32:47.036 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:32:47.036 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:32:47.437 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:32:47.903 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:32:48.036 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:32:48.037 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:32:48.037 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:32:48.037 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:32:48.374 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:32:48.845 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:32:49.038 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:32:49.038 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:32:49.038 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:32:49.039 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:32:49.318 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:32:49.791 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:32:50.039 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:32:50.039 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:32:50.039 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:32:50.039 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:32:50.262 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:32:50.734 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:32:51.040 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:32:51.040 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:32:51.040 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:32:51.040 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:32:51.204 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:32:51.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:51.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:32:51.651 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:51.651 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:51.668 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:51.668 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:51.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:32:51.674 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:51.674 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:51.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:32:51.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:32:51.675 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:32:51.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:51.676 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:32:51.676 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:32:51.676 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:32:51.676 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:32:51.717 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:32:51.717 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:32:51.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:51.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:52.145 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:32:52.617 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:32:53.089 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:32:53.562 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:32:54.035 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:32:54.508 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:32:54.980 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:32:55.447 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:32:55.912 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:32:56.381 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:32:56.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:56.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:32:56.726 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:56.726 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:56.726 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:32:56.741 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:56.741 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:56.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:32:56.747 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:32:56.747 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:32:56.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:32:56.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:32:56.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:56.749 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:32:56.749 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:32:56.749 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:32:56.749 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:32:56.801 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:32:56.802 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:32:56.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:56.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:32:56.851 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:32:57.323 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:32:57.794 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:32:58.264 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:32:58.738 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:32:59.210 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:32:59.682 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:33:00.153 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:33:00.626 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:33:01.099 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:33:01.571 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:33:01.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:01.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:33:01.807 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:01.807 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:01.816 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:01.816 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:01.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:33:01.822 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:01.822 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:01.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:33:01.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:33:01.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:01.824 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:33:01.824 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:33:01.824 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:33:01.824 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:33:01.850 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:33:01.850 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:33:01.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:01.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:02.042 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:33:02.512 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:33:02.982 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:33:03.452 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:33:03.920 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:33:04.386 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:33:04.852 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 03:33:05.323 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 03:33:05.788 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 03:33:06.255 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 03:33:06.726 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 03:33:06.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:06.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:33:06.860 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:06.860 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:06.861 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:33:06.875 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:33:06.875 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:33:06.875 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:33:06.875 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:33:06.879 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:33:06.879 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:33:06.879 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:33:06.879 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:33:06.880 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:33:06.880 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:33:06.880 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:33:06.880 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4523 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:33:06.880 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4523 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:33:06.880 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4523 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:33:06.880 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4523 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:33:06.881 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4523 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:33:06.881 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4523 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:33:06.881 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4523 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:33:11.882 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:33:11.882 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:33:11.882 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:33:11.882 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:33:11.882 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:33:11.882 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:33:11.891 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:33:11.893 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:33:11.893 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:33:11.894 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:33:11.894 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:33:11.899 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:33:11.900 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:33:11.900 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:33:11.900 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:33:11.901 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:33:11.901 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:33:11.901 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:33:11.901 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:33:11.902 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:33:11.904 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:33:11.905 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:33:11.905 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:33:11.905 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:33:11.905 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:33:11.906 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:33:11.906 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:33:11.906 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:33:11.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:33:11.908 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:33:11.908 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:33:11.908 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:33:11.908 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:33:11.909 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:33:11.909 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:33:11.909 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:33:11.909 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:33:11.909 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:33:11.913 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:33:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:33:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:33:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:33:11.913 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:33:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:33:11.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:33:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:33:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:33:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:33:11.913 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:33:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:33:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:33:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:33:11.913 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:33:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:33:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:33:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:33:11.913 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:33:11.913 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:33:11.913 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:33:11.914 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:33:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:33:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:33:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:33:11.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:33:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:33:11.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:33:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:33:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:33:11.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:33:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:33:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:33:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:33:11.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:33:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:33:11.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:33:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:33:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:33:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:33:11.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:33:11.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:33:11.915 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:33:11.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:33:11.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:33:11.915 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:33:11.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:33:11.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:33:11.918 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:33:12.396 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:33:12.444 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:33:12.446 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:33:12.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:33:12.449 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:33:12.472 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:12.472 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:12.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:33:12.498 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:12.498 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:12.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:33:12.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:33:12.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:12.508 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:33:12.508 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:33:12.509 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:33:12.509 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:33:12.535 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:33:12.535 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:33:12.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:12.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:12.869 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:33:12.916 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:33:12.917 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:33:12.917 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:33:12.917 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:33:13.340 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:33:13.813 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:33:13.918 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:33:13.918 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:33:13.918 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:33:13.919 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:33:14.286 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:33:14.758 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:33:14.919 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:33:14.919 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:33:14.920 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:33:14.920 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:33:15.229 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:33:15.700 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:33:15.921 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:33:15.921 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:33:15.921 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:33:15.921 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:33:16.171 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:33:16.644 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:33:16.922 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:33:16.922 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:33:16.922 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:33:16.923 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:33:17.114 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:33:17.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:17.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:33:17.543 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:17.543 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:17.560 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:17.560 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:17.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:33:17.566 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:17.566 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:17.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:33:17.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:33:17.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:17.568 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:33:17.568 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:33:17.568 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:33:17.568 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:33:17.578 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:33:17.578 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:33:17.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:17.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:17.584 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:33:18.056 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:33:18.527 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:33:18.998 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:33:19.465 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:33:19.935 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:33:20.405 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:33:20.877 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:33:21.347 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:33:21.819 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:33:22.289 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:33:22.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:22.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:33:22.586 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:22.586 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:22.587 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:33:22.600 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:22.600 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:22.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:33:22.606 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:22.606 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:22.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:33:22.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:33:22.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:22.607 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:33:22.607 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:33:22.607 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:33:22.607 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:33:22.609 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:33:22.609 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:33:22.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:22.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:22.757 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:33:23.227 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:33:23.698 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:33:24.167 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:33:24.633 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:33:25.105 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:33:25.575 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:33:26.043 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:33:26.513 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:33:26.984 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:33:27.455 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:33:27.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:27.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:33:27.614 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:27.614 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:27.625 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:27.626 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:27.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:33:27.631 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:27.631 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:27.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:33:27.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:33:27.633 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:27.633 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:33:27.633 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:33:27.633 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:33:27.633 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:33:27.635 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:33:27.635 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:33:27.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:27.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:27.921 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:33:28.385 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:33:28.850 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:33:29.323 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:33:29.791 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:33:30.261 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:33:30.732 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 03:33:31.203 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 03:33:31.674 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 03:33:32.144 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 03:33:32.614 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 03:33:32.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:32.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:33:32.642 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:32.642 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:32.642 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:33:32.654 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:33:32.654 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:33:32.654 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:33:32.654 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:33:32.658 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:33:32.658 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:33:32.658 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:33:32.658 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:33:32.659 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:33:32.659 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:33:32.659 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:33:32.659 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4500 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:33:32.659 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4500 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:33:32.659 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4500 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:33:32.660 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4500 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:33:32.660 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4500 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:33:32.660 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=4500 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:33:37.660 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:33:37.660 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:33:37.660 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:33:37.660 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:33:37.660 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:33:37.660 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:33:37.672 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:33:37.673 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:33:37.673 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:33:37.673 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:33:37.673 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:33:37.676 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:33:37.676 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:33:37.676 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:33:37.676 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:33:37.676 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:33:37.677 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:33:37.677 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:33:37.677 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:33:37.677 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:33:37.679 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:33:37.679 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:33:37.679 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:33:37.679 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:33:37.679 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:33:37.679 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:33:37.680 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:33:37.680 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:33:37.680 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:33:37.682 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:33:37.682 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:33:37.682 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:33:37.682 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:33:37.683 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:33:37.683 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:33:37.683 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:33:37.683 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:33:37.683 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:33:37.686 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:33:37.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:33:37.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:33:37.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:33:37.686 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:33:37.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:33:37.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:33:37.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:33:37.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:33:37.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:33:37.687 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:33:37.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:33:37.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:33:37.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:33:37.687 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:33:37.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:33:37.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:33:37.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:33:37.687 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:33:37.687 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:33:37.687 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:33:37.687 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:33:37.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:33:37.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:33:37.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:33:37.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:33:37.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:33:37.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:33:37.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:33:37.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:33:37.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:33:37.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:33:37.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:33:37.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:33:37.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:33:37.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:33:37.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:33:37.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:33:37.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:33:37.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:33:37.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:33:37.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:33:37.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:33:37.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:33:37.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:33:37.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:33:37.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:33:37.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:33:37.692 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:33:38.162 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:33:38.215 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:33:38.217 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:33:38.218 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:33:38.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:33:38.239 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:38.239 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:38.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:33:38.260 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:38.260 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:38.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:33:38.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:33:38.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:38.268 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:33:38.268 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:33:38.268 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:33:38.268 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:33:38.300 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:33:38.300 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:33:38.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:38.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:38.631 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:33:38.690 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:33:38.690 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:33:38.690 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:33:38.691 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:33:39.105 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:33:39.576 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:33:39.691 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:33:39.691 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:33:39.691 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:33:39.692 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:33:40.047 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:33:40.516 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:33:40.692 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:33:40.692 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:33:40.692 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:33:40.692 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:33:40.985 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:33:41.455 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:33:41.693 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:33:41.694 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:33:41.694 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:33:41.694 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:33:41.926 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:33:42.397 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:33:42.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:33:42.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:33:42.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:33:42.695 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:33:42.868 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:33:43.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:43.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:33:43.308 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:43.308 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:43.324 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:43.324 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:43.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:33:43.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:33:43.331 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:43.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:43.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:33:43.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:43.332 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:33:43.332 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:33:43.332 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:33:43.332 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:33:43.340 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:33:43.383 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:33:43.383 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:33:43.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:43.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:43.806 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:33:44.275 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:33:44.745 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:33:45.213 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:33:45.685 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:33:46.158 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:33:46.629 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:33:47.100 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:33:47.574 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:33:48.047 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:33:48.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:48.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:33:48.393 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:48.393 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:48.393 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:33:48.412 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:48.412 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:48.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:33:48.418 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:48.418 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:48.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:33:48.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:33:48.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:48.421 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:33:48.421 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:33:48.421 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:33:48.421 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:33:48.466 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:33:48.467 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:33:48.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:48.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:48.519 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:33:48.990 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:33:49.463 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:33:49.934 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:33:50.402 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:33:50.873 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:33:51.346 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:33:51.817 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:33:52.289 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:33:52.761 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:33:53.231 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:33:53.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:53.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:33:53.474 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:53.474 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:53.490 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:53.490 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:53.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:33:53.495 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:53.495 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:53.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:33:53.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:33:53.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:53.497 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:33:53.497 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:33:53.497 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:33:53.497 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:33:53.509 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:33:53.509 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:33:53.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:53.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:53.702 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:33:54.172 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:33:54.643 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:33:55.114 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:33:55.584 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:33:56.055 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:33:56.525 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 03:33:56.993 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 03:33:57.466 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 03:33:57.938 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 03:33:58.410 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 03:33:58.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:33:58.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:33:58.515 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:33:58.515 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:33:58.515 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:33:58.522 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:33:58.522 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:33:58.522 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:33:58.522 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:33:58.523 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:33:58.523 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:33:58.523 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:33:58.523 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:33:58.523 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:33:58.523 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:33:58.523 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:34:03.530 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:34:03.530 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:34:03.530 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:34:03.530 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:34:03.530 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:34:03.530 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:34:03.538 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:34:03.539 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:34:03.539 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:34:03.539 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:34:03.539 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:34:03.542 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:34:03.542 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:34:03.542 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:34:03.542 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:34:03.543 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:34:03.543 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:34:03.543 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:34:03.543 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:34:03.543 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:34:03.545 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:34:03.545 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:34:03.546 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:34:03.546 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:34:03.546 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:34:03.546 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:34:03.546 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:34:03.546 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:34:03.546 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:34:03.550 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:34:03.550 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:34:03.550 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:34:03.550 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:34:03.550 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:34:03.551 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:34:03.551 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:34:03.551 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:34:03.551 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:34:03.555 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:34:03.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:34:03.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:34:03.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:34:03.555 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:34:03.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:34:03.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:34:03.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:34:03.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:34:03.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:34:03.555 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:34:03.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:34:03.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:34:03.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:34:03.555 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:34:03.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:34:03.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:34:03.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:34:03.555 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:34:03.556 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:34:03.556 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:34:03.556 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:34:03.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:34:03.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:34:03.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:34:03.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:34:03.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:34:03.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:34:03.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:34:03.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:34:03.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:34:03.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:34:03.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:34:03.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:34:03.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:34:03.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:34:03.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:34:03.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:34:03.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:34:03.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:34:03.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:34:03.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:34:03.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:34:03.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:34:03.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:34:03.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:34:03.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:34:03.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:34:03.560 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:34:04.033 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:34:04.083 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:34:04.084 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:34:04.084 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:34:04.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:34:04.104 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:04.104 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:04.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:34:04.127 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:04.127 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:04.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:34:04.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:34:04.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:04.137 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:34:04.137 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:34:04.137 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:34:04.137 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:34:04.170 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:34:04.170 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:34:04.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:04.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:04.501 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:34:04.559 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:34:04.560 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:34:04.560 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:34:04.560 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:34:04.971 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:34:05.442 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:34:05.560 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:34:05.561 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:34:05.561 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:34:05.561 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:34:05.912 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:34:06.384 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:34:06.562 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:34:06.562 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:34:06.562 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:34:06.562 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:34:06.855 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:34:07.325 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:34:07.563 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:34:07.564 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:34:07.564 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:34:07.564 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:34:07.796 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:34:08.267 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:34:08.565 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:34:08.565 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:34:08.565 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:34:08.565 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:34:08.739 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:34:09.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:09.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:34:09.179 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:09.179 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:09.198 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:09.198 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:09.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:34:09.204 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:09.204 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:09.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:34:09.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:34:09.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:09.206 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:34:09.206 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:34:09.206 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:34:09.206 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:34:09.211 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:34:09.253 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:34:09.253 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:34:09.253 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:09.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:09.677 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:34:10.149 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:34:10.619 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:34:11.090 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:34:11.562 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:34:12.034 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:34:12.506 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:34:12.976 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:34:13.448 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:34:13.920 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:34:14.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:14.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:34:14.262 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:14.262 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:14.263 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:34:14.278 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:14.278 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:14.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:34:14.283 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:14.283 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:14.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:34:14.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:34:14.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:14.285 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:34:14.285 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:34:14.285 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:34:14.285 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:34:14.286 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:34:14.286 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:34:14.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:14.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:14.392 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:34:14.863 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:34:15.334 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:34:15.805 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:34:16.271 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:34:16.742 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:34:17.213 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:34:17.683 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:34:18.154 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:34:18.623 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:34:19.095 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:34:19.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:19.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:34:19.292 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:19.292 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:19.310 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:19.310 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:19.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:34:19.316 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:19.316 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:19.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:34:19.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:34:19.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:19.317 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:34:19.317 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:34:19.317 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:34:19.317 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:34:19.328 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:34:19.328 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:34:19.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:19.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:19.564 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:34:20.036 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:34:20.503 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:34:20.969 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:34:21.439 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:34:21.912 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:34:22.383 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 03:34:22.854 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 03:34:23.324 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 03:34:23.794 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 03:34:24.259 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 03:34:24.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:24.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:34:24.333 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:24.333 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:24.334 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:34:24.344 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:34:24.345 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:34:24.345 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:34:24.345 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:34:24.347 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:34:24.347 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:34:24.347 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:34:24.347 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:34:24.347 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:34:24.347 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:34:24.347 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:34:29.350 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:34:29.350 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:34:29.350 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:34:29.350 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:34:29.350 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:34:29.350 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:34:29.359 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:34:29.359 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:34:29.359 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:34:29.360 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:34:29.360 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:34:29.362 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:34:29.362 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:34:29.363 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:34:29.363 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:34:29.363 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:34:29.363 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:34:29.364 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:34:29.364 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:34:29.364 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:34:29.365 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:34:29.365 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:34:29.365 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:34:29.365 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:34:29.365 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:34:29.365 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:34:29.366 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:34:29.366 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:34:29.366 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:34:29.367 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:34:29.367 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:34:29.368 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:34:29.368 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:34:29.368 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:34:29.368 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:34:29.368 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:34:29.368 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:34:29.368 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:34:29.370 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:34:29.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:34:29.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:34:29.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:34:29.370 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:34:29.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:34:29.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:34:29.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:34:29.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:34:29.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:34:29.370 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:34:29.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:34:29.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:34:29.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:34:29.370 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:34:29.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:34:29.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:34:29.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:34:29.371 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:34:29.371 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:34:29.371 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:34:29.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:34:29.375 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:34:29.842 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:34:29.898 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:34:29.899 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:34:29.900 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:34:29.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:34:29.913 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:29.913 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:29.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:34:29.928 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:29.928 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:29.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:34:29.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:34:29.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:29.935 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:34:29.935 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:34:29.935 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:34:29.935 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:34:29.979 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:34:29.980 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:34:29.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:29.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:30.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:30.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:34:30.222 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:30.222 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:30.239 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:30.239 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:30.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:34:30.245 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:30.245 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:30.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:34:30.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:34:30.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:30.247 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:34:30.247 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:34:30.247 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:34:30.247 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:34:30.259 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:34:30.259 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:34:30.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:30.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:30.309 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:34:30.373 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:34:30.373 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:34:30.373 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:34:30.374 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:34:30.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:30.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:34:30.637 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:30.637 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:30.637 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:34:30.655 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:30.655 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:30.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:34:30.661 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:30.661 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:30.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:34:30.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:34:30.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:30.663 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:34:30.663 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:34:30.663 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:34:30.663 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:34:30.680 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:34:30.680 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:34:30.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:30.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:30.777 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:34:31.250 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:34:31.374 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:34:31.374 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:34:31.374 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:34:31.374 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:34:31.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:31.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:34:31.410 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:31.411 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:31.428 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:31.428 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:31.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:34:31.434 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:31.434 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:31.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:34:31.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:34:31.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:31.436 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:34:31.436 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:34:31.436 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:34:31.436 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:34:31.485 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:34:31.485 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:34:31.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:31.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:31.721 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:34:32.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:32.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:34:32.041 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:32.041 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:32.041 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:34:32.052 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:34:32.052 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:34:32.053 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:34:32.053 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:34:32.054 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:34:32.054 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:34:32.054 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:34:32.054 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:34:32.054 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:34:32.054 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:34:32.054 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:34:32.054 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=584 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:34:32.054 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=584 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:34:32.054 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=584 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:34:32.054 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=584 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:34:32.054 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=584 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:34:32.054 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=584 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:34:32.054 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=584 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:34:37.058 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:34:37.058 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:34:37.058 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:34:37.058 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:34:37.058 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:34:37.058 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:34:37.064 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:34:37.064 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:34:37.065 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:34:37.065 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:34:37.065 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:34:37.066 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:34:37.066 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:34:37.066 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:34:37.067 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:34:37.067 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:34:37.067 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:34:37.067 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:34:37.067 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:34:37.067 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:34:37.068 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:34:37.068 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:34:37.068 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:34:37.068 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:34:37.068 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:34:37.068 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:34:37.068 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:34:37.069 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:34:37.069 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:34:37.070 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:34:37.070 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:34:37.070 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:34:37.070 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:34:37.070 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:34:37.070 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:34:37.070 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:34:37.070 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:34:37.071 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:34:37.074 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:34:37.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:34:37.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:34:37.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:34:37.074 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:34:37.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:34:37.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:34:37.075 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:34:37.075 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:34:37.075 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:34:37.075 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:34:37.075 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:34:37.075 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:34:37.075 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:34:37.075 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:34:37.075 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:34:37.075 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:34:37.075 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:34:37.075 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:34:37.075 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:34:37.075 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:34:37.075 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:34:37.075 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:34:37.075 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:34:37.075 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:34:37.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:34:37.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:34:37.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:34:37.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:34:37.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:34:37.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:34:37.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:34:37.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:34:37.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:34:37.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:34:37.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:34:37.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:34:37.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:34:37.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:34:37.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:34:37.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:34:37.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:34:37.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:34:37.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:34:37.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:34:37.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:34:37.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:34:37.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:34:37.080 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:34:37.545 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:34:37.612 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:34:37.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:34:37.616 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:34:37.617 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:34:37.637 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:37.637 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:37.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:34:37.658 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:37.658 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:37.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:34:37.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:34:37.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:37.666 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:34:37.666 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:34:37.666 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:34:37.666 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:34:37.683 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:34:37.683 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:34:37.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:37.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:38.010 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:34:38.079 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:34:38.079 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:34:38.079 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:34:38.080 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:34:38.479 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:34:38.950 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:34:39.079 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:34:39.080 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:34:39.080 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:34:39.081 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:34:39.421 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:34:39.891 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:34:40.080 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:34:40.080 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:34:40.080 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:34:40.082 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:34:40.356 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:34:40.827 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:34:41.081 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:34:41.081 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:34:41.081 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:34:41.083 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:34:41.299 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:34:41.770 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:34:42.082 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:34:42.082 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:34:42.082 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:34:42.083 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:34:42.241 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:34:42.711 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:34:43.183 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:34:43.653 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:34:44.124 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:34:44.595 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:34:45.066 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:34:45.536 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:34:46.008 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:34:46.481 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:34:46.953 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:34:47.425 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:34:47.889 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:34:48.358 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:34:48.828 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:34:49.299 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:34:49.770 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:34:50.243 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:34:50.716 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:34:51.184 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:34:51.653 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:34:52.125 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:34:52.595 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:34:53.064 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:34:53.533 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:34:54.005 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:34:54.474 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:34:54.940 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:34:55.411 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:34:55.882 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 03:34:56.353 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 03:34:56.823 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 03:34:57.294 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 03:34:57.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:57.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:34:57.697 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:57.697 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:57.713 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:57.713 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:57.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:34:57.719 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:34:57.719 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:34:57.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:34:57.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:34:57.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:57.721 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:34:57.721 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:34:57.721 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:34:57.721 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:34:57.762 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:34:57.762 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:34:57.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:57.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:34:57.763 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 03:34:58.231 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 03:34:58.703 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 03:34:59.176 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 03:34:59.648 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 03:35:00.120 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 03:35:00.587 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 03:35:01.060 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 03:35:01.532 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 03:35:02.000 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 03:35:02.471 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 03:35:02.942 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 03:35:03.415 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 03:35:03.887 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 03:35:04.359 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 03:35:04.831 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 03:35:05.297 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 03:35:05.762 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 03:35:06.228 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 03:35:06.699 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 03:35:07.172 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 03:35:07.644 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 03:35:08.116 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 03:35:08.588 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 03:35:09.059 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 03:35:09.531 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 03:35:10.003 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 03:35:10.471 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 03:35:10.940 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 03:35:11.408 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 03:35:11.878 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-06 03:35:12.350 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-06 03:35:12.823 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-06 03:35:13.295 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-06 03:35:13.767 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-06 03:35:14.240 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-06 03:35:14.710 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-06 03:35:15.183 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-06 03:35:15.651 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-06 03:35:16.116 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-06 03:35:16.582 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-06 03:35:17.055 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-06 03:35:17.525 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-06 03:35:17.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:35:17.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:35:17.774 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:35:17.775 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:35:17.775 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:35:17.789 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:35:17.789 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:35:17.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:35:17.794 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:35:17.794 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:35:17.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:35:17.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:35:17.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:35:17.796 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:35:17.796 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:35:17.796 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:35:17.796 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:35:17.801 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:35:17.801 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:35:17.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:35:17.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:35:17.994 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-06 03:35:18.458 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-06 03:35:18.925 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-06 03:35:19.398 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-06 03:35:19.871 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-06 03:35:20.343 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-06 03:35:20.816 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-06 03:35:21.289 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-06 03:35:21.760 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-06 03:35:22.228 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-06 03:35:22.690 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-06 03:35:23.155 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-06 03:35:23.628 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-06 03:35:24.100 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-06 03:35:24.571 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-06 03:35:25.044 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-06 03:35:25.517 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-06 03:35:25.988 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-06 03:35:26.460 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-06 03:35:26.931 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-06 03:35:27.401 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-06 03:35:27.872 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-06 03:35:28.346 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-06 03:35:28.817 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-06 03:35:29.289 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-06 03:35:29.760 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-06 03:35:30.231 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-06 03:35:30.702 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-06 03:35:31.173 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-06 03:35:31.643 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-06 03:35:32.117 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-06 03:35:32.589 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-06 03:35:33.061 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-06 03:35:33.532 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-06 03:35:34.003 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-06 03:35:34.474 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-06 03:35:34.945 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-06 03:35:35.417 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-06 03:35:35.890 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-06 03:35:36.362 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-06 03:35:36.833 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-06 03:35:37.304 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-06 03:35:37.776 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-06 03:35:37.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:35:37.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:35:37.814 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:35:37.814 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:35:37.826 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:35:37.826 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:35:37.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:35:37.832 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:35:37.832 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:35:37.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:35:37.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:35:37.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:35:37.833 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:35:37.834 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:35:37.834 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:35:37.834 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:35:37.864 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:35:37.864 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:35:37.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:35:37.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:35:38.245 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-06 03:35:38.718 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-06 03:35:39.190 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-06 03:35:39.663 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-06 03:35:40.134 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-06 03:35:40.607 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-06 03:35:41.079 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-06 03:35:41.550 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-06 03:35:42.017 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-06 03:35:42.484 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-06 03:35:42.953 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-06 03:35:43.425 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-06 03:35:43.890 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-06 03:35:44.358 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-06 03:35:44.827 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-06 03:35:45.295 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-06 03:35:45.761 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-06 03:35:46.233 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-06 03:35:46.697 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-06 03:35:47.163 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-06 03:35:47.627 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-06 03:35:48.092 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-06 03:35:48.556 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-06 03:35:49.021 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-06 03:35:49.486 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-06 03:35:49.951 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-06 03:35:50.417 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-06 03:35:50.881 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-06 03:35:51.348 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-06 03:35:51.818 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-06 03:35:52.282 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-06 03:35:52.747 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-06 03:35:53.211 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-06 03:35:53.679 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-06 03:35:54.149 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-06 03:35:54.619 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-06 03:35:55.084 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-06 03:35:55.549 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-06 03:35:56.014 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-06 03:35:56.481 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-06 03:35:56.951 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-06 03:35:57.423 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-06 03:35:57.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:35:57.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:35:57.874 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:35:57.874 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:35:57.874 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:35:57.887 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:35:57.887 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:35:57.887 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:35:57.887 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:35:57.890 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-06 03:35:57.890 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:35:57.890 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:35:57.890 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:35:57.890 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:35:57.890 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:35:57.890 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:35:57.890 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:35:57.890 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=17545 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:35:57.890 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=17545 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:35:57.890 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=17545 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:35:57.890 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=17545 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:35:57.890 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=17545 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:35:57.890 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=17545 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:35:57.890 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=17546 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:35:57.890 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=17546 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:35:57.890 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=17546 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:35:57.890 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=17546 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:35:57.890 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=17546 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:35:57.890 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=17546 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:35:57.890 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=17546 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:35:57.890 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=17546 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:35:57.890 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=17547 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:35:57.890 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=17547 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:35:57.890 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=17547 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:35:57.890 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=17547 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:35:57.891 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=17547 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:35:57.891 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=17547 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:35:57.891 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=17547 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:35:57.891 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=17547 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:36:02.892 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:36:02.892 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:36:02.893 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:36:02.893 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:36:02.893 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:36:02.893 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:36:02.913 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:36:02.914 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:36:02.914 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:36:02.915 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:36:02.915 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:36:02.918 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:36:02.918 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:36:02.918 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:36:02.918 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:36:02.918 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:36:02.918 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:36:02.919 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:36:02.919 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:36:02.919 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:36:02.922 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:36:02.922 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:36:02.922 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:36:02.922 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:36:02.922 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:36:02.922 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:36:02.923 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:36:02.923 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:36:02.923 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:36:02.925 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:36:02.925 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:36:02.926 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:36:02.926 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:36:02.926 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:36:02.926 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:36:02.926 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:36:02.926 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:36:02.926 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:36:02.930 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:36:02.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:36:02.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:36:02.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:36:02.930 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:36:02.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:36:02.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:36:02.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:02.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:36:02.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:36:02.931 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:36:02.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:02.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:02.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:02.931 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:36:02.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:02.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:02.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:02.931 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:36:02.931 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:36:02.931 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:36:02.931 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:36:02.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:02.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:02.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:02.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:36:02.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:02.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:02.932 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:02.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:02.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:02.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:02.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:02.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:02.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:02.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:02.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:02.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:02.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:02.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:02.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:02.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:02.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:02.934 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:36:02.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:02.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:02.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:02.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:02.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:02.934 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:36:02.934 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:36:02.934 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:36:02.934 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:36:02.934 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:36:02.934 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:36:07.941 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:36:07.941 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:36:07.941 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:36:07.941 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:36:07.941 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:36:07.941 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:36:07.948 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:36:07.949 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:36:07.949 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:36:07.949 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:36:07.949 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:36:07.952 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:36:07.952 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:36:07.952 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:36:07.952 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:36:07.952 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:36:07.952 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:36:07.952 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:36:07.952 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:36:07.952 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:36:07.954 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:36:07.954 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:36:07.954 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:36:07.954 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:36:07.954 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:36:07.954 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:36:07.954 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:36:07.955 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:36:07.955 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:36:07.956 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:36:07.956 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:36:07.956 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:36:07.956 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:36:07.956 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:36:07.956 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:36:07.956 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:36:07.957 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:36:07.957 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:36:07.959 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:36:07.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:36:07.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:36:07.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:36:07.959 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:36:07.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:36:07.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:36:07.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:36:07.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:07.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:36:07.959 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:36:07.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:07.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:07.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:07.959 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:36:07.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:07.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:07.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:07.959 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:36:07.959 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:36:07.959 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:36:07.959 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:36:07.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:07.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:07.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:07.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:36:07.960 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:07.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:07.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:07.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:07.960 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:07.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:07.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:07.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:07.960 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:07.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:07.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:07.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:07.960 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:07.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:07.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:07.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:07.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:07.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:07.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:07.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:07.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:07.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:07.964 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:36:08.434 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:36:08.485 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:36:08.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:08.488 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:36:08.490 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:36:08.510 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:08.510 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:08.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:08.524 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:08.524 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:08.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:08.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:08.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:08.527 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:08.527 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:08.527 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:36:08.527 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:36:08.571 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:08.571 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:08.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:08.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:08.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:08.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:08.773 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:08.774 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:08.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:08.789 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:08.789 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:08.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:08.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:08.791 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:08.791 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:08.791 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:36:08.791 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:36:08.804 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:08.804 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:08.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:08.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:08.903 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:36:08.961 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:36:08.961 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:36:08.962 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:36:08.962 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:36:09.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:09.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:09.008 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:09.008 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:09.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:09.025 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:09.025 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:09.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:09.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:09.027 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:09.027 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:09.027 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:36:09.027 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:36:09.035 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:09.035 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:09.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:09.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:09.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:09.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:09.248 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:09.248 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:09.266 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:09.266 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:09.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:09.272 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:09.272 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:09.272 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:09.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:09.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:09.274 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:09.274 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:09.274 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:36:09.274 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:36:09.319 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:36:09.319 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:36:09.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:09.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:09.372 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:36:09.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:09.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:09.627 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:09.627 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:09.627 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:36:09.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:09.642 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:09.642 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:09.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:09.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:09.644 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:09.644 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:09.644 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:36:09.644 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:36:09.649 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:36:09.649 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:36:09.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:09.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:09.840 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:36:09.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:09.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:09.947 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:09.947 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:09.947 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:36:09.962 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:36:09.962 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:36:09.962 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:36:09.962 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:36:09.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:09.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:09.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:09.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:09.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:09.966 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:09.966 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:09.966 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:36:09.966 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:36:09.972 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:36:09.972 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:36:09.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:09.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:10.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:10.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:10.264 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:10.264 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:10.264 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:36:10.281 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:10.281 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:10.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:10.287 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:10.287 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:10.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:10.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:10.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:10.289 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:10.289 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:10.289 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:36:10.289 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:36:10.305 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:10.305 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:10.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:10.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:10.308 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:36:10.780 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:36:10.963 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:36:10.964 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:36:10.964 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:36:10.964 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:36:11.250 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:36:11.721 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:36:11.965 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:36:11.965 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:36:11.965 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:36:11.965 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:36:12.192 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:36:12.663 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:36:12.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:12.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:12.820 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:12.820 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:12.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:12.835 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:12.835 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:12.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:12.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:12.837 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:12.837 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:12.837 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:36:12.837 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:36:12.842 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:12.842 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:12.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:12.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:12.966 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:36:12.967 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:36:12.967 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:36:12.967 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:36:13.133 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:36:13.604 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:36:14.074 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:36:14.541 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:36:15.008 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:36:15.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:15.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:15.400 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:15.400 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:15.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:15.416 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:15.416 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:15.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:15.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:15.418 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:15.418 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:15.418 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:36:15.418 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:36:15.422 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:15.422 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:15.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:15.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:15.474 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:36:15.941 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:36:16.412 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:36:16.883 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:36:17.355 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:36:17.827 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:36:17.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:17.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:17.984 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:17.984 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:17.998 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:17.998 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:17.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:18.004 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:18.004 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:18.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:18.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:18.006 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:18.006 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:18.006 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:18.006 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:36:18.006 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:36:18.007 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:36:18.007 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:36:18.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:18.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:18.291 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:36:18.759 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:36:19.226 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:36:19.690 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:36:20.155 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:36:20.619 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:36:20.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:20.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:20.704 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:20.705 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:20.705 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:36:20.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:20.713 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:20.713 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:20.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:20.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:20.714 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:20.714 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:20.714 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:36:20.714 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:36:20.756 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:36:20.757 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:36:20.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:20.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:21.084 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:36:21.548 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:36:22.019 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:36:22.485 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:36:22.956 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:36:23.424 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:36:23.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:23.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:23.504 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:23.504 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:23.504 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:36:23.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:23.514 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:23.514 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:23.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:23.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:23.516 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:23.516 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:23.516 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:36:23.517 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:36:23.556 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:36:23.556 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:36:23.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:23.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:23.892 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:36:24.361 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:36:24.832 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:36:25.303 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:36:25.770 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:36:26.238 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:36:26.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:26.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:26.321 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:26.321 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:26.321 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:36:26.333 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:36:26.334 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:36:26.334 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:36:26.334 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:36:26.335 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:36:26.335 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:36:26.335 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:36:26.335 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:36:26.335 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:36:26.335 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:36:26.335 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:36:31.341 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:36:31.341 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:36:31.341 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:36:31.341 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:36:31.341 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:36:31.341 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:36:31.356 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:36:31.356 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:36:31.356 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:36:31.357 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:36:31.357 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:36:31.359 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:36:31.359 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:36:31.359 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:36:31.359 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:36:31.359 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:36:31.360 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:36:31.360 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:36:31.360 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:36:31.360 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:36:31.361 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:36:31.361 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:36:31.361 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:36:31.361 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:36:31.361 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:36:31.361 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:36:31.361 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:36:31.361 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:36:31.361 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:36:31.362 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:36:31.362 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:36:31.362 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:36:31.362 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:36:31.363 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:36:31.363 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:36:31.363 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:36:31.363 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:36:31.363 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:36:31.365 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:36:31.365 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:36:31.365 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:31.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:31.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:31.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:31.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:31.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:31.370 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:36:31.835 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:36:31.888 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:36:31.888 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:36:31.890 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:36:31.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:31.913 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:31.913 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:31.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:31.932 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:31.933 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:31.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:31.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:31.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:31.940 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:31.940 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:31.940 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:36:31.940 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:36:31.972 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:31.973 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:31.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:31.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:32.305 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:36:32.367 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:36:32.368 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:36:32.368 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:36:32.368 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:36:32.778 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:36:33.249 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:36:33.369 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:36:33.369 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:36:33.369 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:36:33.369 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:36:33.720 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:36:34.191 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:36:34.371 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:36:34.371 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:36:34.371 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:36:34.371 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:36:34.662 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:36:35.083 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:35.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:35.087 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:35.087 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:35.101 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:35.101 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:35.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:35.107 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:35.107 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:35.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:35.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:35.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:35.109 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:35.109 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:35.109 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:36:35.109 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:36:35.129 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:36:35.129 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:36:35.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:35.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:35.132 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:36:35.371 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:36:35.372 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:36:35.372 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:36:35.372 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:36:35.603 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:36:36.074 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:36:36.373 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:36:36.373 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:36:36.373 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:36:36.373 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:36:36.547 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:36:37.018 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:36:37.486 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:36:37.957 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:36:38.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:38.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:38.333 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:38.333 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:38.333 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:36:38.349 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:38.349 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:38.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:38.355 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:38.355 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:38.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:38.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:38.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:38.356 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:38.356 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:38.356 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:36:38.356 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:36:38.374 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:38.374 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:38.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:38.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:38.423 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:36:38.893 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:36:39.361 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:36:39.826 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:36:40.296 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:36:40.765 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:36:41.230 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:36:41.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:41.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:41.652 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:41.652 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:41.671 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:41.671 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:41.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:41.678 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:41.678 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:41.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:41.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:41.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:41.679 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:41.680 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:41.680 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:36:41.680 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:36:41.697 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:36:41.698 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:36:41.698 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:36:41.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:41.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:42.165 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:36:42.636 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:36:43.109 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:36:43.582 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:36:44.050 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:36:44.514 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:36:44.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:44.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:44.852 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:44.852 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:44.852 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:36:44.865 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:36:44.865 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:36:44.865 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:36:44.865 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:36:44.868 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:36:44.868 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:36:44.868 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:36:44.868 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:36:44.868 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:36:44.868 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:36:44.868 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:36:44.868 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2935 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:36:44.868 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2935 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:36:44.868 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2935 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:36:44.868 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2935 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:36:44.868 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2935 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:36:44.868 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=2935 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:36:49.872 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:36:49.872 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:36:49.872 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:36:49.872 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:36:49.872 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:36:49.872 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:36:49.882 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:36:49.883 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:36:49.883 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:36:49.883 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:36:49.883 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:36:49.885 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:36:49.885 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:36:49.885 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:36:49.885 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:36:49.885 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:36:49.885 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:36:49.885 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:36:49.885 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:36:49.885 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:36:49.887 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:36:49.887 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:36:49.887 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:36:49.887 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:36:49.887 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:36:49.887 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:36:49.887 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:36:49.887 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:36:49.888 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:36:49.889 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:36:49.889 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:36:49.889 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:36:49.889 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:36:49.889 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:36:49.889 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:36:49.889 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:36:49.889 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:36:49.889 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:36:49.891 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:36:49.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:36:49.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:36:49.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:36:49.891 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:36:49.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:36:49.892 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:36:49.892 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:36:49.892 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:49.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:49.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:49.893 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:36:49.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:36:49.893 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:36:49.896 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:36:50.366 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:36:50.421 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:36:50.423 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:36:50.425 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:36:50.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:50.448 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:50.448 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:50.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:50.463 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:50.463 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:50.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:50.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:50.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:50.467 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:50.467 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:50.467 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:36:50.467 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:36:50.504 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:50.504 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:50.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:50.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:50.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:50.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:50.824 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:50.824 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:50.825 [WARNING] transceiver.py:257 (MS@172.18.59.22:6700) RX TRXD message (fn=203 tn=4 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:36:50.833 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:36:50.841 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:50.841 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:50.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:50.847 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:50.847 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:50.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:50.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:50.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:50.849 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:50.849 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:50.849 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:36:50.849 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:36:50.878 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:36:50.878 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:36:50.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:50.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:50.895 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:36:50.895 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:36:50.896 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:36:50.899 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:36:51.297 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:36:51.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:51.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:51.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:51.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:51.352 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:36:51.373 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:51.373 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:51.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:51.381 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:51.381 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:51.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:51.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:51.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:51.383 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:51.383 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:51.383 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:36:51.383 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:36:51.432 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:51.432 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:51.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:51.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:51.763 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:36:51.896 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:36:51.896 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:36:51.896 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:36:51.899 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:36:52.229 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:36:52.701 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:36:52.896 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:36:52.897 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:36:52.897 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:36:52.900 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:36:53.174 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:36:53.645 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:36:53.898 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:36:53.898 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:36:53.898 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:36:53.901 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:36:54.116 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:36:54.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:54.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:54.511 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:54.511 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:54.528 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:54.528 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:54.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:54.534 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:54.534 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:54.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:36:54.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:54.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:54.535 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:36:54.535 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:36:54.535 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:36:54.536 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:36:54.586 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:36:54.586 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:36:54.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:54.587 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:36:54.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:54.899 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:36:54.899 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:36:54.900 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:36:54.902 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:36:55.058 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:36:55.531 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:36:56.002 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:36:56.474 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:36:56.944 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:36:57.417 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:36:57.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:36:57.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:36:57.504 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:36:57.504 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:36:57.504 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:36:57.512 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:36:57.512 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:36:57.512 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:36:57.512 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:36:57.512 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:36:57.513 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:36:57.513 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:36:57.513 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:36:57.513 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:36:57.513 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:36:57.513 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:37:02.520 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:37:02.520 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:37:02.520 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:37:02.520 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:37:02.520 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:37:02.520 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:37:02.522 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:37:02.523 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:37:02.523 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:37:02.523 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:37:02.523 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:37:02.524 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:37:02.524 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:37:02.524 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:37:02.524 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:37:02.524 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:37:02.524 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:37:02.524 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:37:02.524 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:37:02.524 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:37:02.525 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:37:02.525 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:37:02.525 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:37:02.526 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:37:02.526 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:37:02.526 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:37:02.526 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:37:02.526 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:37:02.526 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:37:02.527 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:37:02.527 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:37:02.527 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:37:02.527 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:37:02.527 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:37:02.527 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:37:02.527 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:37:02.527 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:37:02.527 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:37:02.529 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:37:02.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:37:02.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:37:02.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:37:02.529 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:37:02.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:37:02.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:37:02.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:37:02.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:37:02.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:37:02.530 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:37:02.530 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:37:02.530 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:37:02.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:37:02.531 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:37:02.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:37:02.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:37:02.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:37:02.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:37:02.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:37:02.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:37:02.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:37:02.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:37:02.534 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:37:03.006 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:37:03.057 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:37:03.059 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:37:03.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:37:03.063 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:37:03.084 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:37:03.084 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:37:03.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:37:03.107 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:37:03.107 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:37:03.108 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:37:03.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:37:03.115 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:03.116 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:37:03.116 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:37:03.116 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:37:03.116 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:37:03.144 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:37:03.144 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:37:03.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:03.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:03.479 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:37:03.532 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:37:03.532 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:37:03.532 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:37:03.532 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:37:03.949 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:37:04.420 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:37:04.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:04.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:37:04.446 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:37:04.446 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:37:04.457 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:37:04.457 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:37:04.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:37:04.463 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:37:04.463 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:37:04.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:37:04.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:37:04.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:04.464 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:37:04.465 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:37:04.465 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:37:04.465 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:37:04.510 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:37:04.510 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:37:04.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:04.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:04.533 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:37:04.534 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:37:04.534 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:37:04.534 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:37:04.890 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:37:05.363 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:37:05.534 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:37:05.535 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:37:05.535 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:37:05.535 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:37:05.836 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:37:06.303 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:37:06.535 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:37:06.535 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:37:06.535 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:37:06.535 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:37:06.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:06.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:37:06.623 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:37:06.623 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:37:06.623 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:37:06.631 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:37:06.631 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:37:06.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:37:06.637 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:37:06.637 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:37:06.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:37:06.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:37:06.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:06.638 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:37:06.638 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:37:06.638 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:37:06.638 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:37:06.672 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:37:06.672 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:37:06.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:06.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:06.765 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:37:07.230 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:37:07.536 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:37:07.536 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:37:07.536 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:37:07.537 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:37:07.702 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:37:08.174 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:37:08.645 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:37:09.118 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:37:09.591 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:37:10.063 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:37:10.534 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:37:11.007 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:37:11.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:11.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:37:11.469 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:37:11.469 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:37:11.480 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:37:11.489 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:37:11.489 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:37:11.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:37:11.496 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:37:11.496 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:37:11.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:37:11.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:37:11.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:11.500 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:37:11.500 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:37:11.500 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:37:11.500 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:37:11.525 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:37:11.526 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:37:11.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:11.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:11.952 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:37:12.423 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:37:12.895 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:37:13.365 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:37:13.838 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:37:14.310 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:37:14.781 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:37:15.253 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:37:15.726 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:37:16.191 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:37:16.660 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:37:17.126 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:37:17.597 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:37:18.068 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:37:18.538 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:37:19.009 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:37:19.479 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:37:19.950 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:37:20.421 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:37:20.892 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:37:21.363 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 03:37:21.831 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 03:37:22.303 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 03:37:22.773 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 03:37:23.245 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 03:37:23.716 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 03:37:24.185 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 03:37:24.654 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 03:37:25.125 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 03:37:25.595 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 03:37:26.064 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 03:37:26.537 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 03:37:27.008 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 03:37:27.479 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 03:37:27.948 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 03:37:28.420 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 03:37:28.891 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 03:37:29.362 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 03:37:29.833 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 03:37:30.303 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 03:37:30.768 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 03:37:31.232 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 03:37:31.495 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:37:31.496 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:37:31.496 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:37:31.497 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:37:31.497 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:37:31.497 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:37:31.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:37:31.499 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:37:31.499 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:37:31.499 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:37:31.499 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:37:31.499 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:37:31.499 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:37:31.499 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:37:31.499 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6281 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:37:31.499 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6281 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:37:31.499 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6281 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:37:31.499 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=6281 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:37:36.507 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:37:36.507 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:37:36.507 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:37:36.507 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:37:36.508 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:37:36.508 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:37:36.521 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:37:36.522 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:37:36.522 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:37:36.522 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:37:36.522 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:37:36.525 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:37:36.525 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:37:36.526 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:37:36.526 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:37:36.526 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:37:36.526 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:37:36.526 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:37:36.526 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:37:36.526 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:37:36.528 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:37:36.529 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:37:36.529 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:37:36.529 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:37:36.529 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:37:36.529 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:37:36.529 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:37:36.529 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:37:36.529 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:37:36.531 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:37:36.531 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:37:36.531 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:37:36.531 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:37:36.531 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:37:36.531 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:37:36.531 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:37:36.531 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:37:36.531 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:37:36.534 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:37:36.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:37:36.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:37:36.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:37:36.534 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:37:36.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:37:36.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:37:36.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:37:36.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:37:36.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:37:36.534 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:37:36.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:37:36.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:37:36.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:37:36.534 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:37:36.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:37:36.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:37:36.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:37:36.534 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:37:36.534 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:37:36.534 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:37:36.535 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:37:36.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:37:36.539 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:37:37.010 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:37:37.061 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:37:37.063 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:37:37.064 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:37:37.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:37:37.082 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:37:37.082 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:37:37.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:37:37.096 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:37:37.096 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:37:37.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:37:37.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:37:37.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:37.100 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:37:37.100 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:37:37.100 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:37:37.100 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:37:37.147 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:37:37.147 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:37:37.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:37.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:37.481 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:37:37.537 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:37:37.537 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:37:37.538 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:37:37.538 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:37:37.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:37.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:37:37.764 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:37:37.764 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:37:37.783 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:37:37.783 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:37:37.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:37:37.789 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:37:37.789 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:37:37.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:37:37.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:37:37.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:37.791 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:37:37.791 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:37:37.791 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:37:37.791 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:37:37.801 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:37:37.801 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:37:37.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:37.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:37.951 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:37:38.424 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:37:38.538 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:37:38.538 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:37:38.539 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:37:38.539 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:37:38.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:38.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:37:38.732 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:37:38.733 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:37:38.733 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:37:38.751 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:37:38.751 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:37:38.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:37:38.757 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:37:38.757 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:37:38.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:37:38.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:37:38.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:38.759 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:37:38.759 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:37:38.759 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:37:38.759 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:37:38.794 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:37:38.794 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:37:38.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:38.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:38.894 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:37:39.367 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:37:39.539 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:37:39.539 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:37:39.539 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:37:39.539 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:37:39.839 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:37:40.310 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:37:40.540 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:37:40.540 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:37:40.541 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:37:40.541 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:37:40.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:40.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:37:40.704 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:37:40.705 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:37:40.722 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:37:40.722 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:37:40.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:37:40.728 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:37:40.728 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:37:40.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:37:40.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:37:40.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:40.730 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:37:40.730 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:37:40.730 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:37:40.730 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:37:40.779 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:37:40.779 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:37:40.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:40.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:37:40.780 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:37:41.249 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:37:41.541 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:37:41.541 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:37:41.541 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:37:41.542 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:37:41.718 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:37:42.191 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:37:42.663 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:37:43.135 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:37:43.599 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:37:44.063 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:37:44.526 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:37:44.993 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:37:45.458 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:37:45.923 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:37:46.387 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:37:46.858 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:37:47.330 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:37:47.801 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:37:48.272 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:37:48.743 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:37:49.214 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:37:49.684 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:37:50.155 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:37:50.626 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:37:51.096 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:37:51.567 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:37:52.039 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:37:52.509 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:37:52.980 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:37:53.460 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:37:53.931 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:37:54.402 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:37:54.870 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:37:55.335 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 03:37:55.801 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 03:37:56.270 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 03:37:56.735 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 03:37:57.201 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 03:37:57.673 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 03:37:58.145 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 03:37:58.617 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 03:37:59.089 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 03:37:59.560 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 03:38:00.030 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 03:38:00.502 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 03:38:00.726 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:00.726 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:00.727 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:38:00.728 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:38:00.728 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:38:00.728 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:38:00.728 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:38:00.729 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:38:00.729 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:38:00.729 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:38:00.729 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:38:00.729 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:38:00.729 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:38:00.729 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:38:05.736 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:38:05.736 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:38:05.736 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:38:05.736 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:38:05.736 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:38:05.736 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:38:05.745 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:38:05.747 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:38:05.747 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:38:05.747 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:38:05.747 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:38:05.751 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:38:05.751 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:38:05.751 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:38:05.751 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:38:05.751 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:38:05.751 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:38:05.752 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:38:05.752 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:38:05.752 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:38:05.755 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:38:05.755 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:38:05.755 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:38:05.756 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:38:05.756 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:38:05.756 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:38:05.756 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:38:05.756 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:38:05.756 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:38:05.759 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:38:05.759 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:38:05.759 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:38:05.759 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:38:05.759 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:38:05.760 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:38:05.760 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:38:05.760 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:38:05.760 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:38:05.765 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:38:05.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:38:05.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:38:05.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:38:05.765 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:38:05.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:38:05.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:38:05.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:38:05.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:38:05.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:38:05.765 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:38:05.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:38:05.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:38:05.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:38:05.765 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:38:05.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:38:05.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:38:05.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:38:05.766 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:38:05.766 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:38:05.766 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:38:05.766 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:38:05.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:38:05.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:38:05.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:38:05.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:38:05.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:38:05.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:38:05.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:38:05.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:38:05.767 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:38:05.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:38:05.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:38:05.767 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:38:05.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:38:05.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:38:05.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:38:05.767 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:38:05.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:38:05.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:38:05.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:38:05.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:38:05.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:38:05.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:38:05.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:38:05.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:38:05.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:38:05.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:38:05.771 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:38:06.235 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:38:06.295 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:38:06.296 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:38:06.298 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:38:06.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:38:06.313 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:06.313 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:06.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:38:06.329 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:06.329 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:06.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:38:06.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:38:06.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:06.338 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:38:06.338 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:38:06.339 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:38:06.339 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:38:06.374 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:38:06.374 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:38:06.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:06.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:06.705 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:38:06.769 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:38:06.769 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:38:06.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:38:06.771 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:38:07.174 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:38:07.645 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:38:07.770 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:38:07.770 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:38:07.772 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:38:07.772 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:38:08.115 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:38:08.585 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:38:08.771 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:38:08.771 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:38:08.773 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:38:08.774 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:38:08.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:08.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:38:08.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:08.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:08.824 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:08.824 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:08.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:38:08.830 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:08.830 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:08.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:38:08.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:38:08.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:08.832 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:38:08.832 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:38:08.832 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:38:08.832 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:38:08.865 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:38:08.865 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:38:08.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:08.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:09.053 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:38:09.525 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:38:09.772 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:38:09.772 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:38:09.775 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:38:09.775 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:38:09.996 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:38:10.465 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:38:10.773 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:38:10.773 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:38:10.776 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:38:10.776 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:38:10.934 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:38:11.406 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:38:11.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:11.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:38:11.547 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:11.547 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:11.547 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:38:11.564 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:11.564 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:11.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:38:11.570 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:11.570 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:11.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:38:11.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:38:11.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:11.572 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:38:11.572 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:38:11.572 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:38:11.572 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:38:11.589 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:38:11.589 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:38:11.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:11.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:11.876 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:38:12.347 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:38:12.819 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:38:13.293 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:38:13.765 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:38:14.237 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:38:14.708 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:38:14.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:14.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:38:14.867 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:14.867 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:14.885 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:14.885 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:14.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:38:14.891 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:14.891 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:14.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:38:14.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:38:14.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:14.892 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:38:14.892 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:38:14.892 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:38:14.892 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:38:14.942 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:38:14.942 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:38:14.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:14.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:15.179 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:38:15.651 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:38:16.120 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:38:16.591 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:38:17.062 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:38:17.532 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:38:18.004 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:38:18.474 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:38:18.942 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:38:19.413 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:38:19.877 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:38:20.342 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:38:20.807 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:38:21.271 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:38:21.739 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:38:22.203 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:38:22.667 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:38:23.135 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:38:23.601 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:38:24.070 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:38:24.541 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 03:38:25.011 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 03:38:25.478 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 03:38:25.943 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 03:38:26.407 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 03:38:26.872 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 03:38:27.337 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 03:38:27.801 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 03:38:28.266 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 03:38:28.734 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 03:38:29.198 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 03:38:29.661 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 03:38:30.129 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 03:38:30.594 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 03:38:31.058 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 03:38:31.523 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 03:38:31.989 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 03:38:32.452 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 03:38:32.917 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 03:38:33.380 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 03:38:33.844 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 03:38:34.312 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 03:38:34.781 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 03:38:34.888 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:34.889 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:34.889 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:38:34.892 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:38:34.893 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:38:34.893 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:38:34.893 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:38:34.894 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:38:34.894 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:38:34.894 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:38:34.894 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:38:34.894 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:38:34.894 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:38:34.894 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:38:39.899 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:38:39.899 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:38:39.899 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:38:39.899 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:38:39.899 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:38:39.899 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:38:39.909 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:38:39.910 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:38:39.911 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:38:39.911 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:38:39.911 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:38:39.915 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:38:39.916 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:38:39.916 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:38:39.916 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:38:39.916 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:38:39.916 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:38:39.916 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:38:39.916 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:38:39.917 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:38:39.919 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:38:39.919 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:38:39.919 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:38:39.919 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:38:39.919 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:38:39.920 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:38:39.920 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:38:39.920 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:38:39.920 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:38:39.922 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:38:39.922 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:38:39.922 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:38:39.922 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:38:39.922 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:38:39.922 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:38:39.922 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:38:39.922 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:38:39.922 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:38:39.925 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:38:39.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:38:39.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:38:39.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:38:39.925 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:38:39.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:38:39.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:38:39.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:38:39.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:38:39.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:38:39.925 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:38:39.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:38:39.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:38:39.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:38:39.925 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:38:39.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:38:39.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:38:39.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:38:39.925 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:38:39.925 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:38:39.925 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:38:39.926 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:38:39.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:38:39.930 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:38:40.393 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:38:40.454 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:38:40.456 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:38:40.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:38:40.458 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:38:40.479 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:40.479 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:40.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:38:40.494 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:40.494 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:40.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:38:40.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:38:40.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:40.499 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:38:40.499 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:38:40.499 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:38:40.499 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:38:40.530 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:38:40.531 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:38:40.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:40.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:40.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:40.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:38:40.750 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:40.750 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:40.764 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:40.764 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:40.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:38:40.770 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:40.770 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:40.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:38:40.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:38:40.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:40.771 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:38:40.771 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:38:40.771 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:38:40.771 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:38:40.813 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:38:40.813 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:38:40.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:40.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:40.858 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:38:40.928 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:38:40.928 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:38:40.928 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:38:40.928 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:38:41.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:41.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:38:41.145 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:41.145 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:41.145 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:38:41.164 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:41.164 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:41.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:38:41.170 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:41.170 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:41.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:38:41.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:38:41.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:41.171 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:38:41.171 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:38:41.171 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:38:41.171 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:38:41.179 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:38:41.179 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:38:41.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:41.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:41.327 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:38:41.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:41.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:38:41.721 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:41.721 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:41.736 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:41.736 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:41.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:38:41.741 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:41.741 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:41.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:38:41.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:38:41.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:41.744 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:38:41.744 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:38:41.744 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:38:41.744 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:38:41.793 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:38:41.796 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:38:41.796 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:38:41.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:41.797 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:41.929 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:38:41.929 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:38:41.929 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:38:41.929 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:38:42.259 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:38:42.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:42.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:38:42.343 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:42.343 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:42.343 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:38:42.353 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:38:42.353 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:38:42.353 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:38:42.353 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:38:42.355 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:38:42.355 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:38:42.355 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:38:42.355 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:38:42.355 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:38:42.355 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:38:42.355 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:38:42.355 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=533 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:38:42.355 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=533 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:38:42.355 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=533 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:38:42.355 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=533 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:38:42.355 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=533 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:38:42.355 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=533 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:38:47.359 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:38:47.359 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:38:47.359 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:38:47.359 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:38:47.359 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:38:47.359 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:38:47.371 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:38:47.371 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:38:47.371 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:38:47.372 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:38:47.372 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:38:47.374 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:38:47.374 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:38:47.374 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:38:47.374 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:38:47.375 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:38:47.375 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:38:47.375 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:38:47.375 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:38:47.375 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:38:47.377 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:38:47.377 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:38:47.377 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:38:47.377 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:38:47.377 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:38:47.377 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:38:47.377 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:38:47.377 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:38:47.378 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:38:47.380 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:38:47.380 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:38:47.380 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:38:47.380 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:38:47.380 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:38:47.380 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:38:47.381 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:38:47.381 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:38:47.381 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:38:47.384 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:38:47.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:38:47.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:38:47.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:38:47.384 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:38:47.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:38:47.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:38:47.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:38:47.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:38:47.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:38:47.385 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:38:47.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:38:47.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:38:47.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:38:47.385 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:38:47.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:38:47.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:38:47.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:38:47.385 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:38:47.385 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:38:47.385 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:38:47.385 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:38:47.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:38:47.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:38:47.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:38:47.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:38:47.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:38:47.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:38:47.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:38:47.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:38:47.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:38:47.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:38:47.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:38:47.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:38:47.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:38:47.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:38:47.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:38:47.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:38:47.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:38:47.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:38:47.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:38:47.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:38:47.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:38:47.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:38:47.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:38:47.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:38:47.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:38:47.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:38:47.390 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:38:47.862 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:38:47.911 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:38:47.912 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:38:47.913 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:38:47.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:38:47.930 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:47.930 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:47.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:38:47.951 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:38:47.951 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:38:47.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:38:47.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:38:47.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:47.958 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:38:47.958 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:38:47.959 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:38:47.959 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:38:48.000 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:38:48.000 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:38:48.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:48.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:38:48.334 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:38:48.389 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:38:48.389 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:38:48.390 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:38:48.390 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:38:48.805 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:38:49.275 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:38:49.390 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:38:49.391 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:38:49.391 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:38:49.391 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:38:49.747 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:38:50.217 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:38:50.392 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:38:50.392 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:38:50.392 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:38:50.393 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:38:50.688 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:38:51.159 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:38:51.394 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:38:51.394 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:38:51.394 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:38:51.394 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:38:51.630 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:38:52.100 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:38:52.395 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:38:52.395 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:38:52.396 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:38:52.396 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:38:52.571 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:38:53.042 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:38:53.513 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:38:53.984 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:38:54.454 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:38:54.925 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:38:55.398 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:38:55.871 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:38:56.343 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:38:56.814 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:38:57.285 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:38:57.755 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:38:58.226 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:38:58.697 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:38:59.168 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:38:59.638 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:39:00.109 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:39:00.580 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:39:01.051 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:39:01.522 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:39:01.993 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:39:02.463 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:39:02.934 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:39:03.405 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:39:03.876 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:39:04.346 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:39:04.817 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:39:05.287 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:39:05.759 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:39:06.233 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 03:39:06.705 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 03:39:07.178 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 03:39:07.651 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 03:39:08.124 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 03:39:08.594 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 03:39:09.058 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 03:39:09.531 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 03:39:10.004 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 03:39:10.476 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 03:39:10.947 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 03:39:11.417 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 03:39:11.888 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 03:39:12.354 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 03:39:12.822 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 03:39:13.291 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 03:39:13.759 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 03:39:14.226 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 03:39:14.691 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 03:39:15.159 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 03:39:15.626 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 03:39:16.096 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 03:39:16.567 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 03:39:17.035 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 03:39:17.505 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 03:39:17.969 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 03:39:18.436 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 03:39:18.903 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 03:39:19.371 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 03:39:19.841 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 03:39:20.314 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 03:39:20.787 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 03:39:20.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:39:20.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:39:20.961 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:39:20.961 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:39:20.974 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:39:20.974 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:39:20.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:39:20.979 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:39:20.979 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:39:20.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:39:20.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:39:20.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:39:20.981 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:39:20.981 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:39:20.981 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:39:20.981 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:39:21.023 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:39:21.023 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:39:21.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:39:21.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:39:21.259 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 03:39:21.732 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 03:39:22.205 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-06 03:39:22.677 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-06 03:39:23.146 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-06 03:39:23.618 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-06 03:39:24.091 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-06 03:39:24.561 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-06 03:39:25.032 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-06 03:39:25.498 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-06 03:39:25.964 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-06 03:39:26.429 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-06 03:39:26.895 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-06 03:39:27.362 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-06 03:39:27.831 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-06 03:39:28.299 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-06 03:39:28.765 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-06 03:39:29.232 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-06 03:39:29.701 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-06 03:39:30.168 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-06 03:39:30.637 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-06 03:39:31.106 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-06 03:39:31.576 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-06 03:39:32.046 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-06 03:39:32.513 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-06 03:39:32.979 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-06 03:39:33.445 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-06 03:39:33.915 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-06 03:39:34.387 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-06 03:39:34.859 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-06 03:39:35.332 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-06 03:39:35.805 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-06 03:39:36.277 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-06 03:39:36.749 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-06 03:39:37.219 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-06 03:39:37.691 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-06 03:39:38.164 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-06 03:39:38.636 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-06 03:39:39.106 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-06 03:39:39.578 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-06 03:39:40.044 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-06 03:39:40.512 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-06 03:39:40.980 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-06 03:39:41.444 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-06 03:39:41.913 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-06 03:39:42.378 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-06 03:39:42.846 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-06 03:39:43.311 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-06 03:39:43.776 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-06 03:39:44.243 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-06 03:39:44.711 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-06 03:39:45.179 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-06 03:39:45.645 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-06 03:39:46.112 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-06 03:39:46.578 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-06 03:39:47.043 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-06 03:39:47.508 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-06 03:39:47.974 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-06 03:39:48.443 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-06 03:39:48.909 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-06 03:39:49.375 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-06 03:39:49.847 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-06 03:39:50.318 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-06 03:39:50.790 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-06 03:39:51.263 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-06 03:39:51.735 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-06 03:39:52.205 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-06 03:39:52.677 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-06 03:39:53.147 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-06 03:39:53.619 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-06 03:39:54.093 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-06 03:39:54.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:39:54.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:39:54.565 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:39:54.565 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:39:54.565 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:39:54.565 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-06 03:39:54.575 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:39:54.575 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:39:54.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:39:54.581 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:39:54.581 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:39:54.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:39:54.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:39:54.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:39:54.582 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:39:54.582 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:39:54.582 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:39:54.582 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:39:54.609 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:39:54.609 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:39:54.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:39:54.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:39:55.036 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-06 03:39:55.505 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-06 03:39:55.976 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-06 03:39:56.448 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-06 03:39:56.919 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-06 03:39:57.390 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-06 03:39:57.861 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-06 03:39:58.332 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-06 03:39:58.802 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-06 03:39:59.273 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-06 03:39:59.744 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-06 03:40:00.215 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-06 03:40:00.685 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-06 03:40:01.156 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-06 03:40:01.629 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-06 03:40:02.102 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-06 03:40:02.573 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-06 03:40:03.044 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-06 03:40:03.515 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-06 03:40:03.986 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-06 03:40:04.457 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-06 03:40:04.928 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-06 03:40:05.398 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-06 03:40:05.869 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-06 03:40:06.340 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-06 03:40:06.811 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-06 03:40:07.281 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-06 03:40:07.752 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-06 03:40:08.223 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-06 03:40:08.696 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-06 03:40:09.169 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-06 03:40:09.641 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-06 03:40:10.112 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-06 03:40:10.582 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-06 03:40:11.052 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-06 03:40:11.524 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-06 03:40:11.995 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-06 03:40:12.465 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-06 03:40:12.935 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-03-06 03:40:13.403 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-03-06 03:40:13.868 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-03-06 03:40:14.334 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-03-06 03:40:14.802 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-03-06 03:40:15.267 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-03-06 03:40:15.734 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-03-06 03:40:16.205 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-03-06 03:40:16.674 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-03-06 03:40:17.143 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-03-06 03:40:17.611 [DEBUG] clck_gen.py:113 IND CLOCK 19584
2026-03-06 03:40:18.082 [DEBUG] clck_gen.py:113 IND CLOCK 19686
2026-03-06 03:40:18.553 [DEBUG] clck_gen.py:113 IND CLOCK 19788
2026-03-06 03:40:19.019 [DEBUG] clck_gen.py:113 IND CLOCK 19890
2026-03-06 03:40:19.486 [DEBUG] clck_gen.py:113 IND CLOCK 19992
2026-03-06 03:40:19.956 [DEBUG] clck_gen.py:113 IND CLOCK 20094
2026-03-06 03:40:20.427 [DEBUG] clck_gen.py:113 IND CLOCK 20196
2026-03-06 03:40:20.899 [DEBUG] clck_gen.py:113 IND CLOCK 20298
2026-03-06 03:40:21.372 [DEBUG] clck_gen.py:113 IND CLOCK 20400
2026-03-06 03:40:21.841 [DEBUG] clck_gen.py:113 IND CLOCK 20502
2026-03-06 03:40:22.309 [DEBUG] clck_gen.py:113 IND CLOCK 20604
2026-03-06 03:40:22.778 [DEBUG] clck_gen.py:113 IND CLOCK 20706
2026-03-06 03:40:23.247 [DEBUG] clck_gen.py:113 IND CLOCK 20808
2026-03-06 03:40:23.714 [DEBUG] clck_gen.py:113 IND CLOCK 20910
2026-03-06 03:40:24.184 [DEBUG] clck_gen.py:113 IND CLOCK 21012
2026-03-06 03:40:24.655 [DEBUG] clck_gen.py:113 IND CLOCK 21114
2026-03-06 03:40:25.121 [DEBUG] clck_gen.py:113 IND CLOCK 21216
2026-03-06 03:40:25.588 [DEBUG] clck_gen.py:113 IND CLOCK 21318
2026-03-06 03:40:26.059 [DEBUG] clck_gen.py:113 IND CLOCK 21420
2026-03-06 03:40:26.530 [DEBUG] clck_gen.py:113 IND CLOCK 21522
2026-03-06 03:40:26.998 [DEBUG] clck_gen.py:113 IND CLOCK 21624
2026-03-06 03:40:27.465 [DEBUG] clck_gen.py:113 IND CLOCK 21726
2026-03-06 03:40:27.939 [DEBUG] clck_gen.py:113 IND CLOCK 21828
2026-03-06 03:40:28.408 [DEBUG] clck_gen.py:113 IND CLOCK 21930
2026-03-06 03:40:28.878 [DEBUG] clck_gen.py:113 IND CLOCK 22032
2026-03-06 03:40:29.349 [DEBUG] clck_gen.py:113 IND CLOCK 22134
2026-03-06 03:40:29.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:40:29.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:40:29.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:40:29.801 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:40:29.814 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:40:29.814 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:40:29.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:40:29.816 [DEBUG] clck_gen.py:113 IND CLOCK 22236
2026-03-06 03:40:29.820 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:40:29.820 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:40:29.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:40:29.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:40:29.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:40:29.822 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:40:29.822 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:40:29.822 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:40:29.822 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:40:29.859 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:40:29.859 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:40:29.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:40:29.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:40:30.287 [DEBUG] clck_gen.py:113 IND CLOCK 22338
2026-03-06 03:40:30.763 [DEBUG] clck_gen.py:113 IND CLOCK 22440
2026-03-06 03:40:31.229 [DEBUG] clck_gen.py:113 IND CLOCK 22542
2026-03-06 03:40:31.695 [DEBUG] clck_gen.py:113 IND CLOCK 22644
2026-03-06 03:40:32.160 [DEBUG] clck_gen.py:113 IND CLOCK 22746
2026-03-06 03:40:32.630 [DEBUG] clck_gen.py:113 IND CLOCK 22848
2026-03-06 03:40:33.099 [DEBUG] clck_gen.py:113 IND CLOCK 22950
2026-03-06 03:40:33.563 [DEBUG] clck_gen.py:113 IND CLOCK 23052
2026-03-06 03:40:34.029 [DEBUG] clck_gen.py:113 IND CLOCK 23154
2026-03-06 03:40:34.497 [DEBUG] clck_gen.py:113 IND CLOCK 23256
2026-03-06 03:40:34.963 [DEBUG] clck_gen.py:113 IND CLOCK 23358
2026-03-06 03:40:35.429 [DEBUG] clck_gen.py:113 IND CLOCK 23460
2026-03-06 03:40:35.897 [DEBUG] clck_gen.py:113 IND CLOCK 23562
2026-03-06 03:40:36.363 [DEBUG] clck_gen.py:113 IND CLOCK 23664
2026-03-06 03:40:36.829 [DEBUG] clck_gen.py:113 IND CLOCK 23766
2026-03-06 03:40:37.299 [DEBUG] clck_gen.py:113 IND CLOCK 23868
2026-03-06 03:40:37.765 [DEBUG] clck_gen.py:113 IND CLOCK 23970
2026-03-06 03:40:38.234 [DEBUG] clck_gen.py:113 IND CLOCK 24072
2026-03-06 03:40:38.706 [DEBUG] clck_gen.py:113 IND CLOCK 24174
2026-03-06 03:40:39.173 [DEBUG] clck_gen.py:113 IND CLOCK 24276
2026-03-06 03:40:39.641 [DEBUG] clck_gen.py:113 IND CLOCK 24378
2026-03-06 03:40:40.114 [DEBUG] clck_gen.py:113 IND CLOCK 24480
2026-03-06 03:40:40.585 [DEBUG] clck_gen.py:113 IND CLOCK 24582
2026-03-06 03:40:41.052 [DEBUG] clck_gen.py:113 IND CLOCK 24684
2026-03-06 03:40:41.520 [DEBUG] clck_gen.py:113 IND CLOCK 24786
2026-03-06 03:40:41.991 [DEBUG] clck_gen.py:113 IND CLOCK 24888
2026-03-06 03:40:42.463 [DEBUG] clck_gen.py:113 IND CLOCK 24990
2026-03-06 03:40:42.935 [DEBUG] clck_gen.py:113 IND CLOCK 25092
2026-03-06 03:40:43.402 [DEBUG] clck_gen.py:113 IND CLOCK 25194
2026-03-06 03:40:43.875 [DEBUG] clck_gen.py:113 IND CLOCK 25296
2026-03-06 03:40:44.346 [DEBUG] clck_gen.py:113 IND CLOCK 25398
2026-03-06 03:40:44.813 [DEBUG] clck_gen.py:113 IND CLOCK 25500
2026-03-06 03:40:45.285 [DEBUG] clck_gen.py:113 IND CLOCK 25602
2026-03-06 03:40:45.602 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:40:45.602 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:40:45.602 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:40:45.606 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:40:45.606 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:40:45.606 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:40:45.606 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:40:45.607 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:40:45.607 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:40:45.607 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:40:45.607 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:40:45.607 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:40:45.607 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:40:45.607 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:40:50.613 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:40:50.613 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:40:50.613 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:40:50.613 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:40:50.613 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:40:50.613 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:40:50.618 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:40:50.619 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:40:50.619 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:40:50.620 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:40:50.620 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:40:50.622 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:40:50.622 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:40:50.622 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:40:50.622 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:40:50.623 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:40:50.623 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:40:50.624 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:40:50.624 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:40:50.624 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:40:50.624 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:40:50.625 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:40:50.625 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:40:50.625 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:40:50.625 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:40:50.625 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:40:50.625 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:40:50.625 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:40:50.626 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:40:50.626 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:40:50.627 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:40:50.627 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:40:50.627 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:40:50.627 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:40:50.627 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:40:50.627 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:40:50.627 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:40:50.627 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:40:50.630 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:40:50.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:40:50.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:40:50.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:40:50.630 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:40:50.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:40:50.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:40:50.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:40:50.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:40:50.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:40:50.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:40:50.630 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:40:50.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:40:50.630 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:40:50.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:40:50.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:40:50.631 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:40:50.631 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:40:50.631 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:40:50.631 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:40:50.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:40:50.631 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:40:50.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:40:50.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:40:50.631 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:40:50.632 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:40:50.632 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:40:50.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:40:50.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:40:50.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:40:55.638 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:40:55.638 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:40:55.638 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:40:55.638 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:40:55.638 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:40:55.638 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:40:55.647 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:40:55.649 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:40:55.649 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:40:55.649 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:40:55.649 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:40:55.654 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:40:55.654 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:40:55.655 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:40:55.655 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:40:55.655 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:40:55.656 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:40:55.656 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:40:55.656 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:40:55.657 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:40:55.658 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:40:55.658 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:40:55.659 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:40:55.659 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:40:55.660 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:40:55.660 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:40:55.660 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:40:55.660 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:40:55.661 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:40:55.661 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:40:55.662 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:40:55.662 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:40:55.662 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:40:55.662 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:40:55.662 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:40:55.663 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:40:55.663 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:40:55.663 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:40:55.665 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:40:55.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:40:55.665 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:40:55.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:40:55.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:40:55.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:40:55.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:40:55.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:40:55.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:40:55.666 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:40:55.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:40:55.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:40:55.666 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:40:55.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:40:55.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:40:55.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:40:55.666 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:40:55.666 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:40:55.666 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:40:55.666 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:40:55.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:40:55.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:40:55.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:40:55.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:40:55.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:40:55.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:40:55.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:40:55.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:40:55.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:40:55.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:40:55.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:40:55.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:40:55.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:40:55.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:40:55.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:40:55.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:40:55.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:40:55.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:40:55.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:40:55.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:40:55.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:40:55.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:40:55.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:40:55.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:40:55.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:40:55.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:40:55.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:40:55.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:40:55.671 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:40:56.152 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:40:56.193 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:40:56.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:40:56.195 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:40:56.196 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:40:56.212 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:40:56.213 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:40:56.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:40:56.229 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:40:56.229 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:40:56.230 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:40:56.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:40:56.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:40:56.239 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:40:56.240 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:40:56.240 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:40:56.240 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:40:56.244 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:40:56.244 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:40:56.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:40:56.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:40:56.625 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:40:56.668 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:40:56.669 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:40:56.669 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:40:56.669 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:40:57.101 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:40:57.580 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:40:57.669 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:40:57.670 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:40:57.670 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:40:57.670 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:40:57.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:40:57.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:40:57.688 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:40:57.688 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:40:57.703 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:40:57.703 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:40:57.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:40:57.709 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:40:57.709 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:40:57.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:40:57.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:40:57.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:40:57.711 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:40:57.711 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:40:57.711 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:40:57.711 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:40:57.715 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:40:57.715 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:40:57.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:40:57.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:40:58.053 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:40:58.533 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:40:58.671 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:40:58.671 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:40:58.671 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:40:58.672 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:40:59.015 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:40:59.495 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:40:59.672 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:40:59.673 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:40:59.673 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:40:59.673 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:40:59.976 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:41:00.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:41:00.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:41:00.012 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:41:00.012 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:41:00.012 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:41:00.030 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:41:00.030 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:41:00.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:41:00.036 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:41:00.036 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:41:00.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:41:00.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:41:00.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:41:00.038 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:41:00.038 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:41:00.038 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:41:00.038 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:41:00.068 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:41:00.068 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:41:00.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:41:00.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:41:00.445 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:41:00.673 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:41:00.674 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:41:00.674 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:41:00.675 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:41:00.915 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:41:01.385 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:41:01.855 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:41:02.326 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:41:02.796 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:41:03.267 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:41:03.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:41:03.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:41:03.426 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:41:03.426 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:41:03.442 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:41:03.442 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:41:03.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:41:03.448 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:41:03.448 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:41:03.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:41:03.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:41:03.450 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:41:03.450 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:41:03.450 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:41:03.450 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:41:03.450 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:41:03.499 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:41:03.500 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:41:03.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:41:03.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:41:03.735 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:41:04.208 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:41:04.685 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:41:04.768 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:41:04.768 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:41:04.768 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:41:04.773 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:41:04.773 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:41:04.773 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:41:04.774 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:41:04.775 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:41:04.776 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:41:04.776 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:41:04.776 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:41:04.776 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:41:04.776 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:41:04.776 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:41:04.776 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1959 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:41:04.776 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1959 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:41:04.776 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1959 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:41:09.783 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:41:09.783 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:41:09.784 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:41:09.784 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:41:09.784 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:41:09.784 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:41:09.790 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:41:09.791 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:41:09.791 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:41:09.791 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:41:09.791 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:41:09.793 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:41:09.793 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:41:09.793 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:41:09.793 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:41:09.793 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:41:09.793 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:41:09.793 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:41:09.793 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:41:09.794 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:41:09.795 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:41:09.795 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:41:09.795 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:41:09.795 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:41:09.795 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:41:09.795 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:41:09.795 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:41:09.795 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:41:09.795 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:41:09.796 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:41:09.796 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:41:09.796 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:41:09.796 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:41:09.797 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:41:09.797 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:41:09.797 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:41:09.797 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:41:09.797 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:41:09.798 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:41:09.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:41:09.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:41:09.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:41:09.798 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:41:09.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:41:09.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:41:09.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:41:09.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:41:09.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:41:09.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:41:09.799 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:41:09.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:41:09.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:41:09.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:41:09.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:41:09.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:41:09.799 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:41:09.799 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:41:09.799 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:41:09.799 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:41:09.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:41:09.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:41:09.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:41:09.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:41:09.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:41:09.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:41:09.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:41:09.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:41:09.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:41:09.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:41:09.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:41:09.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:41:09.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:41:09.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:41:09.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:41:09.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:41:09.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:41:09.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:41:09.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:41:09.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:41:09.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:41:09.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:41:09.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:41:09.801 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:41:09.801 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:41:09.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:41:09.802 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:41:09.804 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:41:10.276 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:41:10.316 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:41:10.317 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:41:10.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:41:10.318 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:41:10.329 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:41:10.330 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:41:10.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:41:10.345 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:41:10.346 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:41:10.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:41:10.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:41:10.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:41:10.352 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:41:10.352 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:41:10.353 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:41:10.353 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:41:10.372 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:41:10.372 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:41:10.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:41:10.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:41:10.750 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:41:10.800 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:41:10.801 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:41:10.801 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:41:10.801 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:41:11.227 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:41:11.706 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:41:11.802 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:41:11.802 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:41:11.803 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:41:11.803 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:41:12.179 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:41:12.655 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:41:12.803 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:41:12.804 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:41:12.804 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:41:12.804 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:41:13.129 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:41:13.603 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:41:13.804 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:41:13.805 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:41:13.805 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:41:13.805 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:41:14.077 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:41:14.550 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:41:14.805 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:41:14.806 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:41:14.806 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:41:14.806 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:41:15.028 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:41:15.502 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:41:15.978 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:41:16.457 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:41:16.936 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:41:17.414 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:41:17.891 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:41:18.364 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:41:18.836 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:41:19.311 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:41:19.789 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:41:20.267 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:41:20.741 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:41:21.211 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:41:21.683 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:41:22.158 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:41:22.627 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:41:23.097 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:41:23.568 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:41:24.038 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:41:24.508 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:41:24.980 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:41:25.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:41:25.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:41:25.268 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:41:25.268 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:41:25.283 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:41:25.283 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:41:25.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:41:25.289 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:41:25.289 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:41:25.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:41:25.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:41:25.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:41:25.291 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:41:25.291 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:41:25.291 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:41:25.291 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:41:25.302 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:41:25.303 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:41:25.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:41:25.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:41:25.452 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:41:25.931 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:41:26.409 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:41:26.883 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:41:27.350 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:41:27.825 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:41:28.298 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:41:28.769 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 03:41:29.240 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 03:41:29.719 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 03:41:30.198 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 03:41:30.677 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 03:41:31.157 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 03:41:31.637 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 03:41:32.117 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 03:41:32.594 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 03:41:33.067 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 03:41:33.547 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 03:41:34.026 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 03:41:34.498 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 03:41:34.973 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 03:41:35.448 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 03:41:35.921 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 03:41:36.393 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 03:41:36.865 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 03:41:37.338 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 03:41:37.810 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 03:41:38.281 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 03:41:38.756 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 03:41:39.230 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 03:41:39.705 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 03:41:40.178 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 03:41:40.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:41:40.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:41:40.520 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:41:40.520 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:41:40.521 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:41:40.536 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:41:40.536 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:41:40.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:41:40.541 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:41:40.541 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:41:40.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:41:40.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:41:40.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:41:40.543 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:41:40.543 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:41:40.543 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:41:40.543 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:41:40.545 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:41:40.546 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:41:40.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:41:40.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:41:40.654 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 03:41:41.132 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 03:41:41.607 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 03:41:42.081 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 03:41:42.554 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 03:41:43.030 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 03:41:43.506 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 03:41:43.985 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 03:41:44.464 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 03:41:44.943 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-06 03:41:45.422 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-06 03:41:45.902 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-06 03:41:46.378 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-06 03:41:46.856 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-06 03:41:47.335 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-06 03:41:47.808 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-06 03:41:48.280 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-06 03:41:48.747 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-06 03:41:49.221 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-06 03:41:49.693 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-06 03:41:50.167 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-06 03:41:50.634 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-06 03:41:51.105 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-06 03:41:51.577 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-06 03:41:52.046 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-06 03:41:52.517 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-06 03:41:52.991 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-06 03:41:53.464 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-06 03:41:53.936 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-06 03:41:54.407 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-06 03:41:54.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:41:54.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:41:54.847 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:41:54.847 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:41:54.864 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:41:54.864 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:41:54.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:41:54.869 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:41:54.869 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:41:54.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:41:54.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:41:54.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:41:54.871 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:41:54.871 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:41:54.871 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:41:54.871 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:41:54.873 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:41:54.873 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:41:54.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:41:54.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:41:54.878 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-06 03:41:55.352 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-06 03:41:55.827 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-06 03:41:56.301 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-06 03:41:56.775 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-06 03:41:57.249 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-06 03:41:57.727 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-06 03:41:58.123 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:41:58.124 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:41:58.124 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:41:58.124 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:41:58.124 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:41:58.124 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:41:58.124 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:41:58.125 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:41:58.125 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:41:58.125 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:41:58.125 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:41:58.125 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:41:58.125 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:41:58.125 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:41:58.125 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=10390 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:41:58.125 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=10390 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:41:58.125 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=10390 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:42:03.135 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:42:03.135 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:42:03.135 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:42:03.136 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:42:03.136 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:42:03.136 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:42:03.143 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:42:03.144 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:42:03.144 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:42:03.145 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:42:03.145 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:42:03.147 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:42:03.148 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:42:03.148 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:42:03.148 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:42:03.149 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:42:03.149 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:42:03.150 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:42:03.150 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:42:03.150 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:42:03.151 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:42:03.152 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:42:03.152 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:42:03.152 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:42:03.153 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:42:03.153 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:42:03.154 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:42:03.154 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:42:03.154 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:42:03.155 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:42:03.155 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:42:03.155 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:42:03.155 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:42:03.156 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:42:03.156 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:42:03.156 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:42:03.156 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:42:03.156 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:42:03.159 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:42:03.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:42:03.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:42:03.159 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:42:03.159 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:42:03.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:42:03.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:42:03.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:42:03.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:42:03.159 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:42:03.159 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:42:03.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:42:03.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:42:03.160 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:42:03.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:42:03.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:42:03.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:42:03.160 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:42:03.160 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:42:03.160 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:42:03.160 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:42:03.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:42:03.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:42:03.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:42:03.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:42:03.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:42:03.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:42:03.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:42:03.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:42:03.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:42:03.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:42:03.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:42:03.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:42:03.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:42:03.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:42:03.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:42:03.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:42:03.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:42:03.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:42:03.162 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:42:03.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:42:03.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:42:03.162 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:42:03.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:42:03.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:42:03.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:42:03.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:42:03.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:42:03.165 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:42:03.637 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:42:03.686 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:42:03.688 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:42:03.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:42:03.689 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:42:03.705 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:42:03.706 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:42:03.706 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:42:03.717 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:42:03.717 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:42:03.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:42:03.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:42:03.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:03.720 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:42:03.721 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:42:03.721 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:42:03.721 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:42:03.726 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:42:03.726 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:42:03.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:03.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:04.107 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:42:04.162 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:42:04.163 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:42:04.163 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:42:04.163 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:42:04.581 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:42:05.056 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:42:05.163 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:42:05.164 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:42:05.164 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:42:05.165 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:42:05.535 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:42:06.009 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:42:06.164 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:42:06.165 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:42:06.165 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:42:06.166 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:42:06.481 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:42:06.955 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:42:07.166 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:42:07.166 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:42:07.167 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:42:07.167 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:42:07.427 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:42:07.899 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:42:08.167 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:42:08.168 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:42:08.168 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:42:08.169 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:42:08.370 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:42:08.844 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:42:09.320 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:42:09.798 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:42:10.271 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:42:10.746 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:42:11.220 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:42:11.692 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:42:12.166 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:42:12.639 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:42:13.115 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:42:13.589 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:42:13.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:13.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:42:13.784 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:42:13.784 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:42:13.798 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:42:13.798 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:42:13.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:42:13.804 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:42:13.804 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:42:13.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:42:13.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:42:13.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:13.806 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:42:13.806 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:42:13.806 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:42:13.806 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:42:13.818 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:42:13.818 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:42:13.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:13.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:14.059 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:42:14.534 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:42:15.010 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:42:15.485 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:42:15.959 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:42:16.436 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:42:16.913 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:42:17.391 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:42:17.866 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:42:18.339 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:42:18.812 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:42:19.290 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:42:19.765 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:42:20.239 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:42:20.712 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:42:21.185 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:42:21.659 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:42:22.136 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 03:42:22.610 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 03:42:23.085 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 03:42:23.558 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 03:42:24.034 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 03:42:24.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:24.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:42:24.199 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:42:24.200 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:42:24.200 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:42:24.215 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:42:24.215 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:42:24.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:42:24.221 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:42:24.221 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:42:24.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:42:24.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:42:24.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:24.222 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:42:24.222 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:42:24.223 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:42:24.223 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:42:24.270 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:42:24.270 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:42:24.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:24.272 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:24.507 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 03:42:24.980 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 03:42:25.454 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 03:42:25.941 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-06 03:42:26.416 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-06 03:42:26.896 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-06 03:42:27.374 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-06 03:42:27.851 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-06 03:42:28.329 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-06 03:42:28.808 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-06 03:42:29.286 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-06 03:42:29.760 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-06 03:42:30.239 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-06 03:42:30.718 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-06 03:42:31.195 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-06 03:42:31.233 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:31.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:42:31.236 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:42:31.236 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:42:31.253 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:42:31.253 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:42:31.253 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:42:31.259 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:42:31.259 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:42:31.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:42:31.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:42:31.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:31.260 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:42:31.261 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:42:31.261 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:42:31.261 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:42:31.287 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:42:31.287 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:42:31.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:31.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:31.668 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-06 03:42:32.139 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-06 03:42:32.611 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-06 03:42:33.086 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-06 03:42:33.559 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-06 03:42:34.030 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-06 03:42:34.505 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-06 03:42:34.978 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-06 03:42:35.450 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-06 03:42:35.934 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-06 03:42:36.409 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-06 03:42:36.886 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-06 03:42:37.360 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-06 03:42:37.834 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-06 03:42:38.308 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-06 03:42:38.780 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-06 03:42:39.254 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-06 03:42:39.727 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-06 03:42:40.200 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-06 03:42:40.675 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-06 03:42:41.149 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-06 03:42:41.624 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-06 03:42:42.096 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-06 03:42:42.569 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-06 03:42:43.042 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-06 03:42:43.516 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-06 03:42:43.993 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-06 03:42:44.472 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-06 03:42:44.950 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-06 03:42:45.424 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-06 03:42:45.899 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-06 03:42:46.375 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-06 03:42:46.854 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-06 03:42:47.327 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-06 03:42:47.798 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-06 03:42:48.273 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-06 03:42:48.752 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-06 03:42:49.230 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-06 03:42:49.702 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-06 03:42:50.180 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-06 03:42:50.659 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-06 03:42:51.138 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-06 03:42:51.254 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:42:51.254 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:42:51.254 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:42:51.255 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:42:51.255 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:42:51.255 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:42:51.255 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:42:51.256 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:42:51.256 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:42:51.256 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:42:51.256 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:42:51.256 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:42:51.256 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:42:51.256 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:42:56.263 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:42:56.263 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:42:56.263 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:42:56.263 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:42:56.263 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:42:56.263 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:42:56.269 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:42:56.270 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:42:56.270 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:42:56.271 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:42:56.271 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:42:56.273 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:42:56.273 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:42:56.273 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:42:56.273 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:42:56.274 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:42:56.274 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:42:56.274 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:42:56.274 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:42:56.274 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:42:56.275 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:42:56.275 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:42:56.275 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:42:56.275 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:42:56.276 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:42:56.276 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:42:56.276 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:42:56.276 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:42:56.276 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:42:56.277 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:42:56.277 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:42:56.277 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:42:56.277 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:42:56.278 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:42:56.278 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:42:56.278 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:42:56.278 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:42:56.278 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:42:56.280 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:42:56.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:42:56.280 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:42:56.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:42:56.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:42:56.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:42:56.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:42:56.280 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:42:56.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:42:56.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:42:56.280 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:42:56.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:42:56.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:42:56.280 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:42:56.280 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:42:56.280 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:42:56.281 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:42:56.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:42:56.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:42:56.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:42:56.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:42:56.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:42:56.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:42:56.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:42:56.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:42:56.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:42:56.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:42:56.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:42:56.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:42:56.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:42:56.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:42:56.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:42:56.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:42:56.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:42:56.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:42:56.282 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:42:56.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:42:56.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:42:56.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:42:56.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:42:56.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:42:56.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:42:56.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:42:56.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:42:56.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:42:56.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:42:56.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:42:56.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:42:56.285 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:42:56.759 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:42:56.813 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:42:56.815 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:42:56.817 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:42:56.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:42:56.834 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:42:56.834 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:42:56.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:42:56.847 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:42:56.847 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:42:56.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:42:56.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:42:56.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:56.851 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:42:56.851 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:42:56.851 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:42:56.851 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:42:56.897 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:42:56.897 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:42:56.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:56.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:57.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:57.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:42:57.218 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:42:57.218 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:42:57.232 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:42:57.232 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:42:57.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:42:57.234 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:42:57.238 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:42:57.238 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:42:57.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:42:57.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:42:57.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:57.240 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:42:57.240 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:42:57.240 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:42:57.240 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:42:57.276 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:42:57.276 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:42:57.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:57.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:57.282 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:42:57.282 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:42:57.283 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:42:57.283 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:42:57.709 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:42:57.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:57.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:42:57.769 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:42:57.769 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:42:57.770 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:42:57.789 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:42:57.789 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:42:57.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:42:57.795 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:42:57.795 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:42:57.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:42:57.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:42:57.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:57.796 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:42:57.796 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:42:57.796 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:42:57.796 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:42:57.798 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:42:57.798 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:42:57.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:57.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:58.183 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:42:58.283 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:42:58.283 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:42:58.284 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:42:58.284 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:42:58.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:58.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:42:58.575 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:42:58.575 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:42:58.588 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:42:58.588 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:42:58.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:42:58.594 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:42:58.594 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:42:58.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:42:58.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:42:58.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:58.596 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:42:58.596 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:42:58.596 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:42:58.596 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:42:58.650 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:42:58.651 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:42:58.651 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:58.651 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:42:58.661 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:42:59.138 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:42:59.284 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:42:59.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:42:59.285 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:42:59.285 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:42:59.615 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:43:00.093 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:43:00.285 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:43:00.285 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:43:00.286 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:43:00.286 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:43:00.569 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:43:01.047 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:43:01.287 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:43:01.287 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:43:01.287 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:43:01.287 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:43:01.523 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:43:02.001 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:43:02.479 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:43:02.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:02.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:43:02.703 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:02.703 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:02.704 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:43:02.716 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:43:02.716 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:43:02.717 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:43:02.717 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:43:02.720 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:43:02.721 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:43:02.721 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:43:02.721 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:43:02.722 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:43:02.722 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:43:02.722 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:43:02.723 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1380 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:43:02.723 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1380 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:43:02.723 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1380 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:43:02.723 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1380 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:43:02.724 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1380 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:43:02.724 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=1380 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:43:07.723 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:43:07.723 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:43:07.723 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:43:07.723 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:43:07.723 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:43:07.723 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:43:07.733 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:43:07.734 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:43:07.734 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:43:07.735 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:43:07.735 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:43:07.737 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:43:07.737 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:43:07.737 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:43:07.738 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:43:07.738 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:43:07.738 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:43:07.738 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:43:07.738 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:43:07.738 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:43:07.740 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:43:07.741 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:43:07.741 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:43:07.741 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:43:07.741 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:43:07.741 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:43:07.742 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:43:07.742 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:43:07.742 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:43:07.744 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:43:07.744 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:43:07.744 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:43:07.744 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:43:07.744 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:43:07.744 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:43:07.745 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:43:07.745 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:43:07.745 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:43:07.748 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:43:07.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:43:07.748 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:43:07.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:43:07.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:43:07.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:43:07.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:43:07.749 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:43:07.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:43:07.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:43:07.749 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:43:07.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:43:07.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:43:07.749 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:43:07.749 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:43:07.749 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:43:07.750 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:43:07.750 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:43:07.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:43:07.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:43:07.750 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:43:07.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:43:07.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:43:07.750 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:43:07.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:43:07.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:43:07.750 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:43:07.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:43:07.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:43:07.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:43:07.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:43:07.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:43:07.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:43:07.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:43:07.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:43:07.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:43:07.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:43:07.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:43:07.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:43:07.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:43:07.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:43:07.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:43:07.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:43:07.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:43:07.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:43:07.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:43:07.755 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:43:07.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:43:07.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:43:08.221 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:43:08.282 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:43:08.284 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:43:08.285 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:43:08.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:43:08.304 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:08.304 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:08.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:43:08.316 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:08.316 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:08.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:43:08.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:43:08.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:08.324 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:43:08.324 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:43:08.324 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:43:08.324 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:43:08.359 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:43:08.359 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:43:08.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:08.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:08.689 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:43:08.752 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:43:08.752 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:43:08.753 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:43:08.753 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:43:09.159 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:43:09.630 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:43:09.753 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:43:09.754 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:43:09.754 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:43:09.754 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:43:10.103 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:43:10.577 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:43:10.754 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:43:10.755 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:43:10.755 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:43:10.755 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:43:11.048 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:43:11.526 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:43:11.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:11.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:43:11.588 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:11.589 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:11.603 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:11.603 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:11.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:43:11.608 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:11.609 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:11.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:43:11.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:43:11.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:11.610 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:43:11.610 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:43:11.610 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:43:11.610 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:43:11.615 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:43:11.615 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:43:11.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:11.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:11.755 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:43:11.755 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:43:11.756 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:43:11.756 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:43:11.998 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:43:12.467 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:43:12.756 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:43:12.756 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:43:12.756 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:43:12.757 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:43:12.935 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:43:13.406 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:43:13.877 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:43:14.348 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:43:14.818 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:43:14.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:14.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:43:14.946 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:14.946 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:14.946 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:43:14.963 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:14.963 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:14.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:43:14.969 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:14.969 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:14.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:43:14.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:43:14.971 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:14.971 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:43:14.971 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:43:14.971 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:43:14.971 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:43:15.001 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:43:15.002 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:43:15.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:15.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:15.289 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:43:15.760 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:43:16.231 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:43:16.700 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:43:17.174 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:43:17.647 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:43:18.119 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:43:18.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:18.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:43:18.510 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:18.510 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:18.525 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:18.526 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:18.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:43:18.531 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:18.531 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:18.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:43:18.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:43:18.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:18.533 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:43:18.533 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:43:18.533 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:43:18.533 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:43:18.586 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:43:18.586 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:43:18.586 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:43:18.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:18.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:19.053 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:43:19.524 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:43:19.991 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:43:20.461 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:43:20.932 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:43:21.403 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:43:21.873 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:43:22.350 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:43:22.828 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:43:22.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:22.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:43:22.914 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:22.914 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:22.914 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:43:22.927 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:43:22.928 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:43:22.928 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:43:22.928 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:43:22.931 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:43:22.931 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:43:22.931 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:43:22.931 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:43:22.931 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:43:22.931 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:43:22.931 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:43:22.931 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3288 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:43:22.931 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3288 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:43:22.931 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3288 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:43:22.932 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3288 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:43:22.932 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3288 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:43:22.932 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3288 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:43:27.934 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:43:27.934 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:43:27.934 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:43:27.934 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:43:27.935 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:43:27.935 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:43:27.944 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:43:27.945 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:43:27.945 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:43:27.946 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:43:27.946 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:43:27.948 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:43:27.948 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:43:27.949 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:43:27.949 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:43:27.950 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:43:27.950 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:43:27.951 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:43:27.951 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:43:27.951 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:43:27.951 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:43:27.951 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:43:27.951 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:43:27.952 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:43:27.952 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:43:27.952 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:43:27.952 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:43:27.952 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:43:27.952 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:43:27.954 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:43:27.954 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:43:27.954 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:43:27.954 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:43:27.954 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:43:27.954 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:43:27.954 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:43:27.954 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:43:27.955 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:43:27.957 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:43:27.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:43:27.957 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:43:27.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:43:27.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:43:27.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:43:27.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:43:27.957 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:43:27.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:43:27.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:43:27.957 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:43:27.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:43:27.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:43:27.957 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:43:27.957 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:43:27.957 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:43:27.958 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:43:27.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:43:27.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:43:27.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:43:27.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:43:27.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:43:27.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:43:27.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:43:27.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:43:27.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:43:27.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:43:27.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:43:27.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:43:27.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:43:27.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:43:27.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:43:27.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:43:27.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:43:27.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:43:27.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:43:27.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:43:27.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:43:27.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:43:27.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:43:27.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:43:27.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:43:27.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:43:27.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:43:27.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:43:27.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:43:27.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:43:27.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:43:27.962 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:43:28.442 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:43:28.480 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:43:28.481 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:43:28.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:43:28.483 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:43:28.503 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:28.503 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:28.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:43:28.525 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:28.525 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:28.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:43:28.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:43:28.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:28.534 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:43:28.535 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:43:28.535 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:43:28.535 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:43:28.581 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:43:28.581 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:43:28.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:28.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:28.917 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:43:28.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:28.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:43:28.956 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:28.957 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:28.959 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:43:28.959 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:43:28.960 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:43:28.960 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:43:28.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:28.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:28.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:43:28.969 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:28.969 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:28.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:43:28.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:43:28.971 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:28.971 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:43:28.971 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:43:28.971 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:43:28.971 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:43:29.002 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:43:29.002 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:43:29.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:29.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:29.387 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:43:29.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:29.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:43:29.564 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:29.564 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:29.564 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:43:29.584 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:29.584 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:29.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:43:29.590 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:29.590 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:29.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:43:29.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:43:29.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:29.592 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:43:29.592 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:43:29.592 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:43:29.592 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:43:29.619 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:43:29.619 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:43:29.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:29.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:29.866 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:43:29.960 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:43:29.960 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:43:29.961 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:43:29.961 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:43:30.345 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:43:30.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:30.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:43:30.740 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:30.740 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:30.755 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:30.755 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:30.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:43:30.761 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:30.761 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:30.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:43:30.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:43:30.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:30.763 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:43:30.763 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:43:30.763 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:43:30.763 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:43:30.815 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:43:30.815 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:43:30.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:30.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:30.818 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:43:30.961 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:43:30.961 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:43:30.962 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:43:30.962 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:43:31.294 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:43:31.772 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:43:31.963 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:43:31.963 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:43:31.963 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:43:31.964 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:43:32.250 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:43:32.728 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:43:32.964 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:43:32.964 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:43:32.964 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:43:32.965 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:43:33.207 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:43:33.685 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:43:34.161 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:43:34.639 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:43:35.117 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:43:35.595 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:43:36.071 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:43:36.549 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:43:37.027 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:43:37.505 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:43:37.984 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:43:38.460 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:43:38.938 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:43:39.416 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:43:39.894 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:43:40.372 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:43:40.850 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:43:41.329 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:43:41.808 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:43:42.287 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:43:42.765 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:43:43.242 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:43:43.718 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:43:44.197 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-06 03:43:44.675 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-06 03:43:45.151 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-06 03:43:45.626 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-06 03:43:46.104 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-06 03:43:46.581 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-06 03:43:47.060 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-06 03:43:47.534 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-06 03:43:48.007 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-06 03:43:48.484 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-06 03:43:48.963 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-06 03:43:49.441 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-06 03:43:49.920 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-06 03:43:50.399 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-06 03:43:50.756 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:50.756 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:50.756 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:43:50.757 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:43:50.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:43:50.757 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:43:50.757 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:43:50.758 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:43:50.758 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:43:50.758 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:43:50.758 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:43:50.758 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:43:50.758 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:43:50.758 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:43:55.767 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:43:55.767 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:43:55.767 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:43:55.767 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:43:55.768 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:43:55.768 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:43:55.774 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:43:55.774 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:43:55.774 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:43:55.775 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:43:55.775 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:43:55.776 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:43:55.776 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:43:55.776 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:43:55.776 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:43:55.777 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:43:55.777 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:43:55.777 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:43:55.777 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:43:55.777 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:43:55.778 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:43:55.778 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:43:55.778 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:43:55.778 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:43:55.778 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:43:55.779 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:43:55.779 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:43:55.779 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:43:55.779 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:43:55.780 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:43:55.780 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:43:55.780 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:43:55.780 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:43:55.780 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:43:55.780 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:43:55.780 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:43:55.780 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:43:55.780 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:43:55.781 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:43:55.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:43:55.782 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:43:55.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:43:55.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:43:55.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:43:55.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:43:55.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:43:55.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:43:55.782 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:43:55.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:43:55.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:43:55.782 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:43:55.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:43:55.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:43:55.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:43:55.782 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:43:55.782 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:43:55.782 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:43:55.782 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:43:55.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:43:55.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:43:55.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:43:55.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:43:55.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:43:55.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:43:55.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:43:55.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:43:55.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:43:55.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:43:55.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:43:55.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:43:55.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:43:55.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:43:55.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:43:55.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:43:55.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:43:55.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:43:55.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:43:55.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:43:55.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:43:55.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:43:55.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:43:55.784 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:43:55.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:43:55.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:43:55.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:43:55.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:43:55.787 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:43:56.262 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:43:56.295 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:43:56.296 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:43:56.297 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:43:56.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:43:56.311 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:56.311 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:56.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:43:56.332 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:56.332 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:56.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:43:56.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:43:56.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:56.337 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:43:56.337 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:43:56.337 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:43:56.337 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:43:56.353 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:43:56.354 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:43:56.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:56.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:56.740 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:43:56.784 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:43:56.785 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:43:56.785 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:43:56.785 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:43:57.220 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:43:57.698 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:43:57.785 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:43:57.786 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:43:57.786 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:43:57.786 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:43:58.176 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:43:58.654 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:43:58.786 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:43:58.787 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:43:58.787 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:43:58.787 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:43:59.133 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:43:59.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:59.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:43:59.227 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:59.227 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:59.245 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:59.245 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:59.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:43:59.252 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:43:59.252 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:43:59.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:43:59.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:43:59.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:59.254 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:43:59.254 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:43:59.254 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:43:59.254 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:43:59.270 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:43:59.270 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:43:59.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:59.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:43:59.608 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:43:59.788 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:43:59.788 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:43:59.788 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:43:59.789 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:44:00.086 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:44:00.563 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:44:00.789 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:44:00.790 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:44:00.790 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:44:00.790 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:44:01.041 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:44:01.519 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:44:01.997 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:44:02.476 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:44:02.954 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:44:03.432 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:44:03.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:44:03.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:03.893 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:44:03.894 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:44:03.894 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:44:03.909 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:44:03.909 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:44:03.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:44:03.909 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:44:03.916 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:44:03.916 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:44:03.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:44:03.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:03.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:44:03.918 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:44:03.918 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:44:03.918 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:44:03.918 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:44:03.955 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:44:03.956 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:44:03.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:44:03.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:44:04.388 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:44:04.867 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:44:05.345 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:44:05.823 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:44:06.302 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:44:06.781 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:44:07.260 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:44:07.740 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:44:08.217 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:44:08.695 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:44:09.173 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:44:09.652 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:44:10.131 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:44:10.608 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:44:10.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:44:10.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:10.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:44:10.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:44:10.784 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:44:10.784 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:44:10.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:44:10.790 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:44:10.790 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:44:10.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:44:10.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:10.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:44:10.792 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:44:10.792 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:44:10.792 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:44:10.792 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:44:10.843 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:44:10.843 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:44:10.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:44:10.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:44:11.082 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:44:11.559 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:44:11.644 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:44:11.644 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:44:11.645 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:44:11.648 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:44:11.648 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:44:11.648 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:44:11.648 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:44:11.649 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:44:11.649 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:44:11.649 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:44:11.649 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:44:11.649 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:44:11.649 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:44:11.649 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:44:16.656 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:44:16.656 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:44:16.656 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:44:16.656 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:44:16.656 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:44:16.656 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:44:16.663 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:44:16.664 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:44:16.665 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:44:16.665 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:44:16.665 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:44:16.669 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:44:16.669 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:44:16.669 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:44:16.670 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:44:16.670 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:44:16.670 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:44:16.671 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:44:16.671 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:44:16.671 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:44:16.673 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:44:16.673 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:44:16.673 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:44:16.674 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:44:16.674 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:44:16.674 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:44:16.674 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:44:16.674 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:44:16.675 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:44:16.676 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:44:16.676 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:44:16.676 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:44:16.677 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:44:16.677 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:44:16.677 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:44:16.677 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:44:16.677 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:44:16.677 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:44:16.680 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:44:16.680 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:44:16.680 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:44:16.680 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:44:16.681 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:44:16.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:44:16.681 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:44:16.681 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:44:16.681 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:44:16.681 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:44:16.681 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:44:16.681 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:16.681 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:16.681 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:44:16.681 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:44:16.681 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:44:16.681 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:44:16.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:16.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:16.682 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:16.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:44:16.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:16.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:16.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:16.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:16.682 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:16.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:16.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:16.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:16.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:16.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:16.682 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:16.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:16.683 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:16.683 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:16.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:16.683 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:16.683 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:16.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:16.683 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:16.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:16.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:16.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:16.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:16.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:16.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:16.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:16.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:16.686 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:44:17.158 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:44:17.212 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:44:17.214 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:44:17.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:17.218 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:44:17.244 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:44:17.244 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:44:17.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:44:17.261 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:44:17.261 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:44:17.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:44:17.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:17.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:44:17.264 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:44:17.265 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:44:17.265 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:44:17.265 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:44:17.298 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:44:17.299 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:44:17.299 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:44:17.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:44:17.625 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:44:17.683 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:44:17.684 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:44:17.684 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:44:17.685 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:44:18.095 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:44:18.569 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:44:18.684 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:44:18.685 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:44:18.685 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:44:18.686 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:44:19.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:44:19.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:19.036 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:44:19.037 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:44:19.037 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:44:19.051 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:44:19.051 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:44:19.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:44:19.058 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:44:19.058 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:44:19.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:44:19.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:19.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:44:19.060 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:44:19.060 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:44:19.060 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:44:19.060 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:44:19.079 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:44:19.079 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-06 03:44:19.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:44:19.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:44:19.507 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:44:19.685 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:44:19.685 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:44:19.686 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:44:19.687 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:44:19.975 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:44:20.440 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:44:20.686 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:44:20.687 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:44:20.687 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:44:20.688 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:44:20.905 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:44:21.370 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:44:21.688 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:44:21.688 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:44:21.688 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:44:21.689 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:44:21.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:44:21.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:21.774 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:44:21.774 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:44:21.775 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:44:21.793 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:44:21.793 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:44:21.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:44:21.800 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:44:21.800 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:44:21.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:44:21.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:21.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:44:21.802 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:44:21.802 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:44:21.802 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:44:21.802 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:44:21.840 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:44:21.842 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:44:21.843 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:44:21.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:44:21.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:44:22.308 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:44:22.774 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:44:23.241 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:44:23.707 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:44:24.174 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:44:24.642 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:44:25.107 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:44:25.574 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:44:26.045 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:44:26.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:44:26.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:26.200 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:44:26.200 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:44:26.212 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:44:26.212 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:44:26.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:44:26.219 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:44:26.220 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:44:26.220 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:44:26.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:26.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:44:26.221 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:44:26.221 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:44:26.222 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:44:26.222 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:44:26.276 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.59.22:6700) Recv SETFH cmd
2026-03-06 03:44:26.276 [INFO] transceiver.py:201 (MS@172.18.59.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-06 03:44:26.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:44:26.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:44:26.514 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:44:26.986 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:44:27.457 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:44:27.932 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:44:28.407 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:44:28.483 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:44:28.483 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:44:28.483 [INFO] transceiver.py:205 (MS@172.18.59.22:6700) Frequency hopping disabled
2026-03-06 03:44:28.484 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:44:28.484 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:44:28.484 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:44:28.484 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:44:28.485 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:44:28.485 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:44:28.485 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:44:28.485 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:44:28.485 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:44:28.485 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:44:28.485 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:44:33.496 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:44:33.496 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:44:33.496 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:44:33.497 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:44:33.497 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:44:33.497 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:44:33.512 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:44:33.513 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:44:33.513 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:44:33.514 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:44:33.514 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:44:33.515 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:44:33.516 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:44:33.516 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:44:33.516 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:44:33.517 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:44:33.517 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:44:33.517 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:44:33.517 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:44:33.518 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:44:33.518 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:44:33.518 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:44:33.518 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:44:33.518 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:44:33.519 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:44:33.519 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:44:33.519 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:44:33.519 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:44:33.519 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:44:33.520 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:44:33.520 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:44:33.520 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:44:33.520 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:44:33.520 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:44:33.520 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:44:33.520 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:44:33.520 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:44:33.520 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:44:33.522 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:44:33.522 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:44:33.522 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:44:33.522 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:44:33.522 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:44:33.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:44:33.522 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:44:33.522 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:44:33.522 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:44:33.522 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:44:33.522 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:33.522 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:33.523 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:44:33.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:33.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:33.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:33.523 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:44:33.523 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:44:33.523 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:44:33.523 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:44:33.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:33.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:33.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:33.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:44:33.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:33.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:33.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:33.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:33.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:33.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:33.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:33.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:33.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:33.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:33.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:33.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:33.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:33.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:33.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:33.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:33.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:33.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:33.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:33.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:33.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:33.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:33.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:33.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:33.528 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:44:33.996 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:44:34.042 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:44:34.044 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:44:34.046 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:44:34.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:34.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:34.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:34.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:34.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:34.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:34.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:34.470 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:44:34.525 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:44:34.525 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:44:34.526 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:44:34.526 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:44:34.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:34.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:34.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:34.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:34.943 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:44:35.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:35.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:35.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:35.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:35.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:35.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:35.376 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:44:35.376 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:44:35.376 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:44:35.377 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:44:35.380 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:44:35.381 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:44:35.381 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:44:35.381 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:44:35.381 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:44:35.381 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:44:35.382 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:44:35.382 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=403 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:35.382 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=403 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:35.383 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=403 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:35.383 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=403 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:35.383 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=403 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:35.383 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=403 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:35.383 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=404 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:35.383 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=404 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:35.384 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=404 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:35.384 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=404 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:35.384 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=404 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:35.384 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=404 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:35.384 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=404 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:35.384 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=404 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:40.384 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:44:40.384 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:44:40.384 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:44:40.384 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:44:40.384 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:44:40.384 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:44:40.392 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:44:40.393 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:44:40.393 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:44:40.394 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:44:40.394 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:44:40.398 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:44:40.398 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:44:40.399 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:44:40.399 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:44:40.400 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:44:40.400 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:44:40.400 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:44:40.401 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:44:40.401 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:44:40.403 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:44:40.403 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:44:40.403 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:44:40.403 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:44:40.404 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:44:40.404 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:44:40.404 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:44:40.405 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:44:40.405 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:44:40.406 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:44:40.406 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:44:40.406 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:44:40.406 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:44:40.407 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:44:40.407 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:44:40.407 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:44:40.407 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:44:40.407 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:44:40.410 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:44:40.410 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:44:40.410 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:44:40.410 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:44:40.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:44:40.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:44:40.410 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:44:40.410 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:44:40.410 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:44:40.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:44:40.410 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:44:40.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:40.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:40.411 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:44:40.411 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:44:40.411 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:44:40.411 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:44:40.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:40.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:40.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:40.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:44:40.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:40.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:40.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:40.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:40.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:40.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:40.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:40.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:40.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:40.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:40.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:40.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:40.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:40.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:40.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:40.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:40.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:40.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:40.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:40.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:40.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:40.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:40.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:40.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:40.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:40.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:40.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:40.416 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:44:40.884 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:44:40.940 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:44:40.942 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:44:40.944 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:44:40.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:40.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:40.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:40.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:40.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:41.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:41.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:41.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:41.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:41.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:41.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:41.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:41.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:41.351 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:44:41.414 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:44:41.414 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:44:41.415 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:44:41.415 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:44:41.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:41.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:41.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:41.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:41.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:41.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:41.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:41.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:41.819 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:44:41.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:41.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:41.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:41.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:41.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:41.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:41.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:41.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:42.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:42.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:42.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:42.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:42.290 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:44:42.294 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:44:42.294 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:44:42.295 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:44:42.295 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:44:42.298 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:44:42.299 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:44:42.299 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:44:42.299 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:44:42.300 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:44:42.300 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:44:42.300 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:44:42.301 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=412 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:42.301 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=412 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:42.301 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=412 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:42.302 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=412 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:42.302 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=412 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:42.302 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=412 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:47.300 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:44:47.300 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:44:47.300 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:44:47.300 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:44:47.300 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:44:47.300 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:44:47.309 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:44:47.311 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:44:47.311 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:44:47.311 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:44:47.311 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:44:47.315 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:44:47.315 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:44:47.316 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:44:47.316 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:44:47.316 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:44:47.316 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:44:47.317 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:44:47.317 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:44:47.317 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:44:47.319 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:44:47.319 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:44:47.320 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:44:47.320 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:44:47.320 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:44:47.320 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:44:47.320 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:44:47.320 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:44:47.320 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:44:47.322 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:44:47.322 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:44:47.323 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:44:47.323 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:44:47.323 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:44:47.323 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:44:47.323 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:44:47.323 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:44:47.323 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:44:47.326 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:44:47.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:44:47.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:44:47.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:44:47.327 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:44:47.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:44:47.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:44:47.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:44:47.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:47.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:44:47.327 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:44:47.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:47.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:47.328 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:44:47.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:47.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:47.328 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:44:47.328 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:44:47.328 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:44:47.328 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:44:47.329 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:47.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:47.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:47.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:44:47.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:47.329 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:47.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:47.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:47.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:47.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:47.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:47.330 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:47.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:47.330 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:47.330 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:47.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:47.330 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:47.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:47.331 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:47.331 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:47.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:47.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:47.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:47.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:47.333 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:44:47.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:47.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:47.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:47.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:47.806 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:44:47.863 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:44:47.864 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:44:47.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:47.866 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:44:47.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:47.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:47.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:48.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:48.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:48.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:48.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:48.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:48.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:48.278 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:44:48.332 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:44:48.332 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:44:48.332 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:44:48.333 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:44:48.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:48.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:48.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:48.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:48.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:48.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:48.750 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:44:48.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:48.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:48.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:48.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:48.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:48.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:49.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:49.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:49.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:49.214 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:44:49.215 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:44:49.215 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:44:49.216 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:44:49.216 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:44:49.217 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:44:49.217 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:44:49.217 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:44:49.217 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:44:49.217 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:44:49.217 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:44:54.219 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:44:54.219 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:44:54.219 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:44:54.219 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:44:54.219 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:44:54.219 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:44:54.225 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:44:54.226 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:44:54.226 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:44:54.226 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:44:54.226 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:44:54.232 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:44:54.232 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:44:54.232 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:44:54.232 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:44:54.233 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:44:54.233 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:44:54.233 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:44:54.233 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:44:54.233 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:44:54.237 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:44:54.237 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:44:54.237 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:44:54.237 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:44:54.238 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:44:54.238 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:44:54.238 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:44:54.238 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:44:54.239 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:44:54.241 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:44:54.241 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:44:54.242 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:44:54.242 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:44:54.242 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:44:54.242 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:44:54.243 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:44:54.243 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:44:54.243 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:44:54.247 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:44:54.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:44:54.248 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:44:54.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:44:54.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:44:54.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:44:54.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:44:54.248 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:44:54.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:44:54.249 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:44:54.249 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:44:54.249 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:54.249 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:54.249 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:44:54.249 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:44:54.249 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:44:54.250 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:44:54.250 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:54.250 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:54.250 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:54.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:44:54.250 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:54.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:54.250 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:54.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:54.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:54.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:54.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:54.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:54.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:54.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:54.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:54.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:54.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:54.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:54.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:54.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:54.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:54.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:54.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:54.254 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:44:54.254 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:54.254 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:54.254 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:44:54.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:44:54.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:44:54.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:54.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:54.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:44:54.722 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:44:54.794 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:44:54.797 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:44:54.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:54.799 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:44:54.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:54.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:55.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:55.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:55.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:55.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:55.190 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:44:55.253 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:44:55.253 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:44:55.254 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:44:55.256 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:44:55.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:55.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:55.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:55.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:55.657 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:44:55.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:55.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:55.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:55.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:56.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:56.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:44:56.112 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:44:56.113 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:44:56.113 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:44:56.113 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:44:56.117 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:44:56.118 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:44:56.118 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:44:56.118 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:44:56.118 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:44:56.119 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:44:56.119 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:44:56.119 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=408 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:56.119 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=408 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:56.120 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=408 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:56.120 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=408 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:56.120 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=408 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:44:56.120 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=408 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:45:01.124 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:45:01.124 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:45:01.125 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:01.125 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:01.125 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:01.125 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:01.137 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:01.138 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:45:01.138 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:01.138 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:45:01.138 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:45:01.140 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:45:01.141 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:45:01.141 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:45:01.141 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:01.141 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:01.142 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:45:01.142 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:45:01.142 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:45:01.142 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:45:01.143 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:45:01.143 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:45:01.143 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:45:01.143 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:01.144 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:01.144 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:45:01.144 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:45:01.144 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:45:01.144 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:45:01.146 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:45:01.146 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:45:01.146 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:45:01.146 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:01.147 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:01.147 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:45:01.147 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:45:01.147 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:45:01.147 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:45:01.151 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:45:01.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:45:01.151 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:45:01.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:45:01.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:45:01.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:45:01.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:45:01.151 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:45:01.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:45:01.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:45:01.151 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:45:01.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:01.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:01.152 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:45:01.152 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:45:01.152 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:45:01.152 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:45:01.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:01.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:01.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:01.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:45:01.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:01.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:01.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:01.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:01.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:01.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:01.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:01.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:01.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:01.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:01.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:01.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:01.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:01.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:01.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:01.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:01.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:01.154 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:01.154 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:01.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:01.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:01.155 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:01.155 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:01.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:01.155 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:01.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:01.155 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:01.157 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:45:01.621 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:45:01.678 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:45:01.680 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:45:01.682 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:45:01.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:01.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:01.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:01.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:02.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:02.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:02.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:02.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:02.090 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:45:02.154 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:45:02.155 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:45:02.155 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:45:02.155 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:45:02.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:02.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:02.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:02.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:02.559 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:45:02.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:02.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:02.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:02.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:02.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:02.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:02.985 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:45:02.985 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:45:02.986 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:45:02.986 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:45:02.987 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:02.987 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:02.987 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:02.987 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:02.987 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:45:02.987 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:45:02.987 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:45:07.995 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:45:07.996 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:45:07.996 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:07.996 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:07.996 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:07.997 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:08.008 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:08.009 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:45:08.009 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:08.010 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:45:08.010 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:45:08.011 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:45:08.012 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:45:08.012 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:45:08.012 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:08.012 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:08.012 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:45:08.012 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:45:08.013 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:45:08.013 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:45:08.013 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:45:08.013 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:45:08.013 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:45:08.013 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:08.014 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:08.014 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:45:08.014 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:45:08.014 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:45:08.014 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:45:08.015 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:45:08.015 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:45:08.015 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:45:08.015 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:08.015 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:08.015 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:45:08.015 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:45:08.015 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:45:08.015 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:45:08.017 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:45:08.017 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:45:08.017 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:45:08.017 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:45:08.017 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:45:08.017 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:45:08.017 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:45:08.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:45:08.017 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:08.017 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:45:08.017 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:45:08.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:08.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:08.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:08.018 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:45:08.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:08.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:08.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:08.018 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:45:08.018 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:45:08.018 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:45:08.018 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:45:08.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:08.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:08.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:08.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:45:08.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:08.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:08.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:08.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:08.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:08.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:08.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:08.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:08.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:08.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:08.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:08.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:08.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:08.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:08.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:08.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:08.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:08.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:08.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:08.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:08.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:08.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:08.023 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:45:08.493 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:45:08.534 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:45:08.536 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:45:08.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:08.538 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:45:08.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:08.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:08.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:08.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:08.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:08.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:08.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:08.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:08.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:08.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:08.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:08.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:08.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:08.964 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:45:09.020 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:45:09.020 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:45:09.021 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:45:09.021 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:45:09.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:09.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:09.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:09.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:09.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:09.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:09.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:09.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:09.435 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:45:09.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:09.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:09.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:09.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:09.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:09.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:09.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:09.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:09.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:09.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:09.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:09.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:09.861 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:45:09.862 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:45:09.862 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:45:09.862 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:45:09.866 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:09.867 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:09.867 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:09.867 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:09.868 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:45:09.868 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:45:09.868 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:45:09.869 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=402 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:45:09.869 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=402 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:45:09.869 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=402 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:45:09.869 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=402 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:45:09.870 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=402 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:45:09.870 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=402 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:45:14.871 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:45:14.872 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:45:14.872 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:14.872 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:14.872 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:14.872 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:14.878 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:14.879 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:45:14.879 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:14.879 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:45:14.879 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:45:14.880 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:45:14.880 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:45:14.880 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:45:14.881 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:14.881 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:14.881 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:45:14.881 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:45:14.881 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:45:14.881 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:45:14.882 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:45:14.882 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:45:14.882 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:45:14.882 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:14.882 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:14.882 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:45:14.882 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:45:14.882 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:45:14.882 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:45:14.883 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:45:14.883 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:45:14.883 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:45:14.883 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:14.883 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:14.884 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:45:14.884 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:45:14.884 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:45:14.884 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:45:14.885 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:45:14.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:45:14.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:45:14.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:45:14.885 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:45:14.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:45:14.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:45:14.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:45:14.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:14.886 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:45:14.886 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:45:14.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:14.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:14.886 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:45:14.886 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:14.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:14.886 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:45:14.886 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:45:14.886 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:45:14.886 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:45:14.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:14.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:14.886 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:14.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:45:14.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:14.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:14.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:14.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:14.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:14.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:14.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:14.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:14.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:14.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:14.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:14.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:14.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:14.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:14.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:14.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:14.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:14.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:14.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:14.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:14.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:14.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:14.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:14.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:14.891 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:45:15.361 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:45:15.405 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:45:15.407 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:45:15.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:15.409 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:45:15.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:15.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:15.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:15.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:15.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:15.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:15.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:15.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:15.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:15.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:15.832 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:45:15.888 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:45:15.888 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:45:15.888 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:45:15.889 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:45:16.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:16.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:16.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:16.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:16.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:16.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:16.298 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:45:16.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:16.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:16.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:16.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:16.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:16.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:16.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:16.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:16.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:16.736 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:45:16.737 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:45:16.737 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:45:16.737 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:45:16.740 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:16.740 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:16.741 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:16.741 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:16.741 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:45:16.741 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:45:16.741 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:45:16.741 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=404 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:45:21.749 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:45:21.749 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:45:21.749 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:21.749 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:21.750 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:21.750 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:21.754 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:21.754 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:45:21.754 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:21.754 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:45:21.754 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:45:21.755 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:45:21.755 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:45:21.755 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:45:21.755 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:21.755 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:21.755 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:45:21.755 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:45:21.755 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:45:21.755 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:45:21.756 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:45:21.756 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:45:21.756 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:45:21.756 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:21.756 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:21.757 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:45:21.757 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:45:21.757 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:45:21.757 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:45:21.758 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:45:21.758 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:45:21.758 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:45:21.758 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:21.758 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:21.758 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:45:21.758 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:45:21.758 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:45:21.758 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:45:21.760 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:45:21.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:45:21.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:45:21.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:45:21.760 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:45:21.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:45:21.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:45:21.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:45:21.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:45:21.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:21.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:21.760 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:45:21.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:21.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:21.760 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:45:21.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:21.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:21.760 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:45:21.760 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:45:21.760 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:45:21.760 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:45:21.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:21.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:21.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:21.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:45:21.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:21.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:21.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:21.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:21.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:21.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:21.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:21.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:21.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:21.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:21.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:21.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:21.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:21.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:21.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:21.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:21.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:21.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:21.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:21.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:21.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:21.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:21.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:21.765 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:45:22.228 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:45:22.286 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:45:22.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.288 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:45:22.289 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:45:22.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:22.355 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:45:22.355 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:45:22.355 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:45:22.355 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:45:22.357 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:22.357 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:22.357 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:22.357 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:22.357 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:45:22.357 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:45:22.357 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:45:27.362 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:45:27.362 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:45:27.362 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:27.362 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:27.362 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:27.362 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:27.366 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:27.367 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:45:27.367 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:27.367 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:45:27.368 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:45:27.369 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:45:27.370 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:45:27.370 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:45:27.370 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:27.370 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:27.371 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:45:27.371 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:45:27.371 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:45:27.372 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:45:27.372 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:45:27.372 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:45:27.372 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:45:27.372 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:27.373 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:27.373 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:45:27.373 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:45:27.373 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:45:27.373 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:45:27.374 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:45:27.374 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:45:27.374 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:45:27.374 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:27.374 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:27.375 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:45:27.375 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:45:27.375 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:45:27.375 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:45:27.377 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:45:27.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:45:27.377 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:45:27.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:45:27.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:45:27.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:45:27.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:45:27.377 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:45:27.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:45:27.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:45:27.377 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:45:27.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:27.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:27.378 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:45:27.378 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:45:27.378 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:45:27.378 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:45:27.378 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:27.378 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:27.378 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:27.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:45:27.378 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:27.378 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:27.378 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:27.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:27.378 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:27.378 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:27.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:27.378 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:27.378 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:27.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:27.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:27.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:27.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:27.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:27.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:27.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:27.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:27.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:27.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:27.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:27.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:27.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:27.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:27.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:27.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:27.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:27.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:27.382 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:45:27.846 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:45:27.908 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:45:27.911 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:45:27.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.913 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:45:27.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:27.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:28.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:28.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:28.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:28.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:28.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:28.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:28.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:28.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:28.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:28.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:28.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:28.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:28.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:28.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:28.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:28.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:28.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:28.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:28.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:28.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:28.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:28.036 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:45:28.036 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:45:28.036 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:45:28.036 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:45:28.037 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:28.037 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:28.037 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:28.037 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:28.037 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:45:28.037 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:45:28.037 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:45:33.046 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:45:33.046 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:45:33.047 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:33.047 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:33.047 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:33.047 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:33.055 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:33.056 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:45:33.056 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:33.057 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:45:33.057 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:45:33.060 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:45:33.060 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:45:33.061 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:45:33.061 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:33.061 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:33.062 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:45:33.062 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:45:33.062 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:45:33.063 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:45:33.064 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:45:33.064 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:45:33.064 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:45:33.064 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:33.065 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:33.065 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:45:33.065 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:45:33.065 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:45:33.065 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:45:33.067 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:45:33.067 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:45:33.067 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:45:33.067 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:33.067 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:33.068 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:45:33.068 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:45:33.068 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:45:33.068 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:45:33.071 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:45:33.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:45:33.071 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:45:33.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:45:33.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:45:33.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:45:33.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:45:33.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:45:33.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:45:33.071 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:45:33.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:33.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:33.071 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:45:33.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:33.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:33.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:33.072 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:45:33.072 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:45:33.072 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:45:33.072 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:45:33.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:33.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:33.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:33.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:45:33.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:33.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:33.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:33.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:33.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:33.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:33.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:33.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:33.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:33.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:33.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:33.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:33.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:33.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:33.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:33.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:33.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:33.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:33.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:33.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:33.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:33.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:33.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:33.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:33.076 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:45:33.540 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:45:33.607 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:45:33.609 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:45:33.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.612 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:45:33.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:33.704 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:45:33.704 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:45:33.704 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:45:33.704 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:45:33.706 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:33.706 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:33.706 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:45:33.706 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:45:33.706 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:45:33.706 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:33.706 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:38.706 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:45:38.706 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:45:38.706 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:38.706 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:38.706 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:38.706 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:38.711 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:38.711 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:45:38.711 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:38.711 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:45:38.711 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:45:38.712 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:45:38.712 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:45:38.712 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:45:38.712 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:38.712 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:38.713 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:45:38.713 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:45:38.713 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:45:38.713 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:45:38.713 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:45:38.713 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:45:38.713 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:45:38.713 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:38.713 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:38.713 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:45:38.713 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:45:38.713 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:45:38.713 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:45:38.714 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:45:38.714 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:45:38.714 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:45:38.714 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:38.714 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:38.714 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:45:38.714 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:45:38.714 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:45:38.715 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:45:38.716 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:45:38.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:45:38.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:45:38.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:45:38.716 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:45:38.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:45:38.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:45:38.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:45:38.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:38.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:45:38.716 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:45:38.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:38.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:38.717 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:45:38.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:38.717 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:45:38.717 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:45:38.717 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:45:38.717 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:45:38.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:38.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:38.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:38.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:45:38.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:38.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:38.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:38.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:38.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:38.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:38.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:38.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:38.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:38.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:38.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:38.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:38.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:38.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:38.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:38.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:38.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:38.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:38.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:38.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:38.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:38.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:38.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:38.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:38.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:38.721 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:45:39.192 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:45:39.238 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:45:39.240 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:45:39.242 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:45:39.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:39.313 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:45:39.313 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:45:39.313 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:45:39.313 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:45:39.314 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:39.314 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:39.314 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:39.314 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:39.314 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:45:39.314 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:45:39.315 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:45:44.319 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:45:44.320 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:45:44.320 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:44.320 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:44.320 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:44.320 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:44.336 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:44.338 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:45:44.338 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:44.338 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:45:44.338 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:45:44.341 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:45:44.342 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:45:44.342 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:45:44.342 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:44.343 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:44.343 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:45:44.344 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:45:44.344 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:45:44.344 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:45:44.346 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:45:44.346 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:45:44.346 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:45:44.346 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:44.346 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:44.347 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:45:44.347 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:45:44.347 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:45:44.347 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:45:44.349 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:45:44.350 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:45:44.350 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:45:44.350 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:44.350 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:44.350 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:45:44.351 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:45:44.351 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:45:44.351 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:45:44.354 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:45:44.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:45:44.355 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:45:44.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:45:44.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:45:44.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:45:44.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:45:44.355 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:45:44.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:45:44.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:45:44.355 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:45:44.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:44.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:44.356 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:45:44.356 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:45:44.356 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:45:44.356 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:45:44.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:44.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:44.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:44.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:45:44.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:44.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:44.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:44.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:44.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:44.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:44.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:44.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:44.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:44.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:44.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:44.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:44.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:44.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:44.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:44.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:44.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:44.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:44.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:44.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:44.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:44.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:44.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:44.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:44.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:44.361 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:45:44.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:44.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:44.836 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:45:44.885 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:45:44.887 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:45:44.890 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:45:44.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:44.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:44.963 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:45:44.963 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:45:44.963 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:45:44.963 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:45:44.964 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:44.965 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:44.965 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:44.965 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:44.965 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:45:44.965 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:45:44.965 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:45:49.974 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:45:49.975 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:45:49.975 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:49.975 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:49.975 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:49.976 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:49.990 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:49.991 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:45:49.991 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:49.991 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:45:49.991 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:45:49.996 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:45:49.996 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:45:49.996 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:45:49.996 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:49.997 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:49.997 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:45:49.997 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:45:49.997 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:45:49.998 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:45:50.001 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:45:50.002 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:45:50.002 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:45:50.002 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:50.003 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:50.003 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:45:50.003 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:45:50.003 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:45:50.004 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:45:50.006 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:45:50.006 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:45:50.007 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:45:50.007 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:50.007 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:50.007 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:45:50.007 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:45:50.008 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:45:50.008 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:45:50.011 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:45:50.011 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:45:50.011 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:45:50.011 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:45:50.012 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:45:50.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:45:50.012 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:45:50.012 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:45:50.012 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:45:50.012 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:45:50.012 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:45:50.012 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:50.012 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:50.012 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:45:50.012 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:45:50.012 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:45:50.013 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:45:50.013 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:50.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:50.013 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:50.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:45:50.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:50.013 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:50.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:50.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:50.013 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:50.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:50.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:50.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:50.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:50.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:50.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:50.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:50.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:50.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:50.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:50.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:50.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:50.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:50.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:50.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:50.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:50.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:50.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:50.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:50.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:50.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:50.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:50.017 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:45:50.492 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:45:50.539 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:45:50.541 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:45:50.542 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:45:50.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:50.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:50.643 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:45:50.643 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:45:50.643 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:45:50.643 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:45:50.644 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:50.644 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:50.644 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:50.644 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:50.644 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:45:50.644 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:45:50.644 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:45:55.655 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:45:55.655 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:45:55.656 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:55.656 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:55.656 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:55.656 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:55.663 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:55.663 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:45:55.663 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:55.663 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:45:55.663 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:45:55.666 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:45:55.666 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:45:55.667 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:45:55.667 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:55.667 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:55.667 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:45:55.667 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:45:55.668 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:45:55.668 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:45:55.670 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:45:55.670 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:45:55.670 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:45:55.670 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:55.670 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:55.670 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:45:55.670 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:45:55.670 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:45:55.671 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:45:55.672 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:45:55.672 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:45:55.672 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:45:55.672 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:45:55.672 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:55.672 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:45:55.673 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:45:55.673 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:45:55.673 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:45:55.675 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:45:55.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:45:55.675 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:45:55.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:45:55.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:45:55.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:45:55.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:45:55.676 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:45:55.676 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:45:55.676 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:45:55.676 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:45:55.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:55.676 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:55.676 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:45:55.676 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:45:55.676 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:45:55.676 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:45:55.676 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:55.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:45:55.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:55.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:55.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:55.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:55.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:55.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:55.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:55.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:55.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:55.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:55.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:55.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:55.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:55.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:55.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:55.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:55.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:55.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:55.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:55.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:45:55.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:55.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:55.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:55.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:55.679 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:55.679 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:55.679 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:45:55.679 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:55.679 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:45:55.681 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:45:56.155 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:45:56.192 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:45:56.193 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:45:56.194 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:45:56.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:45:56.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:45:56.278 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:45:56.278 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:45:56.278 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:45:56.278 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:45:56.279 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:45:56.279 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:45:56.279 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:45:56.279 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:45:56.279 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:45:56.279 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:45:56.279 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:46:01.284 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:46:01.284 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:46:01.284 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:46:01.284 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:46:01.284 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:46:01.284 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:46:01.292 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:46:01.293 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:46:01.293 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:46:01.294 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:46:01.294 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:46:01.298 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:46:01.298 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:46:01.299 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:46:01.299 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:46:01.300 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:46:01.301 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:46:01.301 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:46:01.302 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:46:01.302 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:46:01.303 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:46:01.303 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:46:01.304 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:46:01.304 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:46:01.304 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:46:01.305 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:46:01.305 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:46:01.305 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:46:01.306 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:46:01.307 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:46:01.307 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:46:01.307 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:46:01.308 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:46:01.308 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:46:01.308 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:46:01.308 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:46:01.308 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:46:01.309 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:46:01.312 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:46:01.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:46:01.312 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:46:01.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:46:01.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:46:01.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:46:01.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:46:01.313 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:46:01.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:46:01.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:46:01.313 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:46:01.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:01.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:01.313 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:46:01.313 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:46:01.313 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:46:01.314 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:46:01.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:01.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:46:01.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:01.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:01.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:01.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:01.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:01.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:01.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:01.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:01.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:01.315 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:01.315 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:01.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:01.315 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:01.315 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:01.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:01.315 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:01.315 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:01.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:01.316 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:01.316 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:01.316 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:01.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:01.316 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:01.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:01.316 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:01.316 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:01.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:01.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:01.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:01.318 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:46:01.797 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:46:01.829 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:46:01.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:46:01.831 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:46:01.832 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:46:01.833 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:46:01.833 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:46:01.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:46:01.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:46:01.834 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:46:01.834 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:46:01.834 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:46:01.834 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:46:02.273 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:46:02.316 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:46:02.317 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:46:02.317 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:46:02.317 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:46:02.749 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:46:03.227 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:46:03.317 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:46:03.318 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:46:03.318 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:46:03.318 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:46:03.700 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:46:04.175 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:46:04.318 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:46:04.319 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:46:04.319 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:46:04.319 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:46:04.652 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:46:05.129 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:46:05.308 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:46:05.308 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:46:05.313 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:46:05.313 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:46:05.313 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:46:05.313 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:46:05.315 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:46:05.315 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:46:05.315 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:46:05.315 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:46:05.315 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:46:05.315 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:46:05.315 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:46:05.315 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=858 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:05.315 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=858 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:05.315 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=858 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:05.315 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=858 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:05.315 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=858 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:05.315 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=858 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:10.323 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:46:10.324 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:46:10.324 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:46:10.324 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:46:10.324 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:46:10.325 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:46:10.338 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:46:10.339 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:46:10.339 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:46:10.340 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:46:10.340 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:46:10.342 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:46:10.343 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:46:10.343 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:46:10.343 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:46:10.344 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:46:10.344 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:46:10.345 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:46:10.345 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:46:10.345 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:46:10.346 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:46:10.347 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:46:10.347 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:46:10.347 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:46:10.347 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:46:10.347 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:46:10.347 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:46:10.347 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:46:10.348 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:46:10.349 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:46:10.349 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:46:10.349 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:46:10.349 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:46:10.350 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:46:10.350 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:46:10.350 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:46:10.350 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:46:10.350 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:46:10.352 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:46:10.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:46:10.352 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:46:10.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:46:10.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:46:10.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:46:10.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:46:10.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:46:10.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:46:10.353 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:46:10.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:10.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:10.353 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:46:10.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:10.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:10.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:10.353 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:46:10.353 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:46:10.353 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:46:10.354 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:46:10.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:10.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:46:10.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:10.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:10.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:10.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:10.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:10.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:10.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:10.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:10.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:10.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:10.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:10.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:10.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:10.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:10.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:10.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:10.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:10.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:10.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:10.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:10.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:10.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:10.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:10.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:10.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:10.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:10.358 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:46:10.831 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:46:10.880 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:46:10.882 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:46:10.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:46:10.885 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:46:10.910 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:46:10.910 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:46:10.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:46:10.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:46:10.915 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:46:10.915 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:46:10.916 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:46:10.916 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:46:10.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 03:46:10.931 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:46:10.931 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:46:10.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:46:10.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:46:11.307 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:46:11.355 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:46:11.356 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:46:11.356 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:46:11.356 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:46:11.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:46:11.430 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:46:11.430 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:46:11.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:46:11.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:46:11.431 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:46:11.431 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:46:11.431 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:46:11.431 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:46:11.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:46:11.445 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:46:11.445 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:46:11.454 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:46:11.454 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:46:11.454 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:46:11.455 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:46:11.456 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:46:11.456 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:46:11.456 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:46:11.456 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:46:11.456 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:46:11.456 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:46:11.456 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:46:11.456 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=238 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:11.456 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=238 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:11.456 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=238 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:11.456 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=238 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:11.456 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=238 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:11.457 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=238 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:16.464 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:46:16.465 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:46:16.465 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:46:16.465 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:46:16.465 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:46:16.466 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:46:16.473 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:46:16.473 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:46:16.473 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:46:16.474 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:46:16.474 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:46:16.476 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:46:16.476 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:46:16.476 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:46:16.476 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:46:16.476 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:46:16.477 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:46:16.477 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:46:16.477 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:46:16.477 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:46:16.478 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:46:16.479 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:46:16.479 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:46:16.479 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:46:16.479 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:46:16.479 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:46:16.479 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:46:16.479 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:46:16.480 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:46:16.481 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:46:16.481 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:46:16.481 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:46:16.481 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:46:16.482 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:46:16.482 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:46:16.482 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:46:16.482 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:46:16.482 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:46:16.485 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:46:16.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:46:16.485 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:46:16.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:46:16.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:46:16.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:46:16.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:46:16.485 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:46:16.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:46:16.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:46:16.485 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:46:16.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:16.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:16.486 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:46:16.486 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:46:16.486 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:46:16.486 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:46:16.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:16.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:16.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:16.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:46:16.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:16.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:16.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:16.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:16.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:16.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:16.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:16.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:16.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:16.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:16.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:16.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:16.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:16.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:16.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:16.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:16.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:16.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:16.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:16.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:16.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:16.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:16.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:16.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:16.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:16.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:16.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:16.491 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:46:16.966 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:46:17.003 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:46:17.003 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:46:17.004 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:46:17.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:46:17.013 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:46:17.013 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:46:17.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:46:17.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:46:17.017 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:46:17.017 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:46:17.017 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:46:17.018 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:46:17.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 03:46:17.066 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:46:17.066 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:46:17.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:46:17.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:46:17.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:46:17.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:46:17.182 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:46:17.182 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:46:17.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:46:17.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:46:17.183 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:46:17.183 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:46:17.183 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:46:17.183 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:46:17.444 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:46:17.488 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:46:17.489 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:46:17.489 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:46:17.489 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:46:17.922 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:46:18.400 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:46:18.490 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:46:18.490 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:46:18.490 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:46:18.491 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:46:18.880 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:46:19.359 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-06 03:46:19.490 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:46:19.491 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:46:19.491 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:46:19.492 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:46:19.838 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-06 03:46:20.316 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-06 03:46:20.492 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:46:20.492 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:46:20.492 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:46:20.493 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:46:20.795 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-06 03:46:21.273 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-06 03:46:21.492 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:46:21.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:46:21.493 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:46:21.493 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:46:21.751 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-06 03:46:22.229 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-06 03:46:22.707 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-06 03:46:23.185 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-06 03:46:23.664 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-06 03:46:24.143 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-06 03:46:24.618 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-06 03:46:25.097 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-06 03:46:25.575 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-06 03:46:26.055 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-06 03:46:26.535 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-06 03:46:27.014 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-06 03:46:27.493 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-06 03:46:27.969 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-06 03:46:28.447 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-06 03:46:28.925 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-06 03:46:29.404 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-06 03:46:29.881 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-06 03:46:30.358 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-06 03:46:30.837 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-06 03:46:31.316 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-06 03:46:31.795 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-06 03:46:32.274 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-06 03:46:32.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:46:32.572 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:46:32.572 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:46:32.573 [WARNING] transceiver.py:257 (MS@172.18.59.22:6700) RX TRXD message (fn=3432 tn=6 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:32.573 [WARNING] transceiver.py:257 (MS@172.18.59.22:6700) RX TRXD message (fn=3432 tn=7 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:32.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:46:32.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:46:32.589 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:46:32.590 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:46:32.590 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:46:32.590 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:46:32.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:46:32.601 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:46:32.601 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:46:32.606 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:46:32.606 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:46:32.606 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:46:32.606 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:46:32.610 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:46:32.610 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:46:32.610 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:46:32.610 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:46:32.611 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:46:32.611 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:46:32.611 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:46:32.612 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3440 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:32.612 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3440 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:32.612 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3440 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:32.612 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3440 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:32.612 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3440 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:32.613 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=3440 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:37.615 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:46:37.615 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:46:37.615 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:46:37.615 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:46:37.615 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:46:37.615 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:46:37.622 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:46:37.623 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:46:37.623 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:46:37.624 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:46:37.624 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:46:37.625 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:46:37.626 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:46:37.626 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:46:37.626 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:46:37.627 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:46:37.627 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:46:37.627 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:46:37.627 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:46:37.628 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:46:37.628 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:46:37.628 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:46:37.628 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:46:37.629 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:46:37.629 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:46:37.629 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:46:37.629 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:46:37.629 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:46:37.629 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:46:37.630 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:46:37.630 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:46:37.630 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:46:37.630 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:46:37.630 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:46:37.630 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:46:37.631 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:46:37.631 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:46:37.631 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:46:37.633 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:46:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:46:37.633 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:46:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:46:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:46:37.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:46:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:46:37.633 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:46:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:46:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:46:37.633 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:46:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:37.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:37.633 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:46:37.633 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:46:37.633 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:46:37.633 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:46:37.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:37.634 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:37.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:46:37.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:37.634 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:37.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:37.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:37.634 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:37.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:37.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:37.634 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:37.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:37.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:37.634 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:37.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:37.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:37.634 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:37.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:37.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:37.634 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:37.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:37.634 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:37.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:37.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:37.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:37.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:37.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:37.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:37.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:37.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:37.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:37.638 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:46:38.110 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:46:38.159 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:46:38.162 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:46:38.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:46:38.165 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:46:38.183 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:46:38.183 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:46:38.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:46:38.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:46:38.189 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:46:38.189 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:46:38.189 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:46:38.189 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:46:38.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 03:46:38.211 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:46:38.211 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:46:38.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:46:38.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:46:38.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:46:38.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 03:46:38.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:46:38.505 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:46:38.505 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:46:38.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:46:38.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:46:38.506 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:46:38.506 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:46:38.506 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:46:38.506 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:46:38.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:46:38.530 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:46:38.530 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:46:38.538 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:46:38.538 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:46:38.539 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:46:38.539 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:46:38.542 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:46:38.543 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:46:38.543 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:46:38.543 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:46:38.544 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:46:38.544 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:46:38.544 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:46:38.544 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=197 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:38.544 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=197 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:38.545 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=197 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:38.545 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=197 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:38.545 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=197 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:38.545 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=197 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:43.544 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:46:43.544 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:46:43.544 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:46:43.544 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:46:43.544 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:46:43.544 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:46:43.556 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:46:43.557 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:46:43.557 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:46:43.557 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:46:43.557 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:46:43.559 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:46:43.559 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:46:43.559 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:46:43.560 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:46:43.560 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:46:43.560 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:46:43.560 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:46:43.560 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:46:43.560 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:46:43.562 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:46:43.562 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:46:43.562 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:46:43.562 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:46:43.562 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:46:43.562 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:46:43.562 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:46:43.563 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:46:43.563 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:46:43.564 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:46:43.565 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:46:43.565 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:46:43.565 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:46:43.565 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:46:43.565 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:46:43.566 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:46:43.566 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:46:43.566 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:46:43.570 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:46:43.570 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:46:43.570 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:46:43.571 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:46:43.571 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:46:43.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:46:43.571 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:46:43.571 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:46:43.571 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:46:43.571 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:46:43.571 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:46:43.571 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:43.572 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:43.572 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.59.20:5700) Recv POWERON CMD
2026-03-06 03:46:43.572 [INFO] ctrl_if_trx.py:109 (BTS@172.18.59.20:5700) Starting transceiver...
2026-03-06 03:46:43.572 [INFO] transceiver.py:243 Starting clock generator
2026-03-06 03:46:43.572 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-06 03:46:43.572 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:43.572 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:43.573 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:43.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETRXGAIN
2026-03-06 03:46:43.573 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:43.573 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:43.573 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:43.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:43.573 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:43.573 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:43.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:43.573 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:43.574 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:43.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:43.574 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:43.574 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:43.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:43.574 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:43.574 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:43.574 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:43.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:43.577 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-06 03:46:43.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:43.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:43.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:43.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:43.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:43.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:43.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:43.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETSLOT
2026-03-06 03:46:43.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:43.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:44.050 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-06 03:46:44.102 [DEBUG] fake_trx.py:278 (BTS@172.18.59.20:5700) Recv FAKE_TOA cmd
2026-03-06 03:46:44.104 [DEBUG] fake_trx.py:297 (BTS@172.18.59.20:5700) Recv FAKE_RSSI cmd
2026-03-06 03:46:44.106 [DEBUG] fake_trx.py:322 (BTS@172.18.59.20:5700) Recv FAKE_CI cmd
2026-03-06 03:46:44.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:46:44.133 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:46:44.133 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:46:44.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:46:44.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:46:44.138 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:46:44.139 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:46:44.139 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:46:44.139 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:46:44.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD HANDOVER
2026-03-06 03:46:44.197 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:46:44.198 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:46:44.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:46:44.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:46:44.523 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-06 03:46:44.575 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:46:44.576 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:46:44.576 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:46:44.576 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:46:44.989 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-06 03:46:45.461 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-06 03:46:45.577 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:46:45.577 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:46:45.577 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:46:45.577 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:46:45.930 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-06 03:46:46.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:46:46.205 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:46:46.205 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:46:46.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD ECHO
2026-03-06 03:46:46.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.59.22:6700) Ignore CMD SETSLOT
2026-03-06 03:46:46.221 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.59.22:6700) Recv RXTUNE cmd
2026-03-06 03:46:46.221 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.59.22:6700) Recv TXTUNE cmd
2026-03-06 03:46:46.221 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.59.22:6700) Recv POWERON CMD
2026-03-06 03:46:46.221 [INFO] ctrl_if_trx.py:109 (MS@172.18.59.22:6700) Starting transceiver...
2026-03-06 03:46:46.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD NOHANDOVER
2026-03-06 03:46:46.259 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.59.22:6700) Recv POWEROFF cmd
2026-03-06 03:46:46.259 [INFO] ctrl_if_trx.py:117 (MS@172.18.59.22:6700) Stopping transceiver...
2026-03-06 03:46:46.266 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd
2026-03-06 03:46:46.267 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:46:46.267 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:46:46.267 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:46:46.270 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:46:46.271 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:46:46.271 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:46:46.271 [INFO] transceiver.py:246 Stopping clock generator
2026-03-06 03:46:46.272 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:46:46.272 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:46:46.272 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:46:46.272 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=586 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:46.273 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=586 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:46.273 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=586 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:46.273 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=586 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:46.273 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=586 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:46.273 [WARNING] transceiver.py:257 (BTS@172.18.59.20:5700) RX TRXD message (ver=1 fn=586 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-06 03:46:51.275 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.59.20:5700) Recv POWEROFF cmd
2026-03-06 03:46:51.275 [INFO] ctrl_if_trx.py:117 (BTS@172.18.59.20:5700) Stopping transceiver...
2026-03-06 03:46:51.275 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:46:51.275 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:46:51.275 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:46:51.276 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:46:51.283 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.59.20:5700) Recv RFMUTE cmd
2026-03-06 03:46:51.283 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:46:51.284 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.59.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:46:51.284 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.59.20:5700) Recv SETFORMAT cmd
2026-03-06 03:46:51.284 [INFO] ctrl_if_trx.py:201 (BTS@172.18.59.20:5700) TRXD header version 1 -> 1
2026-03-06 03:46:51.286 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.59.20:5700/1) Recv RXTUNE cmd
2026-03-06 03:46:51.287 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.59.20:5700/1) Recv TXTUNE cmd
2026-03-06 03:46:51.287 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:46:51.287 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.59.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:46:51.288 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.59.20:5700/1) Recv RFMUTE cmd
2026-03-06 03:46:51.289 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.59.20:5700/1) Recv NOMTXPOWER cmd
2026-03-06 03:46:51.289 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.59.20:5700/1) Recv SETFORMAT cmd
2026-03-06 03:46:51.289 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.59.20:5700/1) TRXD header version 1 -> 1
2026-03-06 03:46:51.289 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.59.20:5700/1) Recv SETPOWER cmd
2026-03-06 03:46:51.290 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.59.20:5700/2) Recv RXTUNE cmd
2026-03-06 03:46:51.290 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.59.20:5700/2) Recv TXTUNE cmd
2026-03-06 03:46:51.291 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:46:51.291 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.59.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:46:51.291 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.59.20:5700/2) Recv RFMUTE cmd
2026-03-06 03:46:51.291 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.59.20:5700/2) Recv NOMTXPOWER cmd
2026-03-06 03:46:51.292 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.59.20:5700/2) Recv SETFORMAT cmd
2026-03-06 03:46:51.292 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.59.20:5700/2) TRXD header version 1 -> 1
2026-03-06 03:46:51.292 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.59.20:5700/2) Recv SETPOWER cmd
2026-03-06 03:46:51.293 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.59.20:5700/3) Recv RXTUNE cmd
2026-03-06 03:46:51.293 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.59.20:5700/3) Recv TXTUNE cmd
2026-03-06 03:46:51.293 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:46:51.293 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.59.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-06 03:46:51.293 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.59.20:5700/3) Recv RFMUTE cmd
2026-03-06 03:46:51.294 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.59.20:5700/3) Recv NOMTXPOWER cmd
2026-03-06 03:46:51.294 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.59.20:5700/3) Recv SETFORMAT cmd
2026-03-06 03:46:51.294 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.59.20:5700/3) TRXD header version 1 -> 1
2026-03-06 03:46:51.294 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.59.20:5700/3) Recv SETPOWER cmd
2026-03-06 03:46:51.297 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.59.20:5700) Recv RXTUNE cmd
2026-03-06 03:46:51.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETTSC
2026-03-06 03:46:51.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETTSC
2026-03-06 03:46:51.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETTSC
2026-03-06 03:46:51.298 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.59.20:5700) Recv TXTUNE cmd
2026-03-06 03:46:51.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETRXGAIN
2026-03-06 03:46:51.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETRXGAIN
2026-03-06 03:46:51.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.59.20:5700) Ignore CMD SETTSC
2026-03-06 03:46:51.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:51.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETRXGAIN
2026-03-06 03:46:51.298 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.59.20:5700) Recv NOMTXPOWER cmd
2026-03-06 03:46:51.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.59.20:5700/1) Ignore CMD SETSLOT
2026-03-06 03:46:51.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.59.20:5700/2) Ignore CMD SETSLOT
2026-03-06 03:46:51.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.59.20:5700/3) Ignore CMD SETSLOT
2026-03-06 03:46:51.298 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.59.20:5700) Recv SETPOWER cmd